DE602006001442D1 - Datenprotokoll mit flexibler Breite - Google Patents
Datenprotokoll mit flexibler BreiteInfo
- Publication number
- DE602006001442D1 DE602006001442D1 DE602006001442T DE602006001442T DE602006001442D1 DE 602006001442 D1 DE602006001442 D1 DE 602006001442D1 DE 602006001442 T DE602006001442 T DE 602006001442T DE 602006001442 T DE602006001442 T DE 602006001442T DE 602006001442 D1 DE602006001442 D1 DE 602006001442D1
- Authority
- DE
- Germany
- Prior art keywords
- data protocol
- flexible width
- flexible
- width
- protocol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69814905P | 2005-07-11 | 2005-07-11 | |
US11/374,663 US7441064B2 (en) | 2005-07-11 | 2006-03-13 | Flexible width data protocol |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006001442D1 true DE602006001442D1 (de) | 2008-07-24 |
Family
ID=37192470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006001442T Active DE602006001442D1 (de) | 2005-07-11 | 2006-04-03 | Datenprotokoll mit flexibler Breite |
Country Status (4)
Country | Link |
---|---|
US (1) | US7441064B2 (de) |
EP (1) | EP1750205B1 (de) |
DE (1) | DE602006001442D1 (de) |
TW (1) | TWI320888B (de) |
Families Citing this family (39)
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US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
KR101318116B1 (ko) | 2005-06-24 | 2013-11-14 | 구글 인코포레이티드 | 집적 메모리 코어 및 메모리 인터페이스 회로 |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8130560B1 (en) * | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8438328B2 (en) * | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20070239922A1 (en) * | 2005-12-09 | 2007-10-11 | Horigan John W | Technique for link reconfiguration |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US8085858B2 (en) * | 2007-02-07 | 2011-12-27 | Valens Semiconductor Ltd. | Power saving techniques for a partial functionality communication link |
US9426006B2 (en) * | 2007-02-07 | 2016-08-23 | Valens Semiconductor Ltd. | Low power partial functionality communication link |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
EP2441007A1 (de) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programmierung von dimm-abschlusswiderstandswerten |
US20140325105A1 (en) * | 2013-04-26 | 2014-10-30 | Advanced Micro Devices, Inc. | Memory system components for split channel architecture |
US9454419B2 (en) | 2013-07-18 | 2016-09-27 | Advanced Micro Devices, Inc. | Partitionable data bus |
WO2015006946A1 (en) * | 2013-07-18 | 2015-01-22 | Advanced Micro Devices, Inc. | Partitionable data bus |
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JP2004240713A (ja) | 2003-02-06 | 2004-08-26 | Matsushita Electric Ind Co Ltd | データ転送方法及びデータ転送装置 |
US7206865B2 (en) | 2003-03-28 | 2007-04-17 | Intel Corporation | Apparatus and method for combining writes to I/O |
US20040199723A1 (en) | 2003-04-03 | 2004-10-07 | Shelor Charles F. | Low-power cache and method for operating same |
US7188208B2 (en) | 2004-09-07 | 2007-03-06 | Intel Corporation | Side-by-side inverted memory address and command buses |
-
2006
- 2006-03-13 US US11/374,663 patent/US7441064B2/en active Active
- 2006-04-03 EP EP06251866A patent/EP1750205B1/de active Active
- 2006-04-03 DE DE602006001442T patent/DE602006001442D1/de active Active
- 2006-07-11 TW TW095125220A patent/TWI320888B/zh active
Also Published As
Publication number | Publication date |
---|---|
US20070011387A1 (en) | 2007-01-11 |
EP1750205B1 (de) | 2008-06-11 |
EP1750205A1 (de) | 2007-02-07 |
TW200703009A (en) | 2007-01-16 |
US7441064B2 (en) | 2008-10-21 |
TWI320888B (en) | 2010-02-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |