DE602006001442D1 - Datenprotokoll mit flexibler Breite - Google Patents

Datenprotokoll mit flexibler Breite

Info

Publication number
DE602006001442D1
DE602006001442D1 DE602006001442T DE602006001442T DE602006001442D1 DE 602006001442 D1 DE602006001442 D1 DE 602006001442D1 DE 602006001442 T DE602006001442 T DE 602006001442T DE 602006001442 T DE602006001442 T DE 602006001442T DE 602006001442 D1 DE602006001442 D1 DE 602006001442D1
Authority
DE
Germany
Prior art keywords
data protocol
flexible width
flexible
width
protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006001442T
Other languages
English (en)
Inventor
Darius D Gaskins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE602006001442D1 publication Critical patent/DE602006001442D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3253Power saving in bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Microcomputers (AREA)
DE602006001442T 2005-07-11 2006-04-03 Datenprotokoll mit flexibler Breite Active DE602006001442D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69814905P 2005-07-11 2005-07-11
US11/374,663 US7441064B2 (en) 2005-07-11 2006-03-13 Flexible width data protocol

Publications (1)

Publication Number Publication Date
DE602006001442D1 true DE602006001442D1 (de) 2008-07-24

Family

ID=37192470

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006001442T Active DE602006001442D1 (de) 2005-07-11 2006-04-03 Datenprotokoll mit flexibler Breite

Country Status (4)

Country Link
US (1) US7441064B2 (de)
EP (1) EP1750205B1 (de)
DE (1) DE602006001442D1 (de)
TW (1) TWI320888B (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
KR101318116B1 (ko) 2005-06-24 2013-11-14 구글 인코포레이티드 집적 메모리 코어 및 메모리 인터페이스 회로
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8130560B1 (en) * 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8438328B2 (en) * 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US20070239922A1 (en) * 2005-12-09 2007-10-11 Horigan John W Technique for link reconfiguration
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8085858B2 (en) * 2007-02-07 2011-12-27 Valens Semiconductor Ltd. Power saving techniques for a partial functionality communication link
US9426006B2 (en) * 2007-02-07 2016-08-23 Valens Semiconductor Ltd. Low power partial functionality communication link
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten
US20140325105A1 (en) * 2013-04-26 2014-10-30 Advanced Micro Devices, Inc. Memory system components for split channel architecture
US9454419B2 (en) 2013-07-18 2016-09-27 Advanced Micro Devices, Inc. Partitionable data bus
WO2015006946A1 (en) * 2013-07-18 2015-01-22 Advanced Micro Devices, Inc. Partitionable data bus

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796232A (en) 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US5255378A (en) 1989-04-05 1993-10-19 Intel Corporation Method of transferring burst data in a microprocessor
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
US5640517A (en) 1993-06-22 1997-06-17 Dell Usa, L.P. Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order
US5561780A (en) 1993-12-30 1996-10-01 Intel Corporation Method and apparatus for combining uncacheable write data into cache-line-sized write buffers
US5644788A (en) 1994-10-28 1997-07-01 Cyrix Corporation Burst transfers using an ascending or descending only burst ordering
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
EP0782079A1 (de) 1995-12-18 1997-07-02 Texas Instruments Incorporated Stoss-Zugriff in Datenverarbeitungssystemen
US5960453A (en) 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
US5901298A (en) 1996-10-07 1999-05-04 Intel Corporation Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM
US5835741A (en) 1996-12-31 1998-11-10 Compaq Computer Corporation Bus-to-bus bridge in computer system, with fast burst memory range
US5919254A (en) * 1997-06-25 1999-07-06 Intel Corporation Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
US5915126A (en) 1997-08-12 1999-06-22 International Business Machines Corporation Computer system memory controller and method of burst data ordering translation
US5944806A (en) 1997-09-26 1999-08-31 Hewlett-Packard Company Microprocessor with versatile addressing
US6012116A (en) 1997-12-31 2000-01-04 Sun Microsystems, Inc. Apparatus and method for controlling data, address, and enable buses within a microprocessor
US6275904B1 (en) 1998-03-31 2001-08-14 Intel Corporation Cache pollution avoidance instructions
US6356270B2 (en) 1998-03-31 2002-03-12 Intel Corporation Efficient utilization of write-combining buffers
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6311245B1 (en) 1998-06-05 2001-10-30 Micron Technology, Inc. Method for time multiplexing a low-speed and a high-speed bus over shared signal lines of a physical bus
US6434654B1 (en) * 1999-03-26 2002-08-13 Koninklijke Philips Electronics N.V. System bus with a variable width selectivity configurable at initialization
US6405285B1 (en) 1999-06-25 2002-06-11 International Business Machines Corporation Layered local cache mechanism with split register load bus and cache load bus
US6505259B1 (en) 1999-08-27 2003-01-07 Intel Corporation Reordering of burst data transfers across a host bridge
US6587862B1 (en) 1999-09-07 2003-07-01 Spectral Logic Design Apparatus and method for direct digital frequency synthesis
US6523109B1 (en) 1999-10-25 2003-02-18 Advanced Micro Devices, Inc. Store queue multimatch detection
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
US6671752B1 (en) 2000-08-28 2003-12-30 International Business Machines Corporation Method and apparatus for bus optimization in a PLB system
US6721813B2 (en) 2001-01-30 2004-04-13 Advanced Micro Devices, Inc. Computer system implementing a system and method for tracking the progress of posted write transactions
US6742160B2 (en) 2001-02-14 2004-05-25 Intel Corporation Checkerboard parity techniques for a multi-pumped bus
US20030088799A1 (en) 2001-11-05 2003-05-08 Bodas Devadatta V. Method and apparatus for regulation of electrical component temperature and power consumption rate through bus width reconfiguration
US6775759B2 (en) 2001-12-07 2004-08-10 Micron Technology, Inc. Sequential nibble burst ordering for data
US6747657B2 (en) 2001-12-31 2004-06-08 Intel Corporation Depth write disable for zone rendering
JP2004240713A (ja) 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd データ転送方法及びデータ転送装置
US7206865B2 (en) 2003-03-28 2007-04-17 Intel Corporation Apparatus and method for combining writes to I/O
US20040199723A1 (en) 2003-04-03 2004-10-07 Shelor Charles F. Low-power cache and method for operating same
US7188208B2 (en) 2004-09-07 2007-03-06 Intel Corporation Side-by-side inverted memory address and command buses

Also Published As

Publication number Publication date
US20070011387A1 (en) 2007-01-11
EP1750205B1 (de) 2008-06-11
EP1750205A1 (de) 2007-02-07
TW200703009A (en) 2007-01-16
US7441064B2 (en) 2008-10-21
TWI320888B (en) 2010-02-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition