DE602004017113D1 - Mikroprozessor und Vorrichtung zum Durchführen einer spekulativen Ladeoperation aus einem Stapelspeichercache - Google Patents
Mikroprozessor und Vorrichtung zum Durchführen einer spekulativen Ladeoperation aus einem StapelspeichercacheInfo
- Publication number
- DE602004017113D1 DE602004017113D1 DE602004017113T DE602004017113T DE602004017113D1 DE 602004017113 D1 DE602004017113 D1 DE 602004017113D1 DE 602004017113 T DE602004017113 T DE 602004017113T DE 602004017113 T DE602004017113 T DE 602004017113T DE 602004017113 D1 DE602004017113 D1 DE 602004017113D1
- Authority
- DE
- Germany
- Prior art keywords
- microprocessor
- load operation
- stack cache
- speculative load
- speculative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/451—Stack data
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/759,564 US7139877B2 (en) | 2003-01-16 | 2004-01-16 | Microprocessor and apparatus for performing speculative load operation from a stack memory cache |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602004017113D1 true DE602004017113D1 (de) | 2008-11-27 |
Family
ID=34620721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602004017113T Active DE602004017113D1 (de) | 2004-01-16 | 2004-08-05 | Mikroprozessor und Vorrichtung zum Durchführen einer spekulativen Ladeoperation aus einem Stapelspeichercache |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7139877B2 (de) |
| EP (1) | EP1555616B1 (de) |
| CN (1) | CN1303536C (de) |
| DE (1) | DE602004017113D1 (de) |
| TW (1) | TWI249673B (de) |
Families Citing this family (29)
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| JP3739797B2 (ja) * | 1995-10-06 | 2006-01-25 | パトリオット サイエンティフィック コーポレイション | 縮小命令セット・コンピューター・マイクロプロセッサーの構造 |
| US6615300B1 (en) * | 2000-06-19 | 2003-09-02 | Transmeta Corporation | Fast look-up of indirect branch destination in a dynamic translation system |
| GB2399899B (en) * | 2003-03-27 | 2005-06-22 | Micron Technology Inc | Active memory command engine and method |
| US7073023B2 (en) * | 2003-05-05 | 2006-07-04 | Lsi Logic Corporation | Method for minimizing RAID 0 data transfer rate variability |
| CN100377115C (zh) * | 2005-11-11 | 2008-03-26 | 中国科学院计算技术研究所 | 适用于上下文切换的栈高速缓冲存储器及缓冲存储方法 |
| CN100428200C (zh) * | 2006-12-28 | 2008-10-22 | 北京时代民芯科技有限公司 | 一种片上指令cache的实现方法 |
| US8751747B2 (en) * | 2008-02-26 | 2014-06-10 | International Business Machines Corporation | Management of cache replacement status in cache memory |
| US7853827B2 (en) * | 2008-08-29 | 2010-12-14 | International Business Machines Corporation | Isotropic processor |
| WO2011002436A1 (en) * | 2009-06-29 | 2011-01-06 | Hewlett-Packard Development Company, L.P. | Hypervisor-based management of local and remote virtual memory pages |
| KR101283469B1 (ko) * | 2009-08-31 | 2013-07-12 | 한국전자통신연구원 | 프로세서 명령어의 메모리 액세스 방법 및 장치 |
| US8359528B2 (en) * | 2010-07-23 | 2013-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Parity look-ahead scheme for tag cache memory |
| US8555026B2 (en) | 2010-09-06 | 2013-10-08 | Lsi Corporation | Methods and systems for storing variable width stack elements in a single memory stack |
| US8838935B2 (en) * | 2010-09-24 | 2014-09-16 | Intel Corporation | Apparatus, method, and system for implementing micro page tables |
| US20120079248A1 (en) * | 2010-09-24 | 2012-03-29 | Combs Jonathan D | Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines |
| US20120151232A1 (en) * | 2010-12-12 | 2012-06-14 | Fish Iii Russell Hamilton | CPU in Memory Cache Architecture |
| US9110778B2 (en) | 2012-11-08 | 2015-08-18 | International Business Machines Corporation | Address generation in an active memory device |
| CN104699627B (zh) * | 2013-12-06 | 2019-05-07 | 上海芯豪微电子有限公司 | 一种缓存系统和方法 |
| US9418018B2 (en) * | 2013-12-31 | 2016-08-16 | Samsung Electronics Co., Ltd. | Efficient fill-buffer data forwarding supporting high frequencies |
| US9940262B2 (en) * | 2014-09-19 | 2018-04-10 | Apple Inc. | Immediate branch recode that handles aliasing |
| CN104572499B (zh) * | 2014-12-30 | 2017-07-11 | 杭州中天微系统有限公司 | 一种数据高速缓存的访问装置 |
| CN106528450B (zh) * | 2016-10-27 | 2019-09-17 | 上海兆芯集成电路有限公司 | 数据预先提取方法及使用此方法的装置 |
| US11194583B2 (en) * | 2019-10-21 | 2021-12-07 | Advanced Micro Devices, Inc. | Speculative execution using a page-level tracked load order queue |
| US11733972B2 (en) | 2020-10-06 | 2023-08-22 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address |
| US11907369B2 (en) | 2020-08-27 | 2024-02-20 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception |
| US11797673B2 (en) | 2020-08-27 | 2023-10-24 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception |
| US11868469B2 (en) | 2020-08-27 | 2024-01-09 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception |
| US11734426B2 (en) * | 2020-10-06 | 2023-08-22 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location |
| US11853424B2 (en) | 2020-10-06 | 2023-12-26 | Ventana Micro Systems Inc. | Processor that mitigates side channel attacks by refraining from allocating an entry in a data TLB for a missing load address when the load address misses both in a data cache memory and in the data TLB and the load address specifies a location without a valid address translation or without permission to read from the location |
| US11624831B2 (en) * | 2021-06-09 | 2023-04-11 | Suteng Innovation Technology Co., Ltd. | Obstacle detection method and apparatus and storage medium |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3401376A (en) * | 1965-11-26 | 1968-09-10 | Burroughs Corp | Central processor |
| US3810117A (en) * | 1972-10-20 | 1974-05-07 | Ibm | Stack mechanism for a data processor |
| US5043870A (en) * | 1982-02-24 | 1991-08-27 | At&T Bell Laboratories | Computer with automatic mapping of memory contents into machine registers during program execution |
| GB2260429B (en) | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
| US5500950A (en) * | 1993-01-29 | 1996-03-19 | Motorola, Inc. | Data processor with speculative data transfer and address-free retry |
| US6151661A (en) * | 1994-03-03 | 2000-11-21 | International Business Machines Corporation | Cache memory storage space management system and method |
| US5960487A (en) | 1994-03-16 | 1999-10-05 | Hawkins; Robert D. | Dry toilet |
| US5751990A (en) * | 1994-04-26 | 1998-05-12 | International Business Machines Corporation | Abridged virtual address cache directory |
| KR970029072A (ko) | 1995-11-17 | 1997-06-26 | 김주용 | 이중 디렉토리 가상 캐쉬 및 그 제어 방법 |
| US6038643A (en) * | 1996-01-24 | 2000-03-14 | Sun Microsystems, Inc. | Stack management unit and method for a processor having a stack |
| WO1997027539A1 (en) * | 1996-01-24 | 1997-07-31 | Sun Microsystems, Inc. | Methods and apparatuses for stack caching |
| US5930820A (en) * | 1996-03-18 | 1999-07-27 | Advanced Micro Devices, Inc. | Data cache and method using a stack memory for storing stack data separate from cache line storage |
| US5835968A (en) * | 1996-04-17 | 1998-11-10 | Advanced Micro Devices, Inc. | Apparatus for providing memory and register operands concurrently to functional units |
| US5953741A (en) * | 1996-11-27 | 1999-09-14 | Vlsi Technology, Inc. | Stack cache for stack-based processor and method thereof |
| US5956752A (en) * | 1996-12-16 | 1999-09-21 | Intel Corporation | Method and apparatus for accessing a cache using index prediction |
| US6009499A (en) * | 1997-03-31 | 1999-12-28 | Sun Microsystems, Inc | Pipelined stack caching circuit |
| JPH11212788A (ja) * | 1998-01-28 | 1999-08-06 | Toshiba Corp | プロセッサのデータ供給装置 |
| US6275903B1 (en) * | 1998-04-22 | 2001-08-14 | Sun Microsystems, Inc. | Stack cache miss handling |
| US6496902B1 (en) | 1998-12-31 | 2002-12-17 | Cray Inc. | Vector and scalar data cache for a vector multiprocessor |
| US6425055B1 (en) * | 1999-02-24 | 2002-07-23 | Intel Corporation | Way-predicting cache memory |
| DE10102202A1 (de) * | 2001-01-18 | 2002-08-08 | Infineon Technologies Ag | Mikroprozessorschaltung für tragbare Datenträger |
| US7200740B2 (en) * | 2001-05-04 | 2007-04-03 | Ip-First, Llc | Apparatus and method for speculatively performing a return instruction in a microprocessor |
| US6622211B2 (en) * | 2001-08-15 | 2003-09-16 | Ip-First, L.L.C. | Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty |
| TW556212B (en) | 2002-01-14 | 2003-10-01 | Ip First Llc | L2 cache LRU generation method and apparatus |
| US6671196B2 (en) * | 2002-02-28 | 2003-12-30 | Sun Microsystems, Inc. | Register stack in cache memory |
| CN100419669C (zh) * | 2002-06-13 | 2008-09-17 | 中颖电子(上海)有限公司 | 精简功能及指令数量的微处理器 |
| US7467377B2 (en) | 2002-10-22 | 2008-12-16 | Intel Corporation | Methods and apparatus for compiler managed first cache bypassing |
| WO2004075512A1 (en) * | 2003-02-18 | 2004-09-02 | Nortel Networks Limited | Discovery of an application server in an ip network |
| US7203798B2 (en) | 2003-03-20 | 2007-04-10 | Matsushita Electric Industrial Co., Ltd. | Data memory cache unit and data memory cache system |
-
2004
- 2004-01-16 US US10/759,564 patent/US7139877B2/en active Active
- 2004-08-05 DE DE602004017113T patent/DE602004017113D1/de active Active
- 2004-08-05 EP EP04254723A patent/EP1555616B1/de active Active
- 2004-08-10 TW TW093123853A patent/TWI249673B/zh active
- 2004-12-20 CN CNB2004101011781A patent/CN1303536C/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1555616A3 (de) | 2006-01-11 |
| US7139877B2 (en) | 2006-11-21 |
| EP1555616B1 (de) | 2008-10-15 |
| CN1303536C (zh) | 2007-03-07 |
| EP1555616A2 (de) | 2005-07-20 |
| CN1619511A (zh) | 2005-05-25 |
| US20040148468A1 (en) | 2004-07-29 |
| TWI249673B (en) | 2006-02-21 |
| TW200525355A (en) | 2005-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |