DE4137928A1 - Receiver interface for digital information transmission system - Google Patents

Abstract

The interface has a receiver (16) for receiving digital data words in its input channel. The data word is validated and a memory address determined for a valid data word. The data word is then stored in this memory address. The memory is connected via an interface (22) to a number of sub-systems each capable of reading the contents of the memory without influencing the other sub-systems. The valid data word comprises a predetermined number of bits. In order to identify a valid word, the number of bits is identified and compared with the predetermined number. Pref. the parity bits of the received signal are checked.

Description

The present invention relates to digital information tion transmission system (DITS) and in particular a Ver drive to data collection and a DITS receiver interface place for use with a plurality of Aviation electronics subsystems is suitable.

For the transmission of digital data between elements aviation electronics systems are different Arrangements used. Fulfill typical such arrangements len the standards, which are in the ARINC specification 429-11 entitled "Mark 33 Digital Information Transfer Sy stem (DITS) ", published August 29, 1988 by Aero nautical radio incorporation. The  ARINC specification 429 facilitates compatibility of interfaces of devices that are ver different manufacturers. Through the ARINC Specification 429 are predefined general digi tal data word formats and coding examples created. In the ARINC-429 data system for the high speed a bit rate of 100 kilobits per second ± 1% and a selected bit rate for the low speed Operation in the range between 12.0 and 14.5 kg bits defined per second. Also the selected Nieder speed rate should be kept in the range of ± 1% the.

From US 42 80 221-A is a digital data communication known system that is a data source, a sources interface and a digital data bus for the over transmission of coded information from the data source one or more recipients, each a recipient interface included, includes. The source interface and the receiver interface can be used with both high data rate of 100 kilobits per second as well a low data rate of 12 to 14.5 kilobits per Second work. The source interface can be specified in this way be fitted that they the rise and fall times of Controls signals on the data bus.

From US 42 98 959-A a DITS receiver is known with direct memory for a signal processor handle (DMA) can be created. The DITS receiver stores the data it stores over a plurality of ones receiving channels asynchronously, in the received Rei order directly in a random access memory (RAM) for the DITS data. The first byte ID of the data word informa tion field that identifies the data source is called Address pointer used that defi the position in RAM  on which the subsequent signal bits of the data word be saved. A common scanning network scans the Da received over each of the input channels so that samples with a duration of ge is less than that of a bit cell. The Ab tactile network creates at least one sample in which respective signal speed period both high speed as well as low speed signals are included. The sampled data is a Mul undergone tiplex operation, thereby in a serial Da tenstrom converted and either to an address register for the first byte or directly to the data RAM.

From US 46 46 324-A is a transmitter of a digital information mation transmission system known with the serial word ter of a given length with selected speed sent to a plurality of parals lel channels to be output. The digital transmitter is designed to provide test data for a flight parameter ter simulation from a database to the DITS receiver the US 42 98 959-A can deliver. The words for the serial transmission over the parallel output channels are selected, are repeated in succession in one Multiplexer entered, which is made up of these words chose bits with fixed and variably adjustable Ge speeds to a shift register and signal memory combination for transferring the output different.

In a conventional ARINC-429-DITS is for operation of any aircraft subsystem function within one single interchangeable unit (LRU) a separate DITS receiver interface required. Typically, for example, for a subsystem  a recording unit for digital flight data (DFDAU) and for a subsystem of a data management unit (DMU) data from an aircraft condition monitoring system (ACMS) uses separate DITS receiver interfaces. Hence the need for an ARINC-429 receiver interface for at least two in the same Functions or subsystems located in the unit can be used together and is designed in such a way that the characteristics and functionality of each Subsystems can be changed without the own who influences the other subsystem the.

It is therefore an object of the present invention to provide a Data collection method and a DITS receiver interface designed for use with a plurality of aviation electronics subsystems is suitable, too create.

It is another object of the present invention a data collection process and a DITS receiver interface, which is a first bus interface for the Use with a digital flight registration unit data DFDAU and a second bus interface for the Ver application with a data management unit DMU, to accomplish.

It is another object of the present invention an ARINC-429 receiver interface and method to create data collection with which the disadvantages the corresponding devices of the prior art can be eliminated.  

These tasks are at a receiver interface of the generic type and in a data acquisition drive of the generic type solved according to the invention by the features in the characterizing part of the claim 1 or in the characterizing part of claim 11.

According to the invention, a method for data acquisition and one for use with a plurality of air electronic subsystems suitable for DITS receivers interface created. The DITS emp catcher interface contains a receiver that is an in a digital input input to a receiver input channel tenwort receives. Then it is determined whether this is received gene digital data word is a valid word. In the Identification of a valid word becomes this identi fied valid word processed to at least one Determine memory address. Then the identifi adorned valid word among those available Memory addresses saved. An interface couples memory with each of the plurality of subsystems, so that each of the majority of the subsystems are in memory can read stored words without operating the to affect other subsystems.

Other objects, features and advantages of the invention are in the subclaims that relate to special aus relate to embodiments of the present invention give.

The invention is based on a preferred Embodiment with reference to the drawings he closer purifies; show it:  

Fig. 1 is a block diagram depicting the functional environment of the receiver interface according to the invention egg nes digital information transmission system;

Fig. 2 is a block diagram of the inventive receiver interface of the digital information transmission system; and

Fig. 3 is a flow chart for explaining the logical steps that are performed by a control device of the inventive DITS receiver interface of Fig. 1.

In Fig. 1, a receiver interface 10 for a digital information transmission system (DITS receiver interface) is shown, on the one hand via a DFDAU system bus 12 A with a subsystem 12 , which comprises a recording unit for digital flight data (DFDAU), and on the other hand a DMU system bus 14 A is connected to a subsystem 14 , which comprises a data management unit (DMU). According to a feature of the present invention, the DITS receiver interface 10 can be shared by a plurality of subsystems housed in the housing of a single in-line interchangeable unit (LRU).

The DITS receiver interface 10 carries out a self-test and stores the test results in a memory which can be read either by the DFDAU or by the DMU subsystem 12 or 14 . Although the DITS receiver interface 10 is shown and described for use with the DFDAU and DMU subsystems 12 and 14 , respectively, the DITS receiver interface 10 is not limited to this particular application.

In Fig. 2 is a block diagram of the DITS-receiver interface 10 of the invention is shown. As primary components, the DITS receiver interface 10 comprises a receiver component section 16 with a plurality of receivers 1 to N, a control device 18 , which is functionally coupled to each of the receivers 1 to N, a storage section 20 for storing data and status information and a bus interface 22 for connection to the subsystem buses 12 A and 14 A. The control device 18 , the memory buffer section 20 and the bus interface 22 are connected to the receiver section 16 by means of a bidirectional data, address and control bus 24 . As shown, each of the receivers 1 through N in the receiver section 16 includes four data input channels or ports. For example, if N is 16 , there are 64 ports that can receive data at the same time. The DITS receiver interface 10 can automatically set the speeds of each of the 64 ARINC-429 data inputs so that external speed programming is not required.

In US 6 16 512-A dated November 21, 1990 (which corresponds to the German application filed on the same date as the present application with the title "Method and device for automatic detection of the speed of digital data"), the applicant discloses a method for automatic detection of the speed of digital data in the transmission of digital data between rule's elements of avionics systems, which can be used by the DITS receiver interface 10 according to the invention before geous. The disclosure of the aforementioned application is referred to below.

Various commercially available microprocessors or control devices with standard services can be used for the control device 18 . For each of the receivers 1 through N, an ARINC-429 transceiver integrated on a circuit chip can be used, which contains a transmitter, four receivers and data, activity, status and control registers.

The ARINC-429 data words are received by the ARINC-429 receiver component section 16 and checked for data validity. The data validity check includes the verification of the correct length and the correct parity of the words received, the correct length being, for example, exactly 32 bits. If the received word does not contain exactly 32 bits or does not have the correct parity, the word is rejected by the respective receiver component 16 . If there is an incorrect parity, a status bit is set in a special register in the receiver component section 16 . If the received word is valid, it can be read by the controller 18 of the ARINC-429-DITS receiver interface 10 .

A double buffering of the received data is provided by the receiver component section 16 so that a received word is buffered while a subsequent further word is received. This double data buffering is provided for each of the 1 to N receivers independently of the other receivers. The double buffering allows the controller 18 to read tion the data word and the status of informality in a word clock time. If the controller 18 cannot read the buffered received word before the next word has been completely received, the buffered word is overwritten by the newly received data, and a status bit indicating a buffer overflow in a special corresponding register of the ARINC-429- Receiver component section 16 is set.

The control device 18 is a machine operating in the operating step cycle, which cyclically polls the ARINC-429 receivers 1 to N for data and status. Controller 18 polls all receivers within a high speed ARINC 429 word clock or within approximately 336 microseconds for 32 bits per word plus a minimum 2 bit wide slot at the maximum high speed rate (101 kilohertz). The cyclic data and status polling is performed at a sufficient rate to ensure that all valid data samples entered into the interface 10 are received and stored by the interface. In this way, the most recently received ARINC-429 data for subsystems 12 and 14 are provided in a single LRU package.

When the controller 18 detects a valid received word from the ARINC-429 receiver, the data area of the word is stored in memory 20 with an up count (8 bits). Each valid ARINC-429 word received is stored in memory 20 as a function of recipient number, label, and source identification identifier (SDI) information to uniquely identify the ARINC-429 data words. The label contains 8 bits, which are arranged at bit positions 1 to 8 of the 32-bit ARINC-429 data word. The SDI contains 2 bits, which are arranged at bit positions 9 and 10 of the 32-bit ARINC-429 data word. For some ARINC-429 data words, the SDI is provided optionally and used for the extension of the ARINC-429 DITS word identification. A common use of the SDI serves to identify different sources of the same parameter type. For example, the engine exhaust gas temperature has an ARINC 429 label of 345, with the SDI bits used to identify various engine positions approximately as follows: 01 = engine # 1, 10 = engine # 2, 11 = engine # 3 and 00 = Engine # 4. A first data buffer 26 stores the ARINC-429 data words as a function of the label (8 bits). A second data buffer 28 stores the ARINC-429 data words as a function of both the label and the SDI bits (10 bits). Since the SDI is either taken into account or not taken into account, the ARINC 429 DITS data word received is reduced both as a function of only the label in the memory buffer 26 and as a function of the label / SDI data in order to reduce the load on the subsystems 12 and 14 . Combination stored in memory buffer 28 .

The status information is stored in a third data buffer 30 in the memory 20 . This status information contains, for example, the results of the self-test carried out by the ARINC 429 DITS receiver interface 10 , the DITS receiver activity, the self-speed determination and the parity error counts. The status information stored in the memory buffer 30 can be called up by the subsystems via the bus interface 22 . Memory 20 can be read by any subsystem, such as the illustrated subsystems 12 and 14 in the LRU. A system bus interface 32 , 34 is connected to the DITS memory buffers 26 , 28 and 30 in the memory 20 via the bus 24 . In the ARINC-429 receiver interface 10 , the memory buffers 26 and 28 must be such that they can store 256 or 1024 ARINC-429 DITS words with 64 data bits and 8 up-count bits for 64 ARINC-429 receivers.

In Fig. 3 is a flow chart for the logical steps performed by the Steuerein direction. When the control device 18 is activated, the successive operations begin at the block 300 marked with "Start". In block 302 marked with "initialization", an initialization routine is first executed. Then 429 receiver interface control means is in the marked "self-test" block 304 from the ARINC 18 execute a self-test of all receiver, and a test of the SpeI Chers 20, also all the memory contents, including the received with each valid ARINC 429 word stored Bits 1 to 8 of an up counter are set to zero. The controller 18 sequentially polls each of the 64 ARINC-429 receivers for data and status within a high-speed ARINC-429 word clock. In block 306 , marked "cyclically poll recipient", a first recipient is polled cyclically. In the "Receive data word?" block 307 , a received data word is identified. If the answer is "no", the next recipient is cyclically queried by returning to block 306 . On the other hand, if the answer is "yes", processing continues to one with "data valid?" marked decision block 308 . In block 308 , the receiver status bit, indicating whether the data is valid or not, is checked to determine whether the data word is valid. If a valid ARINC-429 DITS word is not identified in block 308, one or more error status bits are set in block 310 labeled "set status bit (s)". Then the operations performed one after the other return to block 306 labeled "poll receiver cyclically" to poll the next of the 64 receivers cyclically.

If a valid at block 308, ARINC 429 DITS word is fied identical, the controller 18 stores this DITS-word in the memory 20 twice, once as a function of the 8-bit label in the word buffer 26 and a second time as a function of the label and the SDI with a total of 10 bits in word buffer 28 . The addresses are set in block 312 labeled "Label / SDI Addresses" as a function of a particular one of the 64 ARINC-429 DITS receiver buses 1 through 64 and the 8-bit label and SDI bits of the ARINC-429- Word determined. These information bits are used to build the address at which the DITS word is stored in memory buffers 26 and 28 . The ARINC-429 DITS word is stored in the exact location or address specified for each of the DITS memory buffers 26 and 28 , as shown in block 314 labeled "Save and Update Data". The manner in which subsystem 12 and / or subsystem 14 read the ARINC-429 DITS memory buffers 26 and 28 is identical and uses the same information to provide the required ARINC-429 DITS words to address. The subsystem 12 or the subsystem 14 generates an address which is constructed from the 6-bit specific receiver bus number for the 64 buses 1 to 64 , the 8 ARINC-429 label bits 1 to 8 , the 2 ARINC-429-SDI -Bits 9 and 10 and the information whether the SDI must be observed or not.

When the ARINC 429 DITS word is stored in memory buffer 20 in block 314 , controller 18 generates an indication of whether the DITS word has been updated. The update notice represents information required by subsystems 12 and 14 using the stored ARINC-429-DITS words to determine whether the read data represents a new sample or an already read old sample. The update notice is provided along with update counter bits for each individual ARINC-429 DITS word. The update counter value is stored together with the ARINC-429-DITS word instead of the ARINC-429 label. The label is no longer needed because it is implicitly known from the memory addressing information. When the ARINC-429 DITS word is to be stored in the memory buffer, the controller 18 reads the update counter value for the particular ARINC-429 DITS word from the memory buffer, increments the count, and stores the count and the DITS received. Bits 9 to 32 in the available memory buffer space. This process is carried out independently for the 8-bit label storage and the 10-bit label / SDI storage, so that the update counters are read and incremented individually and the data are stored twice, once in the 8-bit memory buffer 26 and one second time in the 10-bit memory buffer 28 . Then the successive operations return to block 306 labeled "Recipient Recipient".

Subsystems 12 and 14 read the ARINC-429 DITS words using the update counter bits to determine whether the ARINC-429 DITS word has been reading since the last time the subsystem read the particular DITS word. has been updated. In order to perform the update comparison, the subsystem must keep the update count of the previously read sample of the ARINC-429-DITS data word. Subsystem 12 , 14 then compares the update count of the new sample with the update count of the previous sample. If the two counts are different, the ARINC-429-DITS word has been updated since the word was last read.

In addition to providing the update notice The update counters wisely generate a hint regarding the number of in a measured period of time ARINC-429-DITS words received for a particular Label or a specific label / SDI combination.

Any storage location in the memory 20 or in the puff 26 , 28 or 30 can be accessed from any of the subsystems 12 , 14 in the LRU via the bus interface 32 , 34 . For the ARINC-429-DITS receiver interface 10 shown , two interface buses are provided which lead to the memory buffer 20 , the DFDAU system bus 12 A and the DMU system bus 14 A. In the preferred embodiment, the DFDAU bus 12 A is a parallel 16-bit bus, while the DMU system bus 14 A is a parallel 32-bit bus. When an ARINC-429-DITS parameter or status information is to be read, the ARINC 429-DITS receiver interface controller 18 shifts a coherent 32-bit word into an output buffer, which is for the 12 A DFDAU and DMU system buses or 14 A is carried out independently. An ARINC-429 DITS word can be read over bus interface 32 , 34 over a 16-bit path and represent a coherent ARINC-429 data sample. The bus interface 34 can also perform a read operation over a 32-bit path.

Although the present invention is related to details th of the illustrated embodiment has been described is not intended to be such details Scope of the present invention by the beige added claims is defined, limit.

Claims (18)

1. Receiver interface ( 10 ) for digital information transmission system, which is suitable for use with a plurality of subsystems ( 12 , 14 ), characterized by
receiver means ( 16 ) for receiving a digital data word input into a receiver input channel;
means ( 18 ) connected to the receiver means ( 16 ) for identifying a received valid word;
means ( 20 ) connected to the means ( 18 ) for identifying a received valid word and storing this identified valid word upon identification of a valid word; and
an interface device ( 32 , 34 ) for connecting the storage device ( 20 ) to each of the plurality of subsystems ( 12 , 14 ) and for releasing each of the plurality of subsystems ( 12 , 14 ) for reading from the storage device ( 20 ) saved words. 2. Receiver interface ( 10 ) for a digital information transmission system according to claim 1, characterized in that the interface device ( 32 , 34 ) releases each of the plurality of subsystems ( 12 ; 14 ) to the words stored by the memory device ( 20 ) read without affecting the operation of their respective subsystems ( 14 ; 12 ). 3. Receiver interface ( 10 ) for a digital information transmission system according to claim 1, characterized in that the valid data word comprises a predetermined number of bits and the means ( 18 ) for identifying a received valid word means for identifying a number of bits in the received gene digital data word and means for comparing the identified number with the predetermined number of bits. 4. Receiver interface ( 10 ) for a digital information transmission system according to claim 1, characterized in that the device ( 18 ) for identifying a received valid word comprises a device for checking the parity bits of the received digital Da word word. 5. Receiver interface ( 10 ) for a digital information transmission system according to claim 1, characterized in that the identification device ( 18 ) comprises a processor device which responds to an identifi ed valid data word to process the valid data word and at least one memory address to Save the identified valid word. 6. Receiver interface ( 10 ) for a digital information transmission system according to claim 5, characterized in that the data word comprises predefined label bits and these label bits are used to determine the at least one memory address for storing the valid data word. 7. Receiver interface ( 10 ) for a digital information transmission system according to claim 6, characterized in that the identification device ( 18 ) comprises a device for storing an update counter value together with each stored valid data word. 8. Receiver interface ( 10 ) for a digital information transmission system according to claim 7, characterized in that the update counter value is stored at given bit positions of the digital data word. 9. A receiver interface ( 10 ) for a digital information transmission system according to claim 6, characterized in that the data word includes predefined sources of destination identifier bits (SDI bits) and the SDI bits are used together with the label bits to provide the at least one memory address Save the valid data word. 10. Receiver interface ( 10 ) for a digital information transmission system according to claim 8, characterized in that the stored update count value is read by the subsystems ( 12 , 14 ) in order to determine a new data word sample. 11. A method for data acquisition for use with a receiver interface ( 10 ) of a digital information transmission system connected to a plurality of subsystems ( 12 , 14 ), characterized by the steps
receiving ( 307 ) a digital data word input into a receiver input channel;
identifying ( 308 ) a received valid word;
processing ( 312 ) the identified valid word based on the identification to determine at least one memory address; and
storing ( 314 ) the identified valid word at the at least one particular memory address. 12. The method according to claim 11, characterized in that the valid data word comprises a predetermined number of bits and the step of identifying ( 308 ) a received valid word comprises the following steps:
Identifying a number of bits in the received digital data word; and
Compare the identified number with the specified number of bits. 13. The method according to claim 12, characterized by the step performing a parity error check for the received digital data word. 14. The method according to claim 11, characterized in that the step of receiving ( 307 ) a digital data word input into a receiver input channel comprises the following step:
Creation of double data buffering by storing a first received digital data word in a second data buffer, while a further existing digital data word is received by a first data buffer. 15. The method according to claim 14, characterized in that the data word comprises predefined label bits and predefined source identification bits (SDI bits) and the step of processing ( 312 ) the identified valid word based on an identification to determine at least one memory address the following Steps include:
Identifying the label bits and the SDI bits; Determining a first memory address for storing the valid data word using the identified label bits; and
Determine a second memory address for storing the valid data word using both the identified label bits and the identified SDI bits. 16. The method according to claim 11, characterized in that the step of storing ( 314 ) the identifi ed valid word comprises the following step:
Storage of an update counter value together with the stored valid data word. 17. The method according to claim 16, characterized in net that the step of saving an update tion counter value the step of identifying a last saved counter value and increment by 1 the identified last saved counter value includes. 18. The method according to claim 17, characterized in net that the data word predetermined bit positions for the includes predefined label bits and the incremented  Counter value at the specified bit positions for the previous defined label bits is stored.