DE4023002A1 - Integrated circuit memory with parallel-series conversion function - has memory cell field with lines and columns for selective access by number of bits - Google Patents

Abstract

The memory contains a memory cell field (32), which can be selectively accessed by a number of bits. The field contains numerous memory cells in lines and columns. An external address signal dependent selector (34, 36, 38, 40) operates w.r.t. the number of bits in the field for data read-out from the selected cells. - The read-out data fron a number of bits are received in parallel by a device (44), while a second device, (46, 50) converts the received parallel data into series ones for output transmission. The second device has a clock pulse generator and a clock pulse counter. In dependence on the latter selective and sequential passing of data from the first device is carried out.

Description

The invention relates to an integrated semiconductor memory facility and in particular a structure for simplification of the clocking design in a system that uses the integrated semiconductor Storage device used, and on a structure for reduction the access time when reading data.

In general, when a large capacity and high operating speed memory system is created by using smaller capacity, low operating speed semiconductor memory devices which are not particularly expensive, a plurality of semiconductor memory devices are wired in an OR circuit as shown in FIG Fig. 1 is shown.

Are with respect to the Fig. 1, four memory IC 3-1, 3-2, 3-3 and 3-4 connected to an output bus 2 in the form of an OR circuit. The memory ICs 3-1 to 3-4 transmit, depending on the output, activation signals to output data Q 0 to Q 3 via corresponding output nodes 1-1 to 1-4 to the output bus 2 .

The output activation signals are applied by a CPU (central processing unit = not shown). In general, if these memory ICs are dynamic semiconductor memory devices, a chip enable signal indicating the activation / deactivation of a chip (memory IC), a row address strobe signal indicating a clock signal for accepting a row address, a signal that a clock signal indicating acceptance of a column address, a write enable signal indicating data write, etc., is applied from the CPU to each of the memory ICs 3-1 to 3-4 .

To simplify the drawing, only the output activation signals to which correspond to the data output are shown in FIG. 1. The output enable signals 12 to 13 generally indicate the enable / disable of an output buffer (not shown) in each of the memory ICs 3-1 to 3-4 . If the output activation signals are to be brought into the active state, access to memory cell fields (not shown) in each of the memory ICs 3-1 to 3-4 has already taken place and the data of the addressed memory cells have been applied to the input areas of the output buffers . The operation of the memory system shown in FIG. 1 will be briefly explained with reference to the signal diagram of FIG. 2.

First, the memory ICs 3-1 to 3-4 are accessed, and in each of these memory ICs 3-1 to 3-4 , selection of memory cells and reading out of the data is carried out. At this time, the output enable signals are still in an inactive state and their level is "H".

Then the output enable signal changes to the active "L" level. After the time Ta for the change of the output activation signal to the active state has passed, the output data Q 0 is transmitted to the output bus 2 and is set there. Subsequently, the output enable signal rises to the "H" level to put the memory IC 3-1 in an output deactivating state, and then the output enable signal falls to the "L" level to put the memory IC in the Set output activation state. Consequently, it is transferred from the memory IC 3-2 the output data Q 1 via the output node 1-2 to the output bus. 2 This operation is then repeated, so that the output data Q 2 and Q 3 of the memory IC 3-3 and 3-4 are successively transmitted to the output bus 2 .

In the memory system shown in Fig. 1, the access time of the output bus 2 is equal to the access time by the output activation signal (bis). Compared to the RAS access time in a general dynamic semiconductor memory device (the time from the beginning of the change of the signal in the active state to the setting of the output data on the output bus 2 ), this access time is shorter, and the formation of a high-speed memory system is therefore lower Use of low speed memory ICs possible.

Since the data of a plurality of memory ICs are read one after another, it is possible to create a high-capacity memory system using lower-capacity memory ICs. More specifically, in the example system of FIG. 1, a memory system can be formed which has a capacity four times greater than that of a memory IC.

With the conventional storage system described above, it is possible to a storage system with large capacity and high operating speed ability to create by using cheap memory ICs which has a smaller capacity and slow operating speed without expensive, large capacity, high memory ICs Need to use operating speed.

In the memory system described above, however, the output activation signals having different phases must be applied to in order to read out data sequentially from the memory ICs 3-1 to 3-4 . Furthermore, a relatively long output bus 2 must be formed externally for the memory ICs 3-1 to 3-4 .

Furthermore, the system clock must take into account the access time Ta (the time from the change of the output activation signal to the active state until the occurrence of the data which occurs on the output bus 2 ) by the output activation signal and the deactivation time Tb (the time from the change of the output activation signal to the inactive state until the data on the output bus 2 ) are invalid in such a way that collisions of the output data on the output bus 2 are avoided.

For a more detailed explanation, reference is now made to FIG. 2. If the output enable signal of the memory IC 3-2 becomes active before the deactivation time Tb of the memory IC 3-1 has passed and the issue date Q 1 appears on the output bus 2 , the data Q 0 and Q 1 collide with each other. This prevents accurate data reading. Therefore, the timing of the memory system must be designed with the collision time Tc in mind.

If necessary, the high-speed storage system to operate, the design of the timing must be considered view of the maximum / minimum values of access and deactivation crossing time. This makes designing the business clocking of the storage system difficult and complicated.

In the memory system described above, there must also be a limit to the clocking for activating the output activation signal with regard to the access and deactivation time in order to avoid a data collision on the output bus 2 . This prevents a high operating speed.

The object of the invention is to overcome the disadvantages described above to avoid a conventional memory system with memory ICs and a memory IC and an operating method therefor create that simplifies the clock design of the storage system, and enables data reading at high speed.

The memory IC according to the invention comprises a memory cell array, which can be accessed bit by bit, a circuit for Read a plurality of bits in parallel from the memory cell array and a circuit for converting the read plurality of Bits in data from a series of bits to output.

The serial conversion circuit includes a counter circuit circuit for counting clock signals and a circuit which is from the Output signal of the counter circuit is dependent on one another  hence the read plurality of bits of the parallel data select it and convert it to serial data and this to spend.

The initial value of the counter circuit can be preset and the counter circuit can go both up and down numbers.

In the memory IC according to the invention, a plurality of are switched off Memory ICs read bits in parallel that represent parallel data, read out serially depending on a clock signal. Therefore it becomes different from a conventional storage system that consists of a plurality of memory IC, possible output data at a speed defined by the clock signals received, the data does not collide without the data read the access time (the time span from the change of the Output activation signals in the active state until Setting the output status), the deactivation time or Similar must be observed. This simplifies the clock design of the storage system.

By operating the counter circuit to output the serial Data also allows the plurality of bits of the parallel data in ascending or descending order, starting with a any bit to read. This leads to a storage system excellent processing skills, e.g. the formation of Mirror images in the field of image processing.

Further features and advantages of the invention result from the description of an embodiment with reference to the figures. From the figures show:

Fig. 1 shows an example of a conventional structure of a memory system with memory ICs for converting a plurality of data bits into serial data to output it;

Fig. 2 is a signal diagram showing the operation of the conventional memory system with a plurality of memory ICs;

Fig. 3 schematically shows the overall structure of the memory IC in accordance with an embodiment of the invention;

Fig. 4 shows an example of the structure of an output buffer area in accordance with the embodiment of the invention;

Fig. 5 is a signal diagram illustrating the operation of the circuits shown in Figures 3 and 4.

Fig. 6 shows an example of the construction of a counter circuit included in the control circuit 50 of Fig. 3; and

FIG. 7 shows an example of the construction of a shift clock generating circuit for indicating the selection included in the control circuit of FIG. 3.

In Fig. 3 only the circuit areas for data reading are Darge provides. Referring to Fig. 3 includes the memory IC 3, a memory cell array 32, can be provided with a plurality of bits bit by bit is accessed to. The memory cell array 32 is divided into four memory cell array blocks M 1 , M 2 , M 3 and M 4 . It is possible to access a bit in each of the memory cell array blocks M 1 to M 4 in order to read data therefrom.

An address buffer 34 , a row decoder 36 and a column decoder 38 are formed for the definition of rows and columns in the memory cell array 32 . The address buffer 34 generates an internal row and an internal column address depending on an externally created address. The row decoder 36 decodes the internal row address from the address buffer 34 in order to select a row in the memory cell field 32 . A row is selected in each of the memory cell array blocks M 1 , M 2 , M 3 and M 4 in accordance with the row selection signal from the row decoder 36 .

The column decoder 38 decodes the internal column address from the address buffer 34 in order to select a corresponding column of the memory cell field 32 . In accordance with the column selection signal from the column decoder 38 , a column is selected in each of the memory cell array blocks M 1 , M 2 , M 3 and M 4 . The row address and the column address are successively applied to the address buffer 34 as external addresses.

An input / output circuit 40 , an internal data bus 42 , a preamplifier 44 and an output buffer 46 are provided for reading data from the selected memory cells. The input / output circuit 40 connects the corresponding to the outputs of the row decoder 36 and column decoder 38 selected SpeI cherzellen with the internal data bus 42nd The I / O circuit 40 comprises four corresponding to the memory cell array blocks M 1 to M 4 formed input / output blocks IO 1, IO 2, IO 3 and IO. 4 Generally, input / output circuit 40 includes a sense amplifier for acquiring and amplifying the data of the selected memory cell. However, to simplify the drawing, the sense amplifier is omitted.

The internal data bus 42 has a width of four bits and transmits the read data in parallel from the memory cells via the input / output blocks IO 1 to IO 4 to the preamplifier 44 . The sense amplifier 44 forms the signals of the parallel 4-bit data Q 0 , Q 1 , Q 2 and Q 3 transmitted via the internal data bus 42 and amplifies them. The output buffer 46 is activated as a function of the output activation signal and converts the parallel 4-bit data from the preamplifier 44 as a function of clock signals Φ 0 to Φ 3 from the control circuit 50 . The clock signals Φ 0 to Φ 3 are four phase clock signals that do not overlap each other and represent clock signals for converting the parallel 4-bit data Q 0 to Q 3 into serial 1-bit data Q in the output buffer 46 . An internal clock generator 48 and a control circuit 50 for defining the operating clock of the memory ICs are provided. The internal clock signal generator 48 receives external control signals, that is, the row address strobe signal, the column address strobe signal, a write enable signal, the output enable signal and a chip select signal, and generates various internal control signals. The control circuit 50 is formed of a counter circuit 50th The control circuit 50 receives signals PR 0 and PR 1 for setting a preset value of the counter, a signal REQ which defines the incrementing / decrementing operation of the counter, and a signal which provides the counting operation clock.

Fig. 4 illustrates an example of a specific structure of the off transfer buffer 46. Referring to FIG. 4 46 (parallel-serial conversion section) includes the output buffer a data selection area, a data area and a locking Ausgabetrei advertising area. The data conversion area includes transmission gates TG 1 , TG 2 , TG 3 and TG 4 , which are connected in parallel to each other.

The transmission gate TG 1 is formed from a p-channel MOS transistor (hereinafter referred to as PMOS transistor) PT 1 and an n-channel MOS transistor (hereinafter referred to as NMOS transistor) NT 1 , which are connected in parallel . The PMOS transistor PT 1 receives a complementary control signal at its gate. The NMOS transistor NT 1 receives a control signal Φ 0 at its gate. Therefore, the transmission gate TG 1 becomes conductive to pass the data Q 0 when the control signal Φ 0 reaches the "H" level.

The transmission gate TG 2 is formed from a PMOS transistor PT 2 and an NMOS transistor NT 2 , which are connected in parallel. The PMOS transistor PT 2 receives at its gate a complementary control signal and the NMOS transistor NT 2 at its gate a control signal Φ. 1 Therefore, the transmission gate TG 2 becomes conductive to pass the data Q 1 when the control signal Φ 1 reaches the "H" level.

The transmission gate TG 3 is formed from a PMOS transistor PT 3 and an NMOS transistor NT 3 , which are connected in parallel. The PMOS transistor PT 3 receives at its gate a complementary control signal and the NMOS transistor NT 3 at its gate a control signal Φ. 2 Therefore, the transmission gate TG 3 becomes conductive to pass the data Q 2 when the control signal Φ 2 reaches the "H" level.

The transmission gate TG 4 is formed from a PMOS transistor PT 4 and an NMOS transistor NT 4 , which are connected in parallel. The PMOS transistor PT 4 receives at its gate a complementary control signal and the NMOS transistor NT 4 at its gate a control signal Φ. 3 Therefore, the transmission gate TG 4 becomes conductive to pass the data Q 3 when the control signal Φ 3 reaches the "H" level.

The locking area consists of inverter circuits I 1 and I 2 , which are connected anti-parallel. The lock area inverts and transmits the date supplied from one of the transmission gates. The output driver area includes gate circuits G 1 and G 2 and NMOS transistors NT 10 and NT 12 . The gate circuit G 1 forms a NOR gate, one input of which receives the output enable signal and the other of which receives an output date from the latch area. The gate circuit G 2 receives at its false input the output activation signal and at its true input the output signal from the locking area.

The NMOS transistors NT 10 and NT 2 are connected in series between a first supply potential Vcc and a second supply potential Vss. The gate of the NMOS transistor NT 10 receives the output signal from the gate circuit G 1 and the gate of the NMOS transistor receives the output signal from the gate circuit G 2 . The output data Q is output by the node between the NMOS transistors NT 10 and NT 12 . The operation of the memory IC shown in Figs. 3 and 4 will be described with reference to Fig. 5, which shows the signals in operation.

First, at an appropriate time before reading the data, the initial value of the control circuit is set and the order of reading the data is defined. The setting of the initial value and the order of the output data selection are carried out in accordance with the control signals ϕ and REQ applied to the control circuit 50 and data PR 0 and PR 1 for setting the initial values. The external address is then applied to the address buffer 34 and, depending on the control signals, etc., the corresponding row and the corresponding column are selected by the row decoder 36 and the column decoder 38 . In the memory cell array 32 , a bit is selected in each of the memory cell blocks M 1 to M 4 , and the selected memory cell data are transmitted to the preamplifier 44 via the input / output circuit 40 and the internal data bus 42 . Then the output enable signal rises to the "L" level to activate the output buffer 46 . As a result, the gate circuits G 1 and G 2 are activated, thereby enabling data output.

Then the external signal drops from "H" to "L" level. In response to the falling edge of the control signal from "H" to "L" level, a control signal ignal 0 is generated. Consequently, the transmission gate TG 1 is switched through and the readout data Q 0 is transmitted to the gate circuits G 1 and G 2 via the inverter locking circuit (from the inverter circuits I 1 and I 2 ). Depending on the reading data Q 0 , one of the NMOS transistors NT 10 and NT 12 is turned on , which causes the data Q to be output.

By successively switching the control signals, the control signals Φ 1 , Φ 2 and Φ 3 are generated in succession as single pulse signals and the transmission gates TG 2 , TG 3 and TG 4 on successively conductive. By sequentially switching through the transmission gates TG 1 to TG 4 , the serial output data Q is output via the inverter locking circuit, the gate circuits G 1 and G 2 and the NMOS transistors NT 10 and NT 12 .

In the foregoing description, the initial value of the counter circuit included in the control circuit has been set to a value that activates the transmission gate TG 1 first, and the control signal REQ, which indicates the reading order, defines a sequence for activating the transmission gates TG 1 , TG 2 , TG 3 and TG 4 , in that order.

Due to the structure described, successive individual pulse signals are generated in response to the falling edge of the control signal from "H" to "L", and the read data selected as a function of the individual pulse signals are held in the locking area and output as output data Q. The control signals Φ 0 to Φ 3 are single pulse signals that do not overlap each other. Since 4-bit data is sequentially output bit by bit, output data can be provided reliably at high speed without data collision on the output bus. Since the data are sequentially output from the memory IC, the output data can be securely output by some kind of clock signals without having to consider the access time and deactivation time in the memory IC. This simplifies the clock signal design of the memory system.

Because the data read in parallel is sequential read, e.g. a memory IC with x4 bit structure and an access time (time) of 100ns equivalent to four Memory ICs with xl bit structure, with a maximum access working time of 25ns. Accordingly, one with high Speed working storage system without collision Output data are created.

The specific structure of the control circuit 50 is described below.

Fig. 6 shows an example of the construction of the Zählerschaltkreisbe rich in the control circuit 50. Referring to Fig. 6 includes the counter circuit portion has a pulse generating circuit PG, the individual pulse signals CK and generates in response to the control signal, and counter 60 and 62 signals for counting the single pulse CK and. The counters 60 and 62 represent 2-bit counters. The counter 60 generates the least significant bit and the counter 62 the more significant bit.

The pulse generation circuit PG comprises three stages of cascade-connected inverters I 20 , I 22 and I 24 , a NAND gate NA 1 which receives the output signal of the inverter I 24 and the control signal, and an inverter I 26 which receives the output signal of the NAND - Gate NA 1 is supplied. The three stages of the cascade-connected inverters I 20 , I 22 and I 24 form an Inversionsver delay circuit which delays the control signal by a predetermined period of time, inverts it and applies it to an input of the NAND gate NA 1 . The NAND gate NA 1 receives the control signal at its other input. Therefore, in response to the falling edge of the control signal from "H" to "L", a single pulse signal is generated which rises for a predetermined period of time (which is defined by the delay time of inverters I 20 , I 22 and I 24 ).

The counter 60 comprises inverter latch circuits L 1 and L 2 , an inverter I 30 and switching transistors ST 1 and ST 2 . The inverter latches L 1 and L 2 are each formed from two anti-parallel inverters. The inverter I 30 inverts the data held by the inverter latch L 1 and outputs it. The switching transistor ST 2 is turned on in response to a single pulse signal from the pulse signal generating circuit PG and transmits the output signal from the inverter I 30 to the inverter latch circuit L 2 . The switching transistor ST 1 is turned on in response to an inverted single pulse signal CK from the single pulse generating circuit PG and transmits the data held by the inverter latch circuit L 2 to the inverter latch circuit L 1 .

The latching ability of the inverter latch circuits L 1 and L 2 , that is, the driving ability of the inverters, is set so that the data flow takes place in a clockwise direction, as shown by the arrow in FIG. 6. A complementary clock signal A is output from the inverter latch circuit L 1 and a clock signal A from the inverter I 30 .

A preset transistor RT 1 , which transmits a preset signal PR 0 as a function of the control signal ϕ, is formed for presetting the initial value of the counter 60 . The preset signal PR 0 is held by the inverter latch circuits L 1 and L 2 .

The counter for generating the high-order bit includes inverter latch circuits L 3 and L 4 , inverters I 40 and I 42 , and switching transistors ST 10 , ST 12 , ST 14 and ST 16 . The clock signal A from the counter 60 is transmitted to the counter 60 via the inverter I 32 . The inverter I 40 receives the lock signal of the inverter lock circuit L 3rd The switching transistor ST 16 switches depending on the output signal of the inverter I 42 , that is, the clock signal A, by.

The switching transistor ST 14 switches depending on the output signal of the inverter 32 and transmits the output date from the inverter latch circuit L 3 to a node F. The switching transistor S 16 transmits the output signal of the inverter I 40 to the node F.

The switching transistor ST 12 is switched in response to the single pulse signal CK by the single pulse signal generating circuit and transmits the potential at node F to the inverter latch circuit L 4 . The switching transistor ST 10 switches depending on the single pulse signal from the single pulse generation circuit PG and transmits the output signal of the inverter latch circuit L 4 to the inverter latch circuit L 3 . Also in this counter circuit 62 , the locking capabilities and the driving ability of the components of the inverter locking circuits L 3 and L 4 constituting the inverter are such that the data flow takes place in the direction of the arrow shown in FIG. 6.

A preset transistor RT 2 is formed, which transmits a signal PR 1 indicating the initial value as a function of the control signal ϕ in order to set the initial value of the counter 62 . The preset date PR 1 is held by the inverter latch circuits L 3 and 4 . A complementary clock signal is output by the inverter latch circuit L 3 and a clock signal B is output by the inverter I 40 . Operation is briefly described below.

It is now assumed that the default values of counters 60 and 62 are both "0"("L"). At this time, clock signals A and B are both at the "L" level, while the two complementary clock signals and both are at a high level. If the control signal is at the "H" level, the single pulse signal CK is not generated and is thus at the "L" level while the inverted pulse signal is at the high level. Therefore, the inverter latch circuits L 1 and L 2 are connected through the switching transistor ST 2 and the node H holds the initial value PR 0 . In contrast, the switching transistor ST 12 in the counter 62 is conductive and the switching transistor ST 10 is blocked. Since the clock signal A is "L", the switching transistor is switched through and the switching transistor ST 16 is blocked. Therefore, the inverter latch circuit L 3 is connected to the inverter latch circuit L 4 via the switching transistors ST 12 and ST 14 . The node G holds the initial value PR 1 .

Now the control signal is generated. In response to the falling edge of the control signal from "H" to "L" level, the single pulse signal CK is generated. Consequently, the switching transistors ST 1 and ST 10 are turned on . "H" is thus written into the node H by the latch circuit L 2 and the data held at the node H becomes "H". In the counter 62 , a signal inverted by the latch circuit L 4 is written into the node G via the switching transistor ST 10 . That is, "L" is written into the node G by the latch circuit L 4 , whereby the date held at the node G becomes "L". In this state, the counters 60 and 62 count a clock signal so that their output signals A and B are "H" and "L", respectively.

When the clock signal CK drops, the transistors ST 1 and ST 10 block and the transistors ST 2 and ST 12 are turned on. The "H" signal A is transmitted to the latch circuit L 2 and the "L" signal B via the transistor ST 16 to the latch circuit 4 .

When the control signal drops from "H" to "L" again, the single pulse clock signal CK is generated again. In response to this signal, the transistors ST 1 and ST 10 turn on and the transistors ST 2 and ST 12 are blocked. As a result, an "L" signal is transmitted from the inverter latch circuit L 2 to the node H, and the signal A falls to "L" via the inverter latch circuit L 1 and the inverter I 30 . In contrast, an "H" signal is transmitted from the inverter latch circuit L 4 to the node G and the signal B rises to "H" via the latch circuit L 3 and the inverter I 40 .

In this state, the transistor ST 14 turns on and the transistor ST 16 blocks. As a result, the potential at node F reaches "L" level through the signal.

When the clock signal drops to "L", the transistors ST 1 and ST 10 block again and the transistors ST 2 and ST 12 turn on. As a result, an "L" signal is transmitted to the latch circuit L 2 and an "L" signal to the latch circuit L 4 .

If the control signal drops a third time, it will Potential at node H, the potential at node G and the signals A and B all the "H" level.  

If the clock signal CK drops to the "L" level, an "H" signal is transmitted via the transistor ST 2 to the latch circuit L 2 and an "H" signal via the transistors ST 16 and ST 12 to the latch circuit L 4 .

In response to the fourth drop in the control signal, by the clock signal CK is generated reach the potentials the nodes G and K and accordingly also the signals A and B all the "L" level.

The operation described above is repeated. Namely, the 2-bit output (BA) of the counters 60 and 62 repeat the cycles ( 01 ), ( 10 ), ( 11 ) and ( 00 ). Bit "1" corresponds to the signal potential "H" and bit "0" corresponds to the signal "L".

Referring to Fig. 7 will now be a circuit structure for generating a control signal for parallel-serial conversion in response to the clock signals A and B described by the counter circuit portion. In Fig. 7, clock signal generating circuits 71 , 73 , 75 and 77 for the clock signals Φ 0 , Φ 1 , Φ 2 and Φ 3 are shown for conversion. The structure of the clock signal generating circuits 71 , 73 , 75 and 77 is the same and only the combination of the clock signals A,, B is different. Therefore, only the construction and operation of the clock signal generating circuit 71 for generating the clock signals Φ 0 and for the conversion is described as a typical example.

Referring to Fig. 7, the clock signal generating circuit 71 comprises transmission gates TM 1, TM 3, TM 5 and TM 7, a NAND gate NA1 and an inverter circuit I50. Each of the transmission gates TM 1 , TM 3 , TM 5 and TM 7 is formed from a PMOS and an NMOS transistor, which are connected in parallel. The transfer gate TM 1 becomes conductive in response to an up / down count determination signal REQ and passes the clock signal A through. The transfer gate TM 3 becomes conductive in response to an inverted signal of the up / down count determination signal REQ and passes the complementary clock signal. Accordingly, the transmission gate TM 5 becomes conductive depending on the up / down count determination signal REQ and passes a complementary clock signal. The transmission gate TM 7 becomes conductive in response to the complementary signal of the up / down count determination signal REQ and transmits the clock signal B.

The NAND gate NA 1 receives a single pulse signal CK, an output signal from one of the transmission gates TM 1 and TM 3 and an output signal from one of the transmission gates TM 5 and TM 7 . The inverter circuit I 50 receives the output signal of the NAND gate NA 1 . A complementary selection determination signal is output by the NAND gate N 1 and a selection determination signal Φ 0 is output by the inverter I 50 . The operation will now be briefly described.

It is assumed that the up / down count determination signal REQ is high "H", thereby specifying an up count operation. In this case, the transmission gates TM 1 and TM 5 are blocked and the clock signals A and are selected and supplied to the NAND gate NA 1 . The NAND gate NA 1 outputs an "L" signal only if all the input signals are "H". Therefore, if the single pulse signal CK, which is generated when the control signal changes from "H" to "L", is generated and the clock signals A and both are "H", the selection determination signal Φ 0 rises to "H". That is, when the preset signals PR 0 and PR 1 indicating the initial state are both "L", the selection determination signal Φ 0 is generated first.

If the up / down count determination signal REQ is at the "H" level, the complementary clock signal and the clock signal B are selected in the clock signal generation circuit 73 . If the up / down count determination signal REQ is "L", the clock signal A and the complementary clock signal are selected.

If the up / down count determination signal REQ is at the "H" level, the clock signals A and B are selected in the clock signal generating circuit 75 . If the up / down count determination signal REQ is "L", the complementary clock signals and are selected.

If the up / down count determination signal REQ is at the "H" level, the complementary clock signals and are selected in the clock signal generating circuit 77 . If the up / down count determination signal REQ is "L", the clock signals A and B are selected.

Accordingly, in the structure described above, if the up / down count determination signal REQ is "H", the selection determination signals Φ 0 , Φ 1 , Φ 2 and Φ 3 become in this order in response to the falling edge of the control signal from "H" - to the "L" level.

If the up / down count determination signal REQ is "L", the selection determination signals Φ 1 , Φ 0 , Φ 3 and Φ 2 are generated in this order.

Which of the selection determination signals is to be activated is suitably set in accordance with the preset signals PR 0 and PR 1 .

By appropriately setting the combination of the signals selected in the clock signal generation circuits 71 to 77 when the down count determination signal is "H", the control signals can be generated in the order Φ 3 , Φ 2 , Φ 1 and Φ 0 if the default value of counters 60 and 62 is (00). In this case, the clock signal generating circuits 71 , 73 , 75 and 77 can be connected such that the signal combinations (,), (A, B), (, B) and (A,) are selected depending on the determination signal. In this case, the signal B () is shared in the clock signal generating circuits 71 to 77 independently of the determination signals REQ and so that the transmission gate for the signal B () can be omitted. This simplifies the circuit structure.

By appropriately inverting the up / down count determination signal REQ, the order of the output data is reversed, see above that the same data is read in reverse order can. This leads e.g. to form mirror images at the Image processing.

Although a dynamic semiconductor memory device as a case game for the memory IC has been described, the vorlie ing invention applied to any storage devices are accessed bit by bit as long as the memory cell array can be. The present invention can e.g. to static Semiconductor memory devices, read-only memories or the like Storage devices are applied.

Although the selection signals Φ 0 to Φ 3 , the preset signal, the up / down count determination signal, and the clock signal for counting are externally applied in the above-described embodiment, signals which set such operations can also be generated internally by various clock signals from the basic Control signals,,, and etc. are generated, which are also used in general memory devices.

Although the preset signals PR 0 and PR 1 for determining the preset values are externally applied in the control circuit 50 using separate pins, they can also be applied using a conventional address pin, a file input / output pin, etc.

As has been described above, according to the invention, in one Memory IC with a memory cell array, on the bitwise can be accessed, a plurality of bits of parallel read Convert data depending on clock signals to serial data tated to be output sequentially, thereby output data can be provided at high speed without a data collision occurs on the data output bus.

Since the serial data is output from a memory IC it does not require the access time, the deactivation time etc. to consider a data collision of the output data avoid. Thus the timing design of the memory system be simplified because the data output clocking by a clock signal he follows.

Claims (7)

1. A memory IC with a parallel-serial conversion function, comprising a memory cell array ( 32 ), which can be optionally accessed with a plurality of bits each and which comprises a plurality of memory cells which are arranged in rows and columns, one external address signal dependent means ( 34 , 36 , 38 , 40 ) for selecting memory cells corresponding to the plurality of bits in the memory cell array to read data from the selected memory cells, first means ( 44 ) for receiving the read data from a plurality of in parallel Bits, a second device ( 46 , 50 ) for converting the parallel data received by the first device into serial data in order to output them as output data, the second device having a device ( 50 , PG) for generating a clock signal, a device ( 60 , 62 ) for counting the clock signal, and a device dependent on the count value of the counting device (TG 1 , TG 2 , TG 3 , TG 4 ) for the selective and successive transmission of the data received by the first device. 2. A memory IC according to claim 1, characterized in that the clock signal generating device comprises a device (PG) dependent on a clock signal indicating the data reading device for generating a single pulse signal having a predetermined width, and in that the device for successively passing one of the count value Counting means and means ( 71 , 73 , 75 , 77 ) dependent on the single-pulse signal for generating a bit selection signal, and means (TG 1 to TG 4 ) dependent on the bit selection signal for selectively passing the read plurality of data bits bit by bit. 3. Memory IC according to claim 2, characterized in that the counting means (L 1 , L 3 , I 30 , I 40 ) for outputting the count value in binary notation and for outputting an inverted signal of the binary value of each digit of the count value, and that the bit selection signal generating means logic gates (NA 1 ), which are formed for each bit of the plurality of data bits and are dependent on the signal of the predetermined combination, for receiving a predetermined combination of the bit values of each digit of the count value and its inverted Signals as well as the single pulse signal to generate the bit selection signal. 4. Memory IC according to claim 3, characterized in that the bit selection signal generating device further comprises a first transmission device (TM 1 , TM 5 ), which is dependent on a signal for determining a first data reading order, to a first signal combination of the output signals from the Allow metering device to pass and apply it to an associated logic gate, and a second transmission device (TM 3 , TM 7 ), which is dependent on a signal for establishing a second data reading order, which is complementary to the signal for determining the first data reading order, for a second signal combination to pass the output signals from the counter and to apply them to the associated logic gate, the first and second transmission means being formed corresponding to each bit of the plurality of data bits. 5. Memory IC according to claim 1, characterized in that the plurality of data bits is equal to four data bits, and the counting device a first counter ( 60 ) with a first locking circuit (L 1 ), the first and a second node ( H) and consists of inverters cross-coupled between the first and second nodes, a second latch circuit (L 2 ) which has third and fourth nodes and inverters cross-coupled between the third and fourth nodes, a first inverter (I 30 ) for inverting the signal potential at the first node to output a signal which indicates the lower bit value of the count value, a first switching element (ST 2 ), which is dependent on the clock signal, for transmitting the output signal from the first inverter to the third node, and with a second switching element (ST 1 ), which is dependent on a complementary signal of the clock signal, for connecting the fourth node to the second Node, and a second counter ( 62 ) with a third latch circuit (L 3 ), which has a fifth and a sixth node (G) and consists of inverters cross-coupled between the fifth and sixth nodes, a fourth latch circuit (L 4 ), which has a seventh and eighth node and inverters cross-coupled between the seventh and eighth nodes, a second inverter (I 40 ) for inverting the signal potential at the fifth node in order to output a signal which indicates the high-order bit of the counting value of the counter, a fourth Switching element (ST 4 ), which is dependent on the signal potential at the first node, for connecting the fifth node to a ninth node (F), a fifth switching element (ST 16 ), which is dependent on the output signal of the first inverter, for transmitting the output signal from the second inverter to the ninth node, a sixth switching element (ST 10 ), which is dependent on the clock signal, for Connecting the eighth node to the sixth node, and a seventh switching element (ST 12 ), which is dependent on the complementary signal of the clock signal, for connecting the ninth node to the seventh node. 6. Operating method for a memory IC with a memory cell field that can be addressed with a plurality of bits and has a data output connection, characterized by the steps:
Selecting memory cells corresponding to the plurality of bits in the memory cell array depending on an external address and reading data in parallel from the selected memory cells, and converting the data read out in parallel into serial data for transferring them to the output terminal, the step of converting the parallel Data in the serial data comprises the steps of generating a clock signal, counting the clock signal, and selectively transferring the memory cell data read in parallel bit by bit to the output terminal as a function of a count value of the clock signal. 7. Operating method according to claim 6, characterized in that the step of selective transfer, the steps of applying the parallel read memory cell data in parallel to a United amplifier ( 44 ), and selectively passing the output signal of the amplifier according to the count value to apply this to the output terminal , includes.