DE3850514D1 - Cachespeicher mit Treffervorhersagelogik. - Google Patents

Cachespeicher mit Treffervorhersagelogik.

Info

Publication number: DE3850514D1
Authority: DE; Germany
Prior art keywords: cache; prediction logic; hit prediction; hit; logic
Prior art date: 1987-03-25
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE3850514T

Other languages

English (en)

Other versions

DE3850514T2 (de

Inventor

Claudio Fiacconi

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Bull HN Information Systems Italia SpA

Bull HN Information Systems Inc

Original Assignee

Bull HN Information Systems Italia SpA

Bull HN Information Systems Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1987-03-25

Filing date

1988-03-14

Publication date

1994-08-11

1988-03-14 Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA

1994-08-11 Application granted granted Critical

1994-08-11 Publication of DE3850514D1 publication Critical patent/DE3850514D1/de

1994-10-27 Publication of DE3850514T2 publication Critical patent/DE3850514T2/de

2008-03-15 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

DE3850514T 1987-03-25 1988-03-14 Cachespeicher mit Treffervorhersagelogik. Expired - Fee Related DE3850514T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
IT19832/87A IT1202687B (it)	1987-03-25	1987-03-25	Memoria tampone a predizione di hit

Publications (2)

Publication Number	Publication Date
DE3850514D1 true DE3850514D1 (de)	1994-08-11
DE3850514T2 DE3850514T2 (de)	1994-10-27

Family

ID=11161653

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE3850514T Expired - Fee Related DE3850514T2 (de)	1987-03-25	1988-03-14	Cachespeicher mit Treffervorhersagelogik.

Country Status (4)

Country	Link
US (1)	US4912626A (de)
EP (1)	EP0283891B1 (de)
DE (1)	DE3850514T2 (de)
IT (1)	IT1202687B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5151982A (en) *	1988-03-30	1992-09-29	Kabushiki Kaisha Toshiba	Data processing system
US5123097A (en) *	1989-01-05	1992-06-16	Bull Hn Information Systems Inc.	Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5093777A (en) *	1989-06-12	1992-03-03	Bull Hn Information Systems Inc.	Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
JPH04233642A (ja) *	1990-07-27	1992-08-21	Dell Usa Corp	キャッシュアクセスと並列的にメモリアクセスを行なうプロセッサ及びそれに用いられる方法
US5392414A (en) *	1992-06-30	1995-02-21	Sun Microsystems, Inc.	Rapid data retrieval from data storage structures using prior access predictive annotations
US5513143A (en) *	1992-07-31	1996-04-30	Sgs-Thomson Microelectronics, Inc.	Data cache memory internal circuitry for reducing wait states
US5553270A (en) *	1993-09-01	1996-09-03	Digital Equipment Corporation	Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay
US5548739A (en) *	1993-11-04	1996-08-20	Sun Microsystems, Inc.	Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations
US5987561A (en)	1995-08-31	1999-11-16	Advanced Micro Devices, Inc.	Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5752069A (en) *	1995-08-31	1998-05-12	Advanced Micro Devices, Inc.	Superscalar microprocessor employing away prediction structure
US5860104A (en) *	1995-08-31	1999-01-12	Advanced Micro Devices, Inc.	Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates
US5838943A (en) *	1996-03-26	1998-11-17	Advanced Micro Devices, Inc.	Apparatus for speculatively storing and restoring data to a cache memory
GB2378779B (en) *	2001-08-14	2005-02-02	Advanced Risc Mach Ltd	Accessing memory units in a data processing apparatus
US7117290B2 (en) *	2003-09-03	2006-10-03	Advanced Micro Devices, Inc.	MicroTLB and micro tag for reducing power in a processor
US20050050278A1 (en) *	2003-09-03	2005-03-03	Advanced Micro Devices, Inc.	Low power way-predicted cache
US7395372B2 (en) *	2003-11-14	2008-07-01	International Business Machines Corporation	Method and system for providing cache set selection which is power optimized
US10257264B1 (en) *	2016-02-22	2019-04-09	Yume, Inc.	System and method for reducing data center latency

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4170039A (en) *	1978-07-17	1979-10-02	International Business Machines Corporation	Virtual address translation speed up technique
US4363095A (en) *	1980-12-31	1982-12-07	Honeywell Information Systems Inc.	Hit/miss logic for a cache memory
US4445177A (en) *	1981-05-22	1984-04-24	Data General Corporation	Digital data processing system utilizing a unique arithmetic logic unit for handling uniquely identifiable addresses for operands and instructions
US4458310A (en) *	1981-10-02	1984-07-03	At&T Bell Laboratories	Cache memory using a lowest priority replacement circuit
US4603380A (en) *	1983-07-01	1986-07-29	International Business Machines Corporation	DASD cache block staging

1987
- 1987-03-25 IT IT19832/87A patent/IT1202687B/it active
1988
- 1988-03-14 DE DE3850514T patent/DE3850514T2/de not_active Expired - Fee Related
- 1988-03-14 EP EP88103991A patent/EP0283891B1/de not_active Expired - Lifetime
- 1988-03-15 US US07/168,309 patent/US4912626A/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
DE3850514T2 (de)	1994-10-27
US4912626A (en)	1990-03-27
IT1202687B (it)	1989-02-09
EP0283891A3 (en)	1990-07-18
EP0283891A2 (de)	1988-09-28
EP0283891B1 (de)	1994-07-06
IT8719832A0 (it)	1987-03-25

Legal Events

Date	Code	Title	Description
1995-08-03	8364	No opposition during term of opposition
2001-03-15	8328	Change in the person/name/address of the agent	Free format text: PATENTANWAELTE RUFF, WILHELM, BEIER, DAUSTER & PARTNER, 70173 STUTTGART
2006-01-05	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE3870716D1 (de)	1992-06-11	Tastatur mit modifizierbarer konfiguration.
DE3850514D1 (de)	1994-08-11	Cachespeicher mit Treffervorhersagelogik.
DE3688192T2 (de)	1993-11-04	Seitenorganisierter cachespeicher mit virtueller adressierung.
DE68924313D1 (de)	1995-10-26	Mehrprozessoranordnungen mit kreuzweise abgefragten Schreib-in-Cachespeichern.
DE68923863D1 (de)	1995-09-21	Ein-/Ausgabecachespeicherung.
DE69023568D1 (de)	1995-12-21	Cache-Speicheranordnung.
FI891370A (fi)	1989-03-22	Vattenloesliga fyllmedel.
DE68924951T2 (de)	1996-04-18	Herzschrittmacher mit adaptiver Schrittfrequenz.
DE68919962T2 (de)	1995-07-06	Kombinierte kryogen-mechanische Gefriereinrichtung.
DE3867110D1 (de)	1992-02-06	Fahrzeugtuer mit geteilter aussenschale.
NO884557L (no)	1989-04-20	Borkrone med diamanter e.l.
DE3852695T2 (de)	1995-06-29	Multiprozessorsystem mit mehreren Speichern.
DE68916563D1 (de)	1994-08-11	Speicheranordnung mit Vorhersage der Bausteinauswahl.
DE3873388D1 (de)	1992-09-10	Cache-speicher.
DE3885008D1 (de)	1993-11-25	Zwischenschicht mit niedrigem Modul.
DE3881896T2 (de)	1993-11-18	Gefrieranordnung.
DE68924945T2 (de)	1996-04-18	Pufferspeicheranordnung.
DE68924125D1 (de)	1995-10-12	Logikanalysator mit Doppel-Triggerung.
DE3579636D1 (de)	1990-10-18	Mechanismus mit schwingender bewegung.
DE3483016D1 (de)	1990-09-27	Assoziativer matrixprozessor.
DE3751252T2 (de)	1995-08-24	Mikroprozessor mit selektivem Cachespeicher.
DE68903288T2 (de)	1993-05-19	Schlagstock mit kreuzgriff.
DE3850608D1 (de)	1994-08-18	Cache-Speicheranordnung.
DE69015145D1 (de)	1995-01-26	Rechner mit cache-speicher.
DE69001478D1 (de)	1993-06-03	Kuehlschrank.