DE3786669T4 - Programmierbare logische zelle und matrix. - Google Patents

Programmierbare logische zelle und matrix.

Info

Publication number
DE3786669T4
DE3786669T4 DE3786669T DE3786669T DE3786669T4 DE 3786669 T4 DE3786669 T4 DE 3786669T4 DE 3786669 T DE3786669 T DE 3786669T DE 3786669 T DE3786669 T DE 3786669T DE 3786669 T4 DE3786669 T4 DE 3786669T4
Authority
DE
Germany
Prior art keywords
matrix
programmable logical
logical cell
programmable
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3786669T
Other languages
English (en)
Other versions
DE3786669T2 (de
DE3786669D1 (de
Inventor
Frederick Furtek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Concurrent Logic Inc
Original Assignee
Concurrent Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Concurrent Logic Inc filed Critical Concurrent Logic Inc
Publication of DE3786669T2 publication Critical patent/DE3786669T2/de
Application granted granted Critical
Publication of DE3786669T4 publication Critical patent/DE3786669T4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
DE3786669T 1986-11-07 1987-11-04 Programmierbare logische zelle und matrix. Expired - Lifetime DE3786669T4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/928,527 US4918440A (en) 1986-11-07 1986-11-07 Programmable logic cell and array
PCT/US1987/002912 WO1988003727A1 (en) 1986-11-07 1987-11-04 Programmable logic cell and array

Publications (2)

Publication Number Publication Date
DE3786669T2 DE3786669T2 (de) 1994-03-31
DE3786669T4 true DE3786669T4 (de) 1995-02-02

Family

ID=25456360

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3786669T Expired - Lifetime DE3786669T4 (de) 1986-11-07 1987-11-04 Programmierbare logische zelle und matrix.
DE8787907712A Expired - Fee Related DE3786669D1 (de) 1986-11-07 1987-11-04 Programmierbare logische zelle und matrix.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8787907712A Expired - Fee Related DE3786669D1 (de) 1986-11-07 1987-11-04 Programmierbare logische zelle und matrix.

Country Status (8)

Country Link
US (1) US4918440A (de)
EP (1) EP0326580B1 (de)
JP (1) JP2701859B2 (de)
AU (1) AU8325487A (de)
CA (1) CA1287122C (de)
DE (2) DE3786669T4 (de)
PH (1) PH30200A (de)
WO (1) WO1988003727A1 (de)

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089973A (en) * 1986-11-07 1992-02-18 Apple Computer Inc. Programmable logic cell and array
US4964056A (en) * 1987-03-25 1990-10-16 Hitachi, Ltd. Automatic design system of logic circuit
DE3718916A1 (de) * 1987-06-05 1988-12-15 Siemens Ag Verbindungsnetzwerk zur einstellbaren verbindung von schaltungsanordnungen, insbesondere programmierbaren schaltungsanordnungen
DE3718915A1 (de) * 1987-06-05 1988-12-15 Siemens Ag Programmierbare schaltungsanordnung
US5644497A (en) * 1988-03-15 1997-07-01 Hyman; Edward Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array
US5377123A (en) * 1992-06-08 1994-12-27 Hyman; Edward Programmable logic device
US5253363A (en) * 1988-03-15 1993-10-12 Edward Hyman Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5369593A (en) 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5144166A (en) * 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5322812A (en) 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5338984A (en) * 1991-08-29 1994-08-16 National Semiconductor Corp. Local and express diagonal busses in a configurable logic array
US5298805A (en) * 1991-08-29 1994-03-29 National Semiconductor Corporation Versatile and efficient cell-to-local bus interface in a configurable logic array
JPH05252025A (ja) * 1991-10-28 1993-09-28 Texas Instr Inc <Ti> 論理モジュールおよび集積回路
US5367209A (en) * 1992-01-07 1994-11-22 Hauck Scott A Field programmable gate array for synchronous and asynchronous operation
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
DE69330974T2 (de) * 1992-07-02 2002-05-29 Atmel Corp Unterbrechungsfreies wahlfreies Zugriffspeichersystem
DE69331085T2 (de) * 1992-08-26 2002-03-14 Matsushita Electric Ind Co Ltd Automatisiertes LSI-Entwurfsystem und Verfahren
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
CH688425A5 (fr) * 1993-05-24 1997-09-15 Suisse Electronique Microtech Circuit électronique organisé en réseau matriciel de cellules.
GB9312674D0 (en) * 1993-06-18 1993-08-04 Pilkington Micro Electronics Configurabel logic array
GB2312308B (en) * 1993-06-18 1998-01-21 Pilkington Micro Electronics Configurable logic array
US6462578B2 (en) 1993-08-03 2002-10-08 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US6051991A (en) * 1993-08-03 2000-04-18 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5457410A (en) 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5959871A (en) * 1993-12-23 1999-09-28 Analogix/Portland State University Programmable analog array circuit
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5732233A (en) * 1995-01-23 1998-03-24 International Business Machines Corporation High speed pipeline method and apparatus
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5742180A (en) * 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5850564A (en) 1995-05-03 1998-12-15 Btr, Inc, Scalable multiple level tab oriented interconnect architecture
AU5718196A (en) 1995-05-03 1996-11-21 Btr, Inc. Scalable multiple level interconnect architecture
US5646544A (en) * 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5777489A (en) 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US6035106A (en) 1997-04-28 2000-03-07 Xilinx, Inc. Method and system for maintaining hierarchy throughout the integrated circuit design process
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
CA2257996A1 (en) * 1996-06-10 1997-12-18 Mark R. Cummings Method and apparatus for compiling one circuit in a sequence of circuits within a programmable gate array
US6034547A (en) 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
US6624658B2 (en) 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
DE19651075A1 (de) * 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US6107824A (en) * 1997-10-16 2000-08-22 Altera Corporation Circuitry and methods for internal interconnection of programmable logic devices
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
JP3576837B2 (ja) * 1998-10-30 2004-10-13 日本電気株式会社 プログラマブルロジックｌｓｉの基本セル及び基本セル２次元アレイ
EP1005162A3 (de) * 1998-11-26 2003-04-02 International Business Machines Corporation Schaltung und Verfahren zum Erzeugen kombinatorischer logischer Funktionen
US6407576B1 (en) * 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
EP1228440B1 (de) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequenz-partitionierung auf zellstrukturen
US6215327B1 (en) * 1999-09-01 2001-04-10 The United States Of America As Represented By The Secretary Of The Air Force Molecular field programmable gate array
US7678048B1 (en) * 1999-09-14 2010-03-16 Siemens Medical Solutions Usa, Inc. Medical diagnostic ultrasound system and method
US6320412B1 (en) 1999-12-20 2001-11-20 Btr, Inc. C/O Corporate Trust Co. Architecture and interconnect for programmable logic circuits
ATE476700T1 (de) 2000-06-13 2010-08-15 Richter Thomas Pipeline ct-protokolle und -kommunikation
DE10049629C1 (de) * 2000-10-05 2002-08-01 Hagen Sankowski Programmierbare Schaltungsanordnung
US7595659B2 (en) * 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
WO2005045692A2 (en) * 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
JP2004533691A (ja) 2001-06-20 2004-11-04 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データを処理するための方法
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US6594810B1 (en) 2001-10-04 2003-07-15 M2000 Reconfigurable integrated circuit with a scalable architecture
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6654944B1 (en) * 2002-06-28 2003-11-25 Intel Corporation Two-dimensional C-element array
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
JP4388895B2 (ja) 2002-09-06 2009-12-24 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト リコンフィギュアラブルなシーケンサ構造
US7255437B2 (en) * 2003-10-09 2007-08-14 Howell Thomas A Eyeglasses with activity monitoring
US8144156B1 (en) 2003-12-31 2012-03-27 Zii Labs Inc. Ltd. Sequencer with async SIMD array
US6975139B2 (en) * 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7460529B2 (en) * 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US7478261B2 (en) * 2005-09-13 2009-01-13 M2000 Reconfigurable circuit with redundant reconfigurable cluster(s)
US8010826B2 (en) * 2005-09-13 2011-08-30 Meta Systems Reconfigurable circuit with redundant reconfigurable cluster(s)
US7275196B2 (en) 2005-11-23 2007-09-25 M2000 S.A. Runtime reconfiguration of reconfigurable circuits
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
US7423453B1 (en) 2006-01-20 2008-09-09 Advantage Logic, Inc. Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
US7693257B2 (en) * 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
WO2010011813A1 (en) * 2008-07-23 2010-01-28 Alkermes, Inc. Complex of trospium and pharmaceutical compositions thereof
US7999570B2 (en) 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US31287A (en) * 1861-02-05 aiken
GB1101851A (en) * 1965-01-20 1968-01-31 Ncr Co Generalized logic circuitry
US3446990A (en) * 1965-12-10 1969-05-27 Stanford Research Inst Controllable logic circuits employing functionally identical gates
US3818252A (en) * 1971-12-20 1974-06-18 Hitachi Ltd Universal logical integrated circuit
US3818452A (en) * 1972-04-28 1974-06-18 Gen Electric Electrically programmable logic circuits
US4034356A (en) * 1975-12-03 1977-07-05 Ibm Corporation Reconfigurable logic array
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
US4068214A (en) * 1976-02-03 1978-01-10 Massachusetts Institute Of Technology Asynchronous logic array
US4240094A (en) * 1978-03-20 1980-12-16 Harris Corporation Laser-configured logic array
JPS558135A (en) * 1978-07-04 1980-01-21 Mamoru Tanaka Rewritable programable logic array
US4293783A (en) * 1978-11-01 1981-10-06 Massachusetts Institute Of Technology Storage/logic array
DE2944794C2 (de) * 1979-11-06 1981-11-12 Siemens AG, 1000 Berlin und 8000 München Breitband-Koppelanordnung
JPS56153839A (en) * 1980-04-30 1981-11-28 Nec Corp Pla logical operation circuit
US4451895A (en) * 1980-07-17 1984-05-29 Telesis Corporation Of Delaware, Inc. Interactive computer aided design system
US4467439A (en) * 1981-06-30 1984-08-21 Ibm Corporation OR Product term function in the search array of a PLA
US4422072A (en) * 1981-07-30 1983-12-20 Signetics Corporation Field programmable logic array circuit
US4414547A (en) * 1981-08-05 1983-11-08 General Instrument Corporation Storage logic array having two conductor data column
US4566064A (en) * 1982-05-10 1986-01-21 American Microsystems, Inc. Combinational logic structure using PASS transistors
JPS6017932A (ja) * 1983-07-09 1985-01-29 Fujitsu Ltd ゲ−ト・アレイ
US4600846A (en) * 1983-10-06 1986-07-15 Sanders Associates, Inc. Universal logic circuit modules
US4642487A (en) * 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
DE3587944T2 (de) * 1985-04-17 1995-04-20 Xilinx Inc Konfigurierbare logische Matrix.
US4700187A (en) * 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array

Also Published As

Publication number Publication date
DE3786669T2 (de) 1994-03-31
JPH01501671A (ja) 1989-06-08
PH30200A (en) 1997-02-05
AU8325487A (en) 1988-06-01
JP2701859B2 (ja) 1998-01-21
EP0326580A1 (de) 1989-08-09
DE3786669D1 (de) 1993-08-26
US4918440A (en) 1990-04-17
WO1988003727A1 (en) 1988-05-19
EP0326580B1 (de) 1993-07-21
CA1287122C (en) 1991-07-30

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