DE3688088T2 - Integrierte halbleiterschaltung. - Google Patents

Integrierte halbleiterschaltung.

Info

Publication number
DE3688088T2
DE3688088T2 DE8686300539T DE3688088T DE3688088T2 DE 3688088 T2 DE3688088 T2 DE 3688088T2 DE 8686300539 T DE8686300539 T DE 8686300539T DE 3688088 T DE3688088 T DE 3688088T DE 3688088 T2 DE3688088 T2 DE 3688088T2
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
integrated
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686300539T
Other languages
English (en)
Other versions
DE3688088D1 (de
Inventor
Takayasu Sakurai
Tetsuya Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3688088D1 publication Critical patent/DE3688088D1/de
Application granted granted Critical
Publication of DE3688088T2 publication Critical patent/DE3688088T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
DE8686300539T 1985-01-26 1986-01-27 Integrierte halbleiterschaltung. Expired - Lifetime DE3688088T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60013068A JPH0738583B2 (ja) 1985-01-26 1985-01-26 半導体集積回路

Publications (2)

Publication Number Publication Date
DE3688088D1 DE3688088D1 (de) 1993-04-29
DE3688088T2 true DE3688088T2 (de) 1993-07-29

Family

ID=11822824

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686300539T Expired - Lifetime DE3688088T2 (de) 1985-01-26 1986-01-27 Integrierte halbleiterschaltung.

Country Status (5)

Country Link
US (2) US4740713A (de)
EP (1) EP0190027B1 (de)
JP (1) JPH0738583B2 (de)
KR (1) KR890004958B1 (de)
DE (1) DE3688088T2 (de)

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JPH0738583B2 (ja) * 1985-01-26 1995-04-26 株式会社東芝 半導体集積回路
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JP2585599B2 (ja) * 1987-06-05 1997-02-26 株式会社日立製作所 出力インタ−フエ−ス回路
US4806801A (en) * 1987-08-27 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories TTL compatible CMOS input buffer having a predetermined threshold voltage and method of designing same
US4782250A (en) * 1987-08-31 1988-11-01 International Business Machines Corporation CMOS off-chip driver circuits
NL8702630A (nl) * 1987-11-04 1989-06-01 Philips Nv Geintegreerde digitale schakeling.
JPH01233755A (ja) * 1988-03-14 1989-09-19 Nec Corp 半導体集積回路装置
JPH0716158B2 (ja) * 1988-05-13 1995-02-22 日本電気株式会社 出力回路およびそれを用いた論理回路
IT1225607B (it) * 1988-07-06 1990-11-22 Sgs Thomson Microelectronics Circuito logico cmos per alta tensione
JPH07109859B2 (ja) * 1988-09-03 1995-11-22 日本電気株式会社 Ｍｏｓ型半導体集積回路装置
US5057715A (en) * 1988-10-11 1991-10-15 Intel Corporation CMOS output circuit using a low threshold device
JPH02159818A (ja) * 1988-12-13 1990-06-20 Toshiba Corp 半導体集積回路
US5015889A (en) * 1989-02-23 1991-05-14 Reay Robert L Schottky enhanced CMOS output circuit
US5089728A (en) * 1989-09-06 1992-02-18 National Semiconductor Corporation Spike current reduction in cmos switch drivers
US4963771A (en) * 1989-09-12 1990-10-16 Samsung Semiconductor TTL/CMOS level translator
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US5187686A (en) * 1990-02-14 1993-02-16 Zilog, Inc. Control circuit having outputs with differing rise and fall times
US5239237A (en) * 1990-02-14 1993-08-24 Zilog, Inc. Control circuit having outputs with differing rise and fall times
US5751643A (en) * 1990-04-06 1998-05-12 Mosaid Technologies Incorporated Dynamic memory word line driver
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GB2243233A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM word line driver
JP2894635B2 (ja) * 1990-11-30 1999-05-24 株式会社東芝 半導体記憶装置
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JPH06505375A (ja) * 1991-02-12 1994-06-16 アナログ・ディバイセス・インコーポレーテッド Ｍｏｓ回路に対する利得線形性補正回路
JP3556679B2 (ja) 1992-05-29 2004-08-18 株式会社半導体エネルギー研究所 電気光学装置
JPH04341009A (ja) * 1991-05-17 1992-11-27 Nec Corp 半導体集積回路装置
KR940009696B1 (ko) * 1991-10-08 1994-10-15 현대전자산업주식회사 열 캐리어 방지 회로
US5274276A (en) * 1992-06-26 1993-12-28 Micron Technology, Inc. Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
US5389842A (en) * 1992-08-10 1995-02-14 Nippon Steel Semiconductor Corporation Latch-up immune CMOS output driver
US5486778A (en) * 1993-03-10 1996-01-23 Brooktree Corporation Input buffer for translating TTL levels to CMOS levels
US5378943A (en) * 1993-04-20 1995-01-03 International Business Machines Corporation Low power interface circuit
US5406140A (en) * 1993-06-07 1995-04-11 National Semiconductor Corporation Voltage translation and overvoltage protection
DE4334513C1 (de) * 1993-10-09 1994-10-20 Itt Ind Gmbh Deutsche CMOS-Schaltung mit erhöhter Spannungsfestigkeit
US5465054A (en) * 1994-04-08 1995-11-07 Vivid Semiconductor, Inc. High voltage CMOS logic using low voltage CMOS process
JP3407975B2 (ja) * 1994-05-20 2003-05-19 株式会社半導体エネルギー研究所 薄膜半導体集積回路
US5682116A (en) * 1994-06-07 1997-10-28 International Business Machines Corporation Off chip driver having slew rate control and differential voltage protection circuitry
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
KR0124141B1 (ko) * 1994-12-29 1998-10-01 김광호 반도체 메모리장치의 데이타 출력 버퍼회로
US5835970A (en) * 1995-12-21 1998-11-10 Cypress Semiconductor Corp. Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
US6043684A (en) * 1995-12-20 2000-03-28 Cypress Semiconductor Corp. Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
US6411140B1 (en) 1995-12-20 2002-06-25 Cypress Semiconductor Corporation Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
US5903174A (en) * 1995-12-20 1999-05-11 Cypress Semiconductor Corp. Method and apparatus for reducing skew among input signals within an integrated circuit
US5604449A (en) * 1996-01-29 1997-02-18 Vivid Semiconductor, Inc. Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes
KR100396831B1 (ko) * 1996-02-26 2003-11-17 주식회사 하이닉스반도체 절전형인버터회로
US6118302A (en) 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
GB2349998B (en) * 1996-05-28 2001-02-28 Altera Corp Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions
US5874836A (en) * 1996-09-06 1999-02-23 International Business Machines Corporation High reliability I/O stacked fets
JP4036923B2 (ja) * 1997-07-17 2008-01-23 株式会社半導体エネルギー研究所 表示装置およびその駆動回路
US5925913A (en) * 1997-08-25 1999-07-20 Advanced Micro Devices, Inc. System for enhancing the performance of a circuit by reducing the channel length of one or more transistors
US5889416A (en) * 1997-10-27 1999-03-30 Cypress Semiconductor Corporation Symmetrical nand gates
US6097222A (en) * 1997-10-27 2000-08-01 Cypress Semiconductor Corp. Symmetrical NOR gates
US6278295B1 (en) 1998-02-10 2001-08-21 Cypress Semiconductor Corp. Buffer with stable trip point
US6023176A (en) * 1998-03-27 2000-02-08 Cypress Semiconductor Corp. Input buffer
KR100301809B1 (ko) * 1998-11-24 2001-09-06 김영환 데이터 입출력 버퍼 제어회로_
ATE390761T1 (de) * 1999-06-29 2008-04-15 Cochlear Ltd Schutzschaltung gegen hochspannung für standard cmos prozess
US6329841B1 (en) * 2000-03-02 2001-12-11 Advanced Micro Devices, Inc. Level-shifter for extremely low power supply
JP3680122B2 (ja) 2001-08-10 2005-08-10 シャープ株式会社 基準電圧発生回路
JP2003281890A (ja) 2002-03-25 2003-10-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US7002392B2 (en) * 2004-02-20 2006-02-21 Fujitsu Limited Converting signals from a low voltage domain to a high voltage domain
JP4706381B2 (ja) * 2004-10-22 2011-06-22 株式会社デンソー 半導体装置
JP4787554B2 (ja) * 2005-07-01 2011-10-05 パナソニック株式会社 入出力回路装置
US7248521B2 (en) * 2005-07-12 2007-07-24 Micron Technology, Inc. Negative voltage discharge scheme to improve snapback in a non-volatile memory
US7705642B2 (en) * 2007-02-08 2010-04-27 Mosaid Technologies Incorporated Simplified bias circuitry for differential buffer stage with symmetric loads
US8000137B2 (en) 2008-03-27 2011-08-16 Genusion, Inc. Nonvolatile semiconductor memory device and usage method thereof
JP2010141496A (ja) * 2008-12-10 2010-06-24 Seiko Epson Corp 半導体集積回路、半導体集積回路の駆動方法、電子機器および電子機器の駆動方法
US8610470B2 (en) 2008-12-10 2013-12-17 Seiko Epson Corporation Inverter circuit
JP5331087B2 (ja) * 2010-11-10 2013-10-30 シャープ株式会社 ドライバ回路、及び、インバータ回路
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Also Published As

Publication number Publication date
US4857763A (en) 1989-08-15
DE3688088D1 (de) 1993-04-29
KR860006137A (ko) 1986-08-18
EP0190027B1 (de) 1993-03-24
JPH0738583B2 (ja) 1995-04-26
JPS61172435A (ja) 1986-08-04
EP0190027A2 (de) 1986-08-06
KR890004958B1 (ko) 1989-12-02
US4740713A (en) 1988-04-26
EP0190027A3 (en) 1988-09-28

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