DE3684557D1 - Waferintegrierte halbleiteranordnung. - Google Patents

Waferintegrierte halbleiteranordnung.

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Publication number
DE3684557D1
DE3684557D1 DE8686113735T DE3684557T DE3684557D1 DE 3684557 D1 DE3684557 D1 DE 3684557D1 DE 8686113735 T DE8686113735 T DE 8686113735T DE 3684557 T DE3684557 T DE 3684557T DE 3684557 D1 DE3684557 D1 DE 3684557D1
Authority
DE
Germany
Prior art keywords
wafer
integrated semiconductor
semiconductor arrangement
arrangement
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686113735T
Other languages
English (en)
Inventor
Toshitaka Fujitsu Lt Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3684557D1 publication Critical patent/DE3684557D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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DE8686113735T 1985-10-05 1986-10-03 Waferintegrierte halbleiteranordnung. Expired - Fee Related DE3684557D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60222593A JPS6281745A (ja) 1985-10-05 1985-10-05 ウエハ−規模のlsi半導体装置とその製造方法

Publications (1)

Publication Number Publication Date
DE3684557D1 true DE3684557D1 (de) 1992-04-30

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Application Number Title Priority Date Filing Date
DE8686113735T Expired - Fee Related DE3684557D1 (de) 1985-10-05 1986-10-03 Waferintegrierte halbleiteranordnung.

Country Status (5)

Country Link
US (1) US4907062A (de)
EP (1) EP0222144B1 (de)
JP (1) JPS6281745A (de)
KR (1) KR900008018B1 (de)
DE (1) DE3684557D1 (de)

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US5008213A (en) * 1988-12-09 1991-04-16 The United States Of America As Represented By The Secretary Of The Air Force Hybrid wafer scale microcircuit integration
US4987295A (en) * 1989-03-31 1991-01-22 General Electric Company Multichip imager with improved optical performance near the butt region
US5075253A (en) * 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5161093A (en) * 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
FR2667443A1 (fr) * 1990-09-28 1992-04-03 Thomson Csf Procede de realisation d'un module hybride.
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
JP2960560B2 (ja) * 1991-02-28 1999-10-06 株式会社日立製作所 超小型電子機器
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
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JPS6281745A (ja) 1987-04-15
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EP0222144A1 (de) 1987-05-20
US4907062A (en) 1990-03-06

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