DE3568911D1 - A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters - Google Patents

A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters

Info

Publication number
DE3568911D1
DE3568911D1 DE8585105039T DE3568911T DE3568911D1 DE 3568911 D1 DE3568911 D1 DE 3568911D1 DE 8585105039 T DE8585105039 T DE 8585105039T DE 3568911 T DE3568911 T DE 3568911T DE 3568911 D1 DE3568911 D1 DE 3568911D1
Authority
DE
Germany
Prior art keywords
matrix
pair
cmos inverters
memory device
memory cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585105039T
Other languages
English (en)
Inventor
Fujio C O Patent Divis Masuoka
Kiyofumi C O Patent Divi Ochii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59085618A external-priority patent/JPH0648723B2/ja
Priority claimed from JP59085617A external-priority patent/JPH0648722B2/ja
Priority claimed from JP59253027A external-priority patent/JPS61131547A/ja
Priority claimed from JP59253026A external-priority patent/JPS61131558A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3568911D1 publication Critical patent/DE3568911D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
DE8585105039T 1984-04-27 1985-04-25 A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters Expired DE3568911D1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP59085618A JPH0648723B2 (ja) 1984-04-27 1984-04-27 半導体記憶装置
JP59085617A JPH0648722B2 (ja) 1984-04-27 1984-04-27 半導体記憶装置
JP59253027A JPS61131547A (ja) 1984-11-30 1984-11-30 半導体装置
JP59253026A JPS61131558A (ja) 1984-11-30 1984-11-30 半導体装置

Publications (1)

Publication Number Publication Date
DE3568911D1 true DE3568911D1 (en) 1989-04-20

Family

ID=27467140

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585105039T Expired DE3568911D1 (en) 1984-04-27 1985-04-25 A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of cmos inverters

Country Status (4)

Country Link
US (1) US4710897A (de)
EP (1) EP0163132B1 (de)
KR (1) KR890004458B1 (de)
DE (1) DE3568911D1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
JPS62169472A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 半導体集積回路装置
KR890002812B1 (ko) * 1986-11-28 1989-07-31 삼성전자 주식회사 씨모오스 디램에서 레이아웃이 최적화된 감지증폭기
JPS63152148A (ja) * 1986-12-16 1988-06-24 Sharp Corp 半導体素子
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト ３次元１トランジスタメモリセル構造とその製法
US4835458A (en) * 1987-11-09 1989-05-30 Intel Corporation Signature analysis technique for defect characterization of CMOS static RAM cell failures
JPH01186655A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体集積回路
US4918510A (en) * 1988-10-31 1990-04-17 Motorola, Inc. Compact CMOS device structure
US5227649A (en) * 1989-02-27 1993-07-13 Texas Instruments Incorporated Circuit layout and method for VLSI circuits having local interconnects
US5194752A (en) * 1989-05-23 1993-03-16 Kabushiki Kaisha Toshiba Semiconductor memory device
EP0527194A4 (en) * 1990-05-02 1993-04-14 Quality Semiconductor, Inc. High density local interconnect in a semiconductor circuit using metal silicide
US5254874A (en) * 1990-05-02 1993-10-19 Quality Semiconductor Inc. High density local interconnect in a semiconductor circuit using metal silicide
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH0541378A (ja) * 1991-03-15 1993-02-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5298782A (en) * 1991-06-03 1994-03-29 Sgs-Thomson Microelectronics, Inc. Stacked CMOS SRAM cell with polysilicon transistor load
US5416034A (en) * 1993-06-30 1995-05-16 Sgs-Thomson Microelectronics, Inc. Method of making resistor with silicon-rich silicide contacts for an integrated circuit
US5654915A (en) * 1993-08-19 1997-08-05 Cypress Semiconductor Corp. 6-bulk transistor static memory cell using split wordline architecture
JP3807836B2 (ja) 1997-11-28 2006-08-09 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
JPH11185476A (ja) * 1997-12-18 1999-07-09 Toshiba Corp 半導体記憶装置
KR100290903B1 (ko) * 1998-02-25 2001-06-01 김영환 반도체소자 및 이의 제조방법
JP3985735B2 (ja) * 2003-06-11 2007-10-03 セイコーエプソン株式会社 半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472691A (en) * 1977-11-21 1979-06-11 Toshiba Corp Semiconductor device
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
JPS5598852A (en) * 1979-01-23 1980-07-28 Nec Corp Memory device
CA1142261A (en) * 1979-06-29 1983-03-01 Siegfried K. Wiedmann Interconnection of opposite conductivity type semiconductor regions
WO1981002222A1 (en) * 1980-01-21 1981-08-06 Mostek Corp Composit gate interconnect structure
JPS6046547B2 (ja) * 1980-07-16 1985-10-16 株式会社東芝 相補型ｍｏｓ半導体装置
JPS57152161A (en) * 1981-03-16 1982-09-20 Seiko Epson Corp Manufacture of semiconductor device
US4613886A (en) * 1981-07-09 1986-09-23 Intel Corporation CMOS static memory cell
JPS594067A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
EP0163132A1 (de) 1985-12-04
EP0163132B1 (de) 1989-03-15
US4710897A (en) 1987-12-01
KR890004458B1 (ko) 1989-11-04
KR850007718A (ko) 1985-12-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)