DE3485564D1 - Redundante schaltung fuer ein halbleiterspeichergeraet. - Google Patents

Redundante schaltung fuer ein halbleiterspeichergeraet.

Info

Publication number
DE3485564D1
DE3485564D1 DE8484113439T DE3485564T DE3485564D1 DE 3485564 D1 DE3485564 D1 DE 3485564D1 DE 8484113439 T DE8484113439 T DE 8484113439T DE 3485564 T DE3485564 T DE 3485564T DE 3485564 D1 DE3485564 D1 DE 3485564D1
Authority
DE
Germany
Prior art keywords
memory
spare
row
main
memory cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484113439T
Other languages
English (en)
Inventor
Makoto C O Patent Divis Segawa
Shoji C O Patent Divi Ariizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3485564D1 publication Critical patent/DE3485564D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE8484113439T 1983-11-09 1984-11-07 Redundante schaltung fuer ein halbleiterspeichergeraet. Expired - Lifetime DE3485564D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58210091A JPH0666120B2 (ja) 1983-11-09 1983-11-09 半導体記憶装置の冗長部

Publications (1)

Publication Number Publication Date
DE3485564D1 true DE3485564D1 (de) 1992-04-16

Family

ID=16583666

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484113439T Expired - Lifetime DE3485564D1 (de) 1983-11-09 1984-11-07 Redundante schaltung fuer ein halbleiterspeichergeraet.

Country Status (4)

Country Link
US (1) US4648075A (de)
EP (1) EP0142127B1 (de)
JP (1) JPH0666120B2 (de)
DE (1) DE3485564D1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751656A (en) * 1986-03-10 1988-06-14 International Business Machines Corporation Method for choosing replacement lines in a two dimensionally redundant array
JPS62293598A (ja) * 1986-06-12 1987-12-21 Toshiba Corp 半導体記憶装置
US4689494A (en) * 1986-09-18 1987-08-25 Advanced Micro Devices, Inc. Redundancy enable/disable circuit
US4837747A (en) * 1986-11-29 1989-06-06 Mitsubishi Denki Kabushiki Kaisha Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block
JPS63220500A (ja) * 1987-03-09 1988-09-13 Mitsubishi Electric Corp 半導体記憶装置の冗長回路
JP2590897B2 (ja) * 1987-07-20 1997-03-12 日本電気株式会社 半導体メモリ
JPS6433800A (en) * 1987-07-29 1989-02-03 Toshiba Corp Semiconductor memory
DE68928112T2 (de) * 1988-03-18 1997-11-20 Toshiba Kawasaki Kk Masken-rom mit Ersatzspeicherzellen
US5426607A (en) * 1988-04-27 1995-06-20 Sharp Kabushiki Kaisha Redundant circuit for memory having redundant block operatively connected to special one of normal blocks
US5265055A (en) * 1988-10-07 1993-11-23 Hitachi, Ltd. Semiconductor memory having redundancy circuit
US5617365A (en) * 1988-10-07 1997-04-01 Hitachi, Ltd. Semiconductor device having redundancy circuit
US5289417A (en) * 1989-05-09 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with redundancy circuit
JP2547633B2 (ja) * 1989-05-09 1996-10-23 三菱電機株式会社 半導体記憶装置
JPH07105159B2 (ja) * 1989-11-16 1995-11-13 株式会社東芝 半導体記憶装置の冗長回路
KR920010347B1 (ko) * 1989-12-30 1992-11-27 삼성전자주식회사 분할된 워드라인을 가지는 메모리장치의 리던던시 구조
JP2575919B2 (ja) * 1990-03-22 1997-01-29 株式会社東芝 半導体記憶装置の冗長回路
US5199033A (en) * 1990-05-10 1993-03-30 Quantum Corporation Solid state memory array using address block bit substitution to compensate for non-functional storage cells
US5212693A (en) * 1990-08-02 1993-05-18 Ibm Corporation Small programmable array to the on-chip control store for microcode correction
JPH04184798A (ja) * 1990-11-19 1992-07-01 Sanyo Electric Co Ltd カラム冗長回路
JP2796590B2 (ja) * 1991-08-07 1998-09-10 三菱電機株式会社 メモリ装置及びそれを使用したデータ処理装置
US5471479A (en) * 1992-08-06 1995-11-28 Motorola, Inc. Arrangement for column sparing of memory
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
US6408401B1 (en) * 1998-11-13 2002-06-18 Compaq Information Technologies Group, L.P. Embedded RAM with self-test and self-repair with spare rows and columns
JP2001044366A (ja) * 1999-07-26 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6496427B2 (en) * 2000-08-28 2002-12-17 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device
US7111193B1 (en) * 2002-07-30 2006-09-19 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor memory having re-configurable fuse set for redundancy repair
US10658067B2 (en) 2018-05-14 2020-05-19 Micron Technology, Inc. Managing data disturbance in a memory with asymmetric disturbance effects

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047163A (en) * 1975-07-03 1977-09-06 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4393474A (en) * 1979-10-26 1983-07-12 Texas Instruments Incorporated EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
JPS5841500A (ja) * 1981-08-24 1983-03-10 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン 欠陥分離用デコ−ダ
JPS5868296A (ja) * 1981-10-16 1983-04-23 Nec Corp 記憶装置
JPS58130495A (ja) * 1982-01-29 1983-08-03 Toshiba Corp 半導体記憶装置
US4459685A (en) * 1982-03-03 1984-07-10 Inmos Corporation Redundancy system for high speed, wide-word semiconductor memories
JPS5975497A (ja) * 1982-10-22 1984-04-28 Hitachi Ltd 半導体記憶装置
JPH0670880B2 (ja) * 1983-01-21 1994-09-07 株式会社日立マイコンシステム 半導体記憶装置

Also Published As

Publication number Publication date
US4648075A (en) 1987-03-03
EP0142127A3 (en) 1988-03-16
JPS60103469A (ja) 1985-06-07
EP0142127B1 (de) 1992-03-11
JPH0666120B2 (ja) 1994-08-24
EP0142127A2 (de) 1985-05-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)