DE3484636D1 - Speicherkorrektursystem unter verwendung von reservematrizen. - Google Patents

Speicherkorrektursystem unter verwendung von reservematrizen.

Info

Publication number
DE3484636D1
DE3484636D1 DE8484108714T DE3484636T DE3484636D1 DE 3484636 D1 DE3484636 D1 DE 3484636D1 DE 8484108714 T DE8484108714 T DE 8484108714T DE 3484636 T DE3484636 T DE 3484636T DE 3484636 D1 DE3484636 D1 DE 3484636D1
Authority
DE
Germany
Prior art keywords
matrices
reserve
correction system
memory correction
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484108714T
Other languages
English (en)
Inventor
Shanker Singh
Vijendra P Singh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3484636D1 publication Critical patent/DE3484636D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE8484108714T 1983-09-02 1984-07-24 Speicherkorrektursystem unter verwendung von reservematrizen. Expired - Fee Related DE3484636D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/528,769 US4584681A (en) 1983-09-02 1983-09-02 Memory correction scheme using spare arrays

Publications (1)

Publication Number Publication Date
DE3484636D1 true DE3484636D1 (de) 1991-07-04

Family

ID=24107112

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484108714T Expired - Fee Related DE3484636D1 (de) 1983-09-02 1984-07-24 Speicherkorrektursystem unter verwendung von reservematrizen.

Country Status (4)

Country Link
US (1) US4584681A (de)
EP (1) EP0136443B1 (de)
JP (1) JPS6072048A (de)
DE (1) DE3484636D1 (de)

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US6295591B1 (en) * 1999-03-30 2001-09-25 International Business Machines Corporation Method of upgrading and/or servicing memory without interrupting the operation of the system
US6370668B1 (en) * 1999-07-23 2002-04-09 Rambus Inc High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
US6708248B1 (en) * 1999-07-23 2004-03-16 Rambus Inc. Memory system with channel multiplexing of multiple memory devices
US20020196687A1 (en) * 2001-06-08 2002-12-26 Sauvageau Anthony J. Methods and apparatus for analyzing and repairing memory
US6941493B2 (en) * 2002-02-27 2005-09-06 Sun Microsystems, Inc. Memory subsystem including an error detection mechanism for address and control signals
US20030163769A1 (en) * 2002-02-27 2003-08-28 Sun Microsystems, Inc. Memory module including an error detection mechanism for address and control signals
US6996766B2 (en) * 2002-06-28 2006-02-07 Sun Microsystems, Inc. Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6973613B2 (en) * 2002-06-28 2005-12-06 Sun Microsystems, Inc. Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
US6976194B2 (en) * 2002-06-28 2005-12-13 Sun Microsystems, Inc. Memory/Transmission medium failure handling controller and method
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
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US7360132B1 (en) * 2005-05-19 2008-04-15 Sun Microsystems, Inc. System and method for memory chip kill
US20080077840A1 (en) * 2006-09-27 2008-03-27 Mark Shaw Memory system and method for storing and correcting data
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US8473791B2 (en) * 2007-04-30 2013-06-25 Hewlett-Packard Development Company, L.P. Redundant memory to mask DRAM failures
JP2008217811A (ja) * 2008-04-03 2008-09-18 Hitachi Ltd 不揮発メモリを使用したディスク制御装置
US8555141B2 (en) * 2009-06-04 2013-10-08 Lsi Corporation Flash memory organization
US8560924B2 (en) * 2010-01-05 2013-10-15 International Business Machines Corporation Register file soft error recovery
US9043661B2 (en) 2012-05-30 2015-05-26 Micron Technology, Inc. Memories and methods for performing column repair
US9459956B2 (en) 2013-07-19 2016-10-04 Seagate Technology Llc Data decoder with trapping set flip bit mapper
US9317361B2 (en) 2013-11-27 2016-04-19 Seagate Technology Llc Bit-line defect detection using unsatisfied parity code checks
US9891864B2 (en) 2016-01-19 2018-02-13 Micron Technology, Inc. Non-volatile memory module architecture to support memory error correction
US10120749B2 (en) 2016-09-30 2018-11-06 Intel Corporation Extended application of error checking and correction code in memory
JP6841698B2 (ja) * 2017-03-21 2021-03-10 ルネサスエレクトロニクス株式会社 半導体装置
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US10990472B2 (en) * 2018-07-24 2021-04-27 Micron Technology, Inc. Spare substitution in memory system
KR20210147131A (ko) 2020-05-27 2021-12-07 삼성전자주식회사 반도체 메모리 모듈을 액세스하는 방법
KR20220060156A (ko) 2020-11-04 2022-05-11 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법

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Also Published As

Publication number Publication date
EP0136443B1 (de) 1991-05-29
EP0136443A2 (de) 1985-04-10
JPS6072048A (ja) 1985-04-24
EP0136443A3 (en) 1987-09-02
US4584681A (en) 1986-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee