DE3374822D1 - Anisotropic silicide etching process - Google Patents

Anisotropic silicide etching process

Info

Publication number
DE3374822D1
DE3374822D1 DE8484900081T DE3374822T DE3374822D1 DE 3374822 D1 DE3374822 D1 DE 3374822D1 DE 8484900081 T DE8484900081 T DE 8484900081T DE 3374822 T DE3374822 T DE 3374822T DE 3374822 D1 DE3374822 D1 DE 3374822D1
Authority
DE
Germany
Prior art keywords
anisotropic
etching process
silicide etching
silicide
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484900081T
Other languages
English (en)
Inventor
Ronald Bourassa
Michael Reeder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inmos Corp
Original Assignee
Inmos Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Corp filed Critical Inmos Corp
Application granted granted Critical
Publication of DE3374822D1 publication Critical patent/DE3374822D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
DE8484900081T 1982-12-03 1983-12-01 Anisotropic silicide etching process Expired DE3374822D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/446,597 US4414057A (en) 1982-12-03 1982-12-03 Anisotropic silicide etching process
PCT/GB1983/000314 WO1984002228A1 (en) 1982-12-03 1983-12-01 Anisotropic silicide etching process

Publications (1)

Publication Number Publication Date
DE3374822D1 true DE3374822D1 (en) 1988-01-14

Family

ID=23773183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484900081T Expired DE3374822D1 (en) 1982-12-03 1983-12-01 Anisotropic silicide etching process

Country Status (5)

Country Link
US (1) US4414057A (de)
EP (1) EP0126758B1 (de)
JP (1) JPS59502164A (de)
DE (1) DE3374822D1 (de)
WO (1) WO1984002228A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472237A (en) * 1981-05-22 1984-09-18 At&T Bell Laboratories Reactive ion etching of tantalum and silicon
DE3216823A1 (de) * 1982-05-05 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen
US4470189A (en) * 1983-05-23 1984-09-11 International Business Machines Corporation Process for making polycide structures
JPS61136229A (ja) * 1984-12-06 1986-06-24 Toshiba Corp ドライエツチング装置
US5087591A (en) * 1985-01-22 1992-02-11 Texas Instruments Incorporated Contact etch process
US4680086A (en) * 1986-03-20 1987-07-14 Motorola, Inc. Dry etching of multi-layer structures
US4808259A (en) * 1988-01-25 1989-02-28 Intel Corporation Plasma etching process for MOS circuit pregate etching utiliizing a multi-step power reduction recipe
US5201993A (en) * 1989-07-20 1993-04-13 Micron Technology, Inc. Anisotropic etch method
US5271799A (en) * 1989-07-20 1993-12-21 Micron Technology, Inc. Anisotropic etch method
US5094712A (en) * 1990-10-09 1992-03-10 Micron Technology, Inc. One chamber in-situ etch process for oxide and conductive material
US5221414A (en) * 1991-07-16 1993-06-22 Micron Technology, Inc. Process and system for stabilizing layer deposition and etch rates while simultaneously maintaining cleanliness in a water processing reaction chamber
US5378648A (en) * 1992-07-15 1995-01-03 Micron Technology, Inc. Situ stringer removal during polysilicon capacitor cell plate delineation
US5605603A (en) * 1995-03-29 1997-02-25 International Business Machines Corporation Deep trench process
US5856239A (en) * 1997-05-02 1999-01-05 National Semiconductor Corporaton Tungsten silicide/ tungsten polycide anisotropic dry etch process
US5902133A (en) * 1997-08-13 1999-05-11 Vanguard International Semiconductor Corporation Method of forming a narrow polysilicon gate with i-line lithography
US6605541B1 (en) * 1998-05-07 2003-08-12 Advanced Micro Devices, Inc. Pitch reduction using a set of offset masks
JP3776856B2 (ja) * 2002-09-13 2006-05-17 株式会社日立ハイテクノロジーズ プラズマ処理装置およびプラズマ処理方法
CN112930591A (zh) 2018-09-18 2021-06-08 应用材料公司 原位集成型腔室

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1417085A (en) * 1973-05-17 1975-12-10 Standard Telephones Cables Ltd Plasma etching
US4211601A (en) * 1978-07-31 1980-07-08 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4208241A (en) * 1978-07-31 1980-06-17 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4226665A (en) * 1978-07-31 1980-10-07 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
US4332839A (en) * 1978-12-29 1982-06-01 Bell Telephone Laboratories, Incorporated Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
JPS56277A (en) * 1979-06-12 1981-01-06 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of metal layer pattern
JPS5690525A (en) * 1979-11-28 1981-07-22 Fujitsu Ltd Manufacture of semiconductor device
JPS56100421A (en) * 1980-01-17 1981-08-12 Toshiba Corp Plasma etching method
JPS56144541A (en) * 1980-04-11 1981-11-10 Fujitsu Ltd Etching method
US4362597A (en) * 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
CA1202597A (en) * 1981-05-22 1986-04-01 Jean S. Deslauriers Reactive ion layers containing tantalum and silicon

Also Published As

Publication number Publication date
WO1984002228A1 (en) 1984-06-07
US4414057A (en) 1983-11-08
EP0126758B1 (de) 1987-12-02
EP0126758A1 (de) 1984-12-05
JPS59502164A (ja) 1984-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition