DE3279113D1 - Page controlled cache directory addressing - Google Patents

Page controlled cache directory addressing

Info

Publication number
DE3279113D1
DE3279113D1 DE8282109612T DE3279113T DE3279113D1 DE 3279113 D1 DE3279113 D1 DE 3279113D1 DE 8282109612 T DE8282109612 T DE 8282109612T DE 3279113 T DE3279113 T DE 3279113T DE 3279113 D1 DE3279113 D1 DE 3279113D1
Authority
DE
Germany
Prior art keywords
cache directory
controlled cache
page controlled
directory addressing
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282109612T
Other languages
English (en)
Inventor
Robert Percy Fletcher
Daniel Bond Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3279113D1 publication Critical patent/DE3279113D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
DE8282109612T 1981-11-23 1982-10-18 Page controlled cache directory addressing Expired DE3279113D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/324,165 US4441155A (en) 1981-11-23 1981-11-23 Page controlled cache directory addressing

Publications (1)

Publication Number Publication Date
DE3279113D1 true DE3279113D1 (en) 1988-11-17

Family

ID=23262380

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282109612T Expired DE3279113D1 (en) 1981-11-23 1982-10-18 Page controlled cache directory addressing

Country Status (4)

Country Link
US (1) US4441155A (de)
EP (1) EP0080062B1 (de)
JP (1) JPS5891573A (de)
DE (1) DE3279113D1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612612A (en) * 1983-08-30 1986-09-16 Amdahl Corporation Virtually addressed cache
US4631660A (en) * 1983-08-30 1986-12-23 Amdahl Corporation Addressing system for an associative cache memory
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
AU5768886A (en) * 1985-05-24 1986-11-27 G.D. Searle & Co. 2-((1-h-benzimidazol-2-ylsulfinyl)methyl)benzenamines
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
JPS6286407A (ja) * 1985-10-11 1987-04-20 Omron Tateisi Electronics Co プログラマブル・コントロ−ラ
US5119290A (en) * 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US5133061A (en) * 1987-10-29 1992-07-21 International Business Machines Corporation Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses
US5210843A (en) * 1988-03-25 1993-05-11 Northern Telecom Limited Pseudo set-associative memory caching arrangement
US5077826A (en) * 1989-08-09 1991-12-31 International Business Machines Corporation Cache performance in an information handling system employing page searching
US5148538A (en) * 1989-10-20 1992-09-15 International Business Machines Corporation Translation look ahead based cache access
AU8870291A (en) * 1990-10-12 1992-05-20 Intel Corporation Cache controller and associated method for remapping cache address bits
US5493668A (en) * 1990-12-14 1996-02-20 International Business Machines Corporation Multiple processor system having software for selecting shared cache entries of an associated castout class for transfer to a DASD with one I/O operation
IT1254937B (it) * 1991-05-06 1995-10-11 Aggiornamento dinamico di memoria non volatile in un sistema informatico
DE4215063C2 (de) * 1991-05-10 1999-11-25 Intel Corp Einrichtung und Verfahren zum Seitenwechsel bei einem nicht-flüchtigen Speicher
FR2688612A1 (fr) * 1992-03-13 1993-09-17 Inst Nat Rech Inf Automat Dispositif d'antememoire.
JP3169155B2 (ja) * 1993-12-22 2001-05-21 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 情報をキャッシュするための回路
EP0826181A4 (de) * 1995-04-11 2005-02-09 Kinetech Inc Identifizierung von daten in einem datenverarbeitungssystem
US5822581A (en) * 1995-09-29 1998-10-13 Intel Corporation Method for CMOS configuration information storage and retrieval in flash
US5930504A (en) * 1996-07-22 1999-07-27 Intel Corporation Dynamic nonvolatile memory update in a computer system
US5838893A (en) * 1996-12-26 1998-11-17 Microsoft Corporation Method and system for remapping physical memory
US6145057A (en) * 1997-04-14 2000-11-07 International Business Machines Corporation Precise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests
US6049849A (en) * 1997-04-14 2000-04-11 International Business Machines Corporation Imprecise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests
US6014709A (en) * 1997-11-05 2000-01-11 Unisys Corporation Message flow protocol for avoiding deadlocks
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
US6212616B1 (en) * 1998-03-23 2001-04-03 International Business Machines Corporation Even/odd cache directory mechanism
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6665761B1 (en) 1999-07-28 2003-12-16 Unisys Corporation Method and apparatus for routing interrupts in a clustered multiprocessor system
US6687818B1 (en) 1999-07-28 2004-02-03 Unisys Corporation Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system
US6425058B1 (en) * 1999-09-07 2002-07-23 International Business Machines Corporation Cache management mechanism to enable information-type dependent cache policies
US6421761B1 (en) 1999-11-09 2002-07-16 International Business Machines Corporation Partitioned cache and management method for selectively caching data by type
WO2006059384A1 (ja) * 2004-12-02 2006-06-08 Fujitsu Limited データバッファ装置、キャッシュ装置、データバッファ制御方法
US8185576B2 (en) * 2006-03-14 2012-05-22 Altnet, Inc. Filter for a distributed network
TWI301270B (en) * 2006-06-30 2008-09-21 Winbond Electronics Corp Semiconductor memory and circuit and method of decoding address for the same
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US3840863A (en) * 1973-10-23 1974-10-08 Ibm Dynamic storage hierarchy system
US4228503A (en) * 1978-10-02 1980-10-14 Sperry Corporation Multiplexed directory for dedicated cache memory system
US4215402A (en) * 1978-10-23 1980-07-29 International Business Machines Corporation Hash index table hash generator apparatus
US4314331A (en) * 1978-12-11 1982-02-02 Honeywell Information Systems Inc. Cache unit information replacement apparatus
US4363095A (en) * 1980-12-31 1982-12-07 Honeywell Information Systems Inc. Hit/miss logic for a cache memory

Also Published As

Publication number Publication date
JPH0324699B2 (de) 1991-04-03
EP0080062B1 (de) 1988-10-12
JPS5891573A (ja) 1983-05-31
US4441155A (en) 1984-04-03
EP0080062A3 (en) 1986-06-11
EP0080062A2 (de) 1983-06-01

Similar Documents

Publication Publication Date Title
DE3279113D1 (en) Page controlled cache directory addressing
DE3176266D1 (en) Cache addressing mechanism
GB8712513D0 (en) Cache directory & control
GB2068155B (en) Cache memory system
AU554363B2 (en) Cache memory
EP0144121A3 (en) Virtually addressed cache
DE3278863D1 (en) Hybrid cache control
GB2037041B (en) Cache unit
AU7913981A (en) Cache memory
JPS57141088A (en) Memory addressing system
JPS5587367A (en) Cache memory
DE3277709D1 (en) Memory addressing system
JPS5587368A (en) Cache unit
AU578420B2 (en) Cache memory
GB2065941B (en) Cache store system
DE3278375D1 (en) Page addressing mechanism and method for using the same
AU544005B2 (en) Cache buffer-pageing
JPS57157513A (en) Capacitor
GB2097365B (en) Page turner
GB2037039B (en) Cache memory system
AU551086B2 (en) Telescopic cylinders
GB2108419B (en) Rod driver
GB2094228B (en) Bookmark
JPS57148335A (en) Capacitor
JPS56116075A (en) Page memory composition

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee