DE2964292D1 - Large scale integrated circuit wafer and method of testing same - Google Patents

Large scale integrated circuit wafer and method of testing same

Info

Publication number
DE2964292D1
DE2964292D1 DE7979103612T DE2964292T DE2964292D1 DE 2964292 D1 DE2964292 D1 DE 2964292D1 DE 7979103612 T DE7979103612 T DE 7979103612T DE 2964292 T DE2964292 T DE 2964292T DE 2964292 D1 DE2964292 D1 DE 2964292D1
Authority
DE
Germany
Prior art keywords
chip
chips
wafer
incorporation
large scale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979103612T
Other languages
English (en)
Inventor
Frank Fang Tsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2964292D1 publication Critical patent/DE2964292D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
DE7979103612T 1978-12-29 1979-09-24 Large scale integrated circuit wafer and method of testing same Expired DE2964292D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/974,641 US4244048A (en) 1978-12-29 1978-12-29 Chip and wafer configuration and testing method for large-scale-integrated circuits

Publications (1)

Publication Number Publication Date
DE2964292D1 true DE2964292D1 (en) 1983-01-20

Family

ID=25522298

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979103612T Expired DE2964292D1 (en) 1978-12-29 1979-09-24 Large scale integrated circuit wafer and method of testing same

Country Status (4)

Country Link
US (1) US4244048A (de)
EP (1) EP0013290B1 (de)
JP (1) JPS5937578B2 (de)
DE (1) DE2964292D1 (de)

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DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
AU8963582A (en) * 1981-10-30 1983-05-05 Honeywell Information Systems Incorp. Design and testing electronic components
US4808915A (en) * 1981-10-30 1989-02-28 Honeywell Bull, Inc. Assembly of electronic components testable by a reciprocal quiescent testing technique
US4465968A (en) * 1981-11-13 1984-08-14 At&T Technologies, Inc. Method and apparatus for testing open collector electrical circuit devices
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4476560A (en) * 1982-09-21 1984-10-09 Advanced Micro Devices, Inc. Diagnostic circuit for digital systems
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US4581738A (en) * 1983-10-06 1986-04-08 Honeywell Information Systems Inc. Test and maintenance method and apparatus for a data processing system
US4680539A (en) * 1983-12-30 1987-07-14 International Business Machines Corp. General linear shift register
DE3578224D1 (de) * 1984-07-27 1990-07-19 Fujitsu Ltd Integrierte schaltung vom chip-auf-chip-typ.
US4638246A (en) * 1984-09-21 1987-01-20 Gte Laboratories Incorporated Integrated circuit input-output diagnostic system
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
US4635261A (en) * 1985-06-26 1987-01-06 Motorola, Inc. On chip test system for configurable gate arrays
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
EP0228156A3 (de) * 1985-11-07 1989-06-07 Control Data Corporation Prüfsystem für VLSI-Schaltungen
US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
US4680761A (en) * 1986-01-30 1987-07-14 Burkness Donald C Self diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI
US4725773A (en) * 1986-06-27 1988-02-16 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Cross-contact chain
KR900002770B1 (ko) * 1986-08-04 1990-04-30 미쓰비시 뎅끼 가부시끼가이샤 반도체 집적회로장치
KR910002236B1 (ko) * 1986-08-04 1991-04-08 미쓰비시 뎅기 가부시끼가이샤 반도체집적회로장치
US4853929A (en) * 1987-03-06 1989-08-01 Fujitsu Limited Electronic circuit device able to diagnose status-holding circuits by scanning
US4876501A (en) * 1987-04-13 1989-10-24 Prime Computer, Inc. Method and apparatus for high accuracy measurment of VLSI components
US6349392B1 (en) * 1987-06-02 2002-02-19 Texas Instruments Incorporated Devices, systems and methods for mode driven stops
US6539497B2 (en) * 1987-06-02 2003-03-25 Texas Instruments Incorporated IC with selectively applied functional and test clocks
US4996691A (en) * 1988-09-21 1991-02-26 Northern Telecom Limited Integrated circuit testing method and apparatus and integrated circuit devices for use therewith
JPH0394183A (ja) * 1989-05-19 1991-04-18 Fujitsu Ltd 半導体集積回路の試験方法及び回路
US5047711A (en) * 1989-08-23 1991-09-10 Silicon Connections Corporation Wafer-level burn-in testing of integrated circuits
US5648730A (en) * 1994-11-30 1997-07-15 Texas Instruments Incorporated Large integrated circuit with modular probe structures
US5606710A (en) * 1994-12-20 1997-02-25 National Semiconductor Corporation Multiple chip package processor having feed through paths on one die
US5600257A (en) * 1995-08-09 1997-02-04 International Business Machines Corporation Semiconductor wafer test and burn-in
US6611941B1 (en) * 1999-10-06 2003-08-26 Inventec Corporation Method for RAMDAC testing
US6624651B1 (en) 2000-10-06 2003-09-23 International Business Machines Corporation Kerf circuit for modeling of BEOL capacitances
KR100505686B1 (ko) * 2003-05-26 2005-08-03 삼성전자주식회사 다수의 피시험 소자들을 병렬로 검사하는 테스트 시스템및 테스트 방법
EP2030030B1 (de) * 2006-05-29 2010-11-03 Freescale Semiconductor, Inc. Einrichtung und verfahren zum prüfen integrierter schaltungen
CN110021334B (zh) * 2019-04-19 2021-08-27 上海华虹宏力半导体制造有限公司 一种晶圆测试方法

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US3742254A (en) * 1971-01-27 1973-06-26 Texas Instruments Inc Automatic mos grounding circuit
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3784907A (en) * 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US3879839A (en) * 1973-06-04 1975-04-29 Ibm Method of manufacturing multi-function LSI wafers
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
US4071902A (en) * 1976-06-30 1978-01-31 International Business Machines Corporation Reduced overhead for clock testing in a level system scan design (LSSD) system
US4051352A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Level sensitive embedded array logic system
US4139818A (en) * 1977-09-30 1979-02-13 Burroughs Corporation Circuit means for collecting operational errors in IC chips and for identifying and storing the locations thereof

Also Published As

Publication number Publication date
US4244048A (en) 1981-01-06
JPS5937578B2 (ja) 1984-09-11
JPS5591137A (en) 1980-07-10
EP0013290B1 (de) 1982-12-15
EP0013290A1 (de) 1980-07-23

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Publication Publication Date Title
DE2964292D1 (en) Large scale integrated circuit wafer and method of testing same
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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee