DE2948120A1 - IGFET with minimum capacitance - has pyramid island structure with insulated gate structure along apex using silicon deposit on sapphire or spinel - Google Patents

Abstract

The insulated gate FET is formed using SOS techniques (Silicon on Sapphire or Spinel), for epitaxial layering so that attention can be directed to overlap, and consequently junction capacitance, reduction. The first semiconductor elements (33, 34) for the source zone (34) and drain (33) are formed parallel to the substrate (36) and with a channel zone (35) between them. The source (34) and drain (33) sections have three parts each (33, 33", 33'", 34', 34'") formed down the sides of the channel zone (35) and onto a foot parallel with the substrate (36). The insulated gate section (32) is mounted along the top of the channel (35) and over the first sections (33', 34') of the source and drain, with gate electrode (31). In one example of gate construction, the overlap capacities are of the order of 0.003pF with channel widths of 4 mu m.

Description

B e s c h r e i b u ii g

The invention relates to an insulating layer field effect transistor (IG FET) with an island-shaped semiconductor layer on the surface of an insulating Substrate, a source and a drain zone in the semiconductor layer, a channel zone between the source and drain zone, a gate insulating layer on the channel zone and a gate electrode on this insulating layer and a method for its production, specifically an IG FET with a silicon single crystal resting on a sapphire or spinel substrate (Silicon on Sapphire or Spinel: hereinafter abbreviated as SOS) epitaxially grown and a process for its manufacture.

Lately the performance of IG FET's has increased Using the technique of micro-fining and others quickly developed. Particularly for circuit integration it has become an important technique the capacitance of wiring levels, each of which has transistors or the like with one another connect by arranging a plurality of transistors in isolation from each other on an insulating substrate of high resistance. On the other On the other hand, the capacitance of the transistors must be reduced. To this end generally became a method of forming the source and drain regions into one proposed with respect to the gate self-centering process. But also with this one so-called 'self-centering VedShren (self-aligning process), in which a gate electrode made of polycrystalline silicon as a mask for forming the source and drain zones is used, the overlap between the gate electrode and the source or drain zones due to lateral diffusion approximately equal to the thickness of the silicon layer when the source and drain regions are formed so deep that s # to reach to the interface between sapphire and silicon. The ones from this overlap caused capacity therefore becomes large; and the dynamic performance of the Transistor deteriorates. It is only necessary to have the silicon single crystal layer or to make the semiconductor layer thin to avoid such overlapping due to lateral Reduce diffusion. The crystal properties of a semiconductor layer depend but strong from its thickness as long as this thickness is not too strong and, in general, reducing the thickness below a certain flow becomes one Deterioration in crystal properties and consequently in the performance of the Trara tor built using such a semiconductor layer. For example, according to today's technology, one must be grown on a sapphire substrate Silicon crystal must be at least 2000 µm thick and silicon layers are generally used used with a thickness of 5000 i to 10,000 i. In addition, in the case of on Semi-insulating GaAs substrate, grown GaAs layers reduce the thickness Limited with regard to zones with variable concentration of impurities, traps on the boundary layer, uniformity of the thickness of an epitaxial layer, reproducibility etc.

If on the other hand the source and drain regions are so formed that they are to avoid the overlap between the gate electrode and the source and drain zone do not reach down to the insulating substrate, then the Capacity of the pn junction between the lower part of these areas and the semiconductor layer enlarged.

Since lately the realization of a transistor with a Gate length of up to 5000 i in view of the need for high speed operations has become necessary, the above-mentioned increase in capacity must avoided will.

With regard to SOS FEIsBoll here e.g. to the articles in IEEE Transactions on Electron Devices, VdL ED-25, No. 8, August 1978, pp. 868 - 873, by Ditmar Kranzer et al, and pp. 873-878, by Ronald T. Jerdonek et al. to get expelled.

The invention is based on the object of an effective IG To provide FET which is designed to avoid the disadvantages mentioned above.

It also aims to be an effective method of manufacturing IG FETs be created by which ~ through the application of the present invention in an integrated circuit with a large number of transistors the integrated Circuit can be realized easily and with good yield.

According to the invention, the object is the one mentioned at the beginning with an IG FET Art solved in that the island-shaped semiconductor layer has a first surface parallel to the surface of the substrate, second surface on both sides of the first Surface parallel to the substrate surface, 'closer to the substrate surface lie than that has the first surface, and lateral surfaces / each having the connect the first surface to the second, the Drain or source zones from the second surfaces to the respective part of the substrate surface extend under these and on the side surfaces and the respective end of the first surface are shaped so that the pn junction is substantially parallel runs to the lateral surfaces, and the channel zone extends to the first surface is located.

In a more specific embodiment, source and drain regions contain of the IG FET each has a part that is located on the canal zone, a second part, which creates the connection to the wiring level, and a third part which this continuously connects both parts.

The surface of the first part is continuous from the surface of the Channel zone provided, i.e. the surface of the first part goes into that of the channel zone above. The surface of the second part, i.e. the surface that the connection to the wiring level is lower than the first part, i.e. on one level near the major surface of the insulating or semi-insulating substrate.

The surface of the third part is with the surfaces of the first and second parts connected and inclined to the main surface of the substrate and the surfaces of the first and second parts. On the canal zone and an insulating gate layer is provided on the surface of the first part and on this insulating gate Layer is at least above the canal zone the gate electrode attached.

As the semiconductor layer in terms of its crystal properties must have a thickness of 2000 i or more, the distance t1 should be from the main surface of the insulating substrate to the surface of the channel zone and the surface of the first Parts of the source and drain zones are preferably 2000 i or larger. Furthermore, if the distance between the major surface of the insulating substrate and the surface of the second part of the source and drain region is represented by t2, the effective range of the thickness ratio 3 :, t1 / t2 z 1.5. This relationship derived from the fact that with yourself to the present-day state of lithography for VLSI (very large is scale integration), the overlap will be about 1000 a should, and that if the thickness t2 is too small, the resistance to the channel region increases becomes large, while on the other hand, when the thickness becomes too large, the The effect of the capacity reduction of the overlap is not effective.

In addition, the invention is a method for producing a IG FET's, comprising the steps of: forming a silicon layer on the main surface of an insulating substrate, which is island-shaped and one Has {100} -plane as surface; Applying an insulating gate # iicht with larger Corrosion resistance than silicon, a gate electrode layer with a corrosion resistance, which is equal to or close to that of silicon, and an XtZ.masking which has a corrosion resistance equal to or greater than that of the gate insulating layer on the main surface of the silicon single crystal Has; Structuring of the etching mask, the gate electrode layer and the gate insulating layer in the same planar configuration so that the gate configuration is its interface along the (110) direction of the silicon layer; Etching with a selective Etchant whose etching speed is sufficient for the 100 # plane of silicon Dimensions is greater than its etch rate for a 100} plane of silicon, to form the silicon single crystal layer into a mesa structure that has a first Surface of a 100} plane that remains under the gate insulating layer, second Surface as a 100} plane that is on either side of the first surface and closer lying on the substrate surface as the first surface, and side surfaces as F11 p planes that connect the first and second surfaces to each other, and to make the gate electrode layer narrower than the remaining gate insulating layer; Introduction of impurities in order to form the source and drain zones so far that below of the second surface of the 000} plane, the imperfections are the underside of the silicon layer reached on the main surface of the insulating substrate and in the {111} Surface part -surface part of the mesa structure the bottom of the ends of the constricted Reach the gate electrode.

In the following the invention is illustrated by means of embodiments explained in more detail with reference to the figures.

Figs. 1 and 2 each show a cross section through an IG FET conventional type in SOS construction; Fig. 3A is a plan view of a first according to the invention Embodiment; Fig. B is a cross section taken along line B-Bt of Fig. 3A in Direction of arrows; Figures 4 to 7 are cross-sections showing a sequence of manufacturing steps show an IG FET according to the first embodiment of the present invention; Fig. 8 to 11 each have cross sections showing a second to fifth embodiment of the invention demonstrate.

Figs. 1 and 2 show IG FETs of conventional construction in which an island of a conductive type semiconductor layer on an insulating Substrate 16, 26 is formed is, with a source zone in this island 14, 24 and drain zone 13, 23 each of the other conductivity type in by a self-centering Method using a gate insulating layer 12, 22 and a gate electrode 11, 21 made of polycrystalline silicon are formed as noses. A canal zone 14, 25 of the one conduction type lies between the source zone and the drain zone.

In the conventional structure of Fig. 1, the depth of the transition is shallow chosen to increase the capacitance of the overlap between gate electrode 11 and source and to reduce drain zones 14 and 13. But as can be seen from Fig. 1, there are it becomes a zone of the one type of conduction below zones 13 and 14, and consequently the capacitance of the pn junction between zones 14 and 13 and the zone of the one Line type great.

On the other hand, in the conventional construction of Fig. 2 the zones 23 and 24 formed so deep that they reach the insulating substrate 26, and so is the capacitance of the pn junction between zones 24 and 23 and the zone 25 greatly reduced compared to the conventional type from FIG. 1, but in contrast 1, the gate overlap over the source or Drain enlarged.

First Preferred Embodiment Figs. 3A and 3B show a first one Embodiment according to the invention, in which a semiconductor layer 30 of a conductivity type formed in an island shape on the main surface of an insulating substrate 36 and this semiconductor layer 23 has a source zone 34 and a drain zone 33 each of the other conductivity type by using a gate insulating layer 33 as Mask are formed. As can be seen from these figures is compared to the Height t1 of the first parts 34 'and 33' of the source and drain zones, which are at the channel zone 35 lie, the thickness t2 of the second parts 34 "and 33" of these zones, which with the Wiring layers 38 and 39 are connected, thinner.

Therefore, despite the fact that these zones are the insulating substrate achieve the extent of the lateral diffusion so small that de overlap between Source and drain zones and the gate electrode 31 is reduced and in soauch the Capacity is reduced. In addition, this embodiment according to the invention, since the IG FET manufactured by a new manufacturing method as described later is, the gate electrode 31 is narrowed its lateral length P as seen in Fig. 3B compared to the insulating layer 32, and so the overlap capacitance becomes even smaller.

In the illustrated IG FET, the length t1 is the gate insulating layer 32 1.6 Hm, and since the gate electrode is 0.3 m laterally in the manufacturing process is etched away, the lateral length 2 of the gate electrode 31 is 1.0 pm Since the source and drain zones due to the side diffusion during their production 0.4 m below the Insulating layer are diffused, the respective overlap between the source or drain zone and the gate electrode 0.1 pm. Since the thickness t1 of the semiconductor layer 30 is 0.6 m, the overlap length of 0.1 Hm is a very small value.

The capacity of this IG FET was 0.003 picofarads in the case of one channel width W of 4 #m. On the other hand, in the case of the IG-FET of Fig. 2, where was the others Conditions including the length of the gate insulating layer were kept the same, the capacity 0.006 picofarads. Also in the case of the IG FET of Fig. 1, where the length from the end of the gate electrode to the end of the source and drain zone is 5 pm and the other conditions are kept the same, the capacity was 0.008 to 0.013 Pico-farad. Therefore, according to the invention, compared to conventional IG FETs high speed operation can be expected. Furthermore, regarding the Performance of a ring oscillator made of IG FETs in conventional design, in the case of a 31-stage oscillator, a delay time of 15.5 n seconds can be observed, while for a similar ring oscillator using the invention IG FET's manufactured the delay time was reduced to 8.7 n sec was, thus demonstrating the importance of the present invention.

Now the process for the production of the IG FETs according to the first embodiment of the invention will be described.

The SOS substrate, which in the first preferred embodiment is used is a sapphire single crystal wafer 36 approximately 400 Hm thick and has a 1102 plane on which silicon single crystal of 0.6 µm thick is grown with a tiOOj plane as the main surface, which is n-type and has a specific resistance of 100dz / cm or greater. The silicon single crystal is selectively etched to remain in the shape of an island 30 by the conventional process. Subsequent to this is a suitable mer impurity, in the illustrated embodiment Boron, introduced into the island-shaped silicon layer 30, so that the average The impurity concentration is approximately 3 x 1016 atoms / cm3, and there is also a silicon oxide layer 32 for use as a gate insulating film on the silicon layer 30 by thermal Oxidation produced with a thickness of 500 2. Then there is polycrystalline silicon over the entire surface of the plate in a thickness of about 4000 2 in one CVD process (chemical vapor deposition) deposited on a polycrystalline silicon layer 31, which is used as a gate electrode, the top of which area part is oxidized to a depth of about 100 i to form a silicon oxide layer to form (shown in Fig. 4 as the lower part of the undifferentiated view 44), a silicon nitride layer (in Fig. 4 as the middle part of the layer 44) is on the silicon oxide layer with a CVD process to a thickness of approximately 2000 i grown and further this silicon nitride layer is thermally oxidized to a Silicon oxide layer (in Fig. 4 the upper part of layer 44) of about 300 # Thickness on the surface of the layer 44 to form. This composite layer 44 serves as an etching mask. A schematic cross-section through that made in this way Semiconductor die is shown in FIG. Next is some structuring the polycrystalline silicon layer 31 by using the photo-etching base 45 as a mask according to the conventional lithography technique made, i.e. the layer 44 and the polycrystalline silicon layer 31 are etched away one after the other. here must be noted that one of the characteristics of the manufacturing process for IG FETs according to the invention is the structure of polycrystalline silicon so that they are parallel to the (110> direction of the single crystal silicon layer 30 lies. In the illustrated embodiment, the structure was within +10 with respect to aligned with the <110> direction. After this process, the next step will be taken bare silicon oxide layer 32 for use as a gate insulating layer Etching removed. The state of the tile at this time Point is shown in FIG. In the following, for the sample in the state of FIG causes the silicon to be etched. In this case, the so-called anisotropic etching is used, in which the etching speed depends on the Crystal direction is different.

In the embodiment shown, it was heated to 600 ° C + 20 ° C Hydrazine hydrate used. With this etchant, the etching speed is for one t100} - level of silicon about a hundred times larger than for a level and is about 1 Hm / min. If silicon is etched with this etchant for about 20 seconds, the exposed silicon layer becomes about 3000 a thick and the lower surface in the t1009 plane will be parallel to the surface of the sapphire substrate. Between this lower surface and the part covered by the gate insulating layer 32 is, a side surface occurs in the t111} 5 plane as a result of the etching which is inclined 540 44 sec. with respect to the # 00 # plane, and so the Mesa-type silicon layer. During this period also the # is polycrystalline Silicon layer 31 exposed to the etchant, but this etching process shows up no dependence on crystal faces and consequently the polycrystalline silicon layer 31 etched away by about 3000 a from each side. This state of the plate is in Fig. 6 shown.

Next, put the composite layer 44 on top of the polycrystalline Silicon layer 31 is removed by etching and then used as an impurity for formation from Source and drain regions phosphorus in the silicon layer 30 introduced with the help of ion implantation at a low energy of about 20 KeV and an ion density of approximately 1 x 1015 atoms / cm2. During this process the acceleration voltage is chosen so that no phosphorus enters the silicon layer 30, which is covered by the gate insulating layer 32, can penetrate, though the impurities are also introduced into the polycrystalline silicon layer 31. The sample is then subjected to a heat treatment in order to achieve deep diffusion to achieve the phosphorus, so that the diffused zones bottom on the substrate Reached below the bottom surface in the 2003 level and from the side surface in the 111- plane extends to a part below the edge of the gate electrode 31.

In the illustrated embodiment, a depth diffusion of about 0.4 pm under the influence of an oxygen atmosphere at 10,000 C for 30 minutes achieved. As a result, the source and drain regions have an impurity concentration of 1 x 1019 atoms / cm3, the gate zone has a similar concentration of impurities and the length of overlap between the gate electrode and the source or drain region becomes 0.1 Fm. A cross-sectional view of the sample at this point in time is shown in FIG. 7. With Using the conventional processes of vapor deposition of a silicon oxide layer 37 with With the help of CVD, etching of contact holes, vapor deposition of a conductive aluminum layer and patterning become a source layer wiring. , a drain wiring layer 39 and a gate wiring layer 40 with source zone 34, drain zone 33 and gate electrode 31 are connected through openings 42, 43 and 41, respectively. After that is the IG FET as shown in Figs. 3A and 3B is completed.

Even if the process for the production of IG FET's has only been described in connection with a typical embodiment, Of course, various changes and modifications to the above can be made Procedures are undertaken; so e.g.

the etchant can be delayed when introducing the impurities in the source and drain can be the composite layer 44 on the polycrystalline silicon layer 31, the impurities for forming the source and drain regions could be retained be introduced under such conditions that the imperfections through the exposed Part of the gate insulating layer 32 and also the impurities can be introduced after the protruding part of the gate insulating layer 32 is removed. Additionally is, as far as the selective etchant is concerned, that is necessary to carry out the present Invention is preferred whose etching speed for a t100 off level of Silicon is sufficiently faster than for a cm113 surface, and for the silicon nitride or silicon oxide as an etching mask is available, even if a Example that used hydrocine hydrate, described above, the invention not limited to this etchant only. A mixture of ethylene diamine and pyrocatechol and water in the ratio of 17 ml: 3 g: 8 ml is also an excellent caustic agent. Likewise, a 20 to 30% solution of potassium hydroxide and a 20 to 30% solution % caustic soda are described as excellent caustic agents, even if their Etching rates for silicon oxide are quite high.

Regarding the etching mask, even if in the example above the composite Layer of silicon nitride of about 2000 R thickness and silicon oxide of about 200 up to 300 ß thickness existed, this thickness of the etching mask can be varied in a wide range and even a silicon nitride layer approximately 200R thick can work well as an etching mask to serve. If it is desired to further simplify the manufacture of the etching mask, there is nothing wrong with even a simple layer of silicon oxide, even if their masking ability is lower than that of silicon nitride. In this case but must, since it is necessary that the etching mask itself at least over a period of time exists, which is sufficient for structuring the gate insulating layer, an etching mask that is at least thicker than the gate insulating layer, if the Gate insulating layer is made of the same material. Also, they're not just silicon nitrite or silicon oxide can be used as an etching mask, but also e.g. corrosion-resistant metal. If for the etch mask a material is used that has a sufficient Ensuring conductivity, it does not have to be removed in the step shown in FIG but it is possible to leave the etching mask in the end product. In this The case would result in the overlap between the source and drain zone and the gate electrode the depth diffusion of the impurities is controlled.

Second Preferred Embodiment In the second preferred embodiment in Figure 8 is encased on an insulating or semi-insulating GaAs substrate Iron 150 Wm thick with a resistivity of 1 x 104 cm or higher an n-type GaAs layer 85 formed with tellurium as doping and an impurity concentration of 3 x 1015 atoms / cm3 and a thickness of 1 Hm, a gallium oxide layer is produced by anodic oxidation, is used as the gate insulating layer 82, and a metal like molybdenum, platinum, etc.

is used as a gate electrode because of its low specific resistance 81 used. As can be seen from Fig. 8, the height of the major surfaces is the Parts of the source region 84 and drain region 83 that connect to the wiring layer create, deeper than the height of the semiconductor layer on which the gate insulation layer is formed and consequently the transition capacities can be reduced.

In addition, despite the fact that source and drain Zone 84 and 83 extend to the surface of the insulating substrate 86, the overlaps between the regions 83 and 84 and the gate 81 can be reduced and consequently is a reduction in both the source and drain junction capacitance and the electrical capacitance due to the overlap between gate and source or gate and Drain achieved what was difficult to achieve conventionally. Also protrude in this preferred embodiment the gate insulating layer 82 and the gate electrode 81 beyond the parts of the source and drain zones that lie on the channel-in zone. In this preferred embodiment, etching of the semiconductor layer becomes isotropic Etching is used and when doping the source and drain zone, thermal diffusion is used.

Third Preferred Embodiment A third preferred embodiment according to Fig. 9 uses the same materials as the second preferred embodiment, except that the gate electrode 91 is formed from polycrystalline gallium arsenide is. As can be seen from Figure 9, this preferred embodiment solves the problem of the prior art in a manner similar to the first and second described above Embodiment. It should be noted that in this b ~ preferred embodiment the overhang of the gate part, as it is in the second preferred embodiment was seen, is not available and consequently a further reduction in the coupling capacity between gate and source and between between gate and drain reached can be.

Fourth Preferred Embodiment In the fourth preferred embodiment 10, the gate electrode 71 is made of tungsten and the gate insulating layer 72 is made formed from silicon dioxide. The silicon single crystal layer 75, in the source and Drain regions 74 and 73 on a sapphire single crystal substrate with a {1T02} surface has a + 100g - plane as the main surface. The inclined surfaces of regions 73 and 74 extending to the end of the gate insulating layer 1113 faces and the gate 71 is arranged so that its edges are parallel to t110} - Can be directed towards the silicon layer. In this preferred embodiment the etching of the semiconductor layer is effected with the aid of an anisotropic etching process. As can be seen from FIG. 10, in this preferred embodiment the difficulties of the prior art in a manner similar to the previous ones Embodiments are solved. In addition, this preferred embodiment has compared to the second and third embodiment described above, the advantage that the fluctuations in the structure are small because of the inclined side surfaces of zones 73 and 74 are determined by the crystal structure.

Fifth Preferred Embodiment In this preferred embodiment is the design of the source or drain zone 64, which is in a semiconductor layer 65 are formed on an insulating substrate 66 in the so-called niche shape (recessed shape) made by decreasing its surface from the to the Gate electrode 61 and gate insulating layer 62 adjacent point and again rising Surface at one end part at the same level as the channel zone. Even with such an arrangement of the source and drain regions can have the same effects and advantages as in the previous preferred embodiments are achieved and the The structure of the preceding forms of expression could be changed to such an Auf ## u ~ will.

Claims (5)

P a -t e n t a n s p r ü c h e 1. Insulating layer field effect transistor (IG FET) with an island-shaped semiconductor layer on the surface of an insulating Substrate, a source zone and a drain zone in the semiconductor layer, one Channel zone between source and drain zone, a gate insulating layer on the channel zone and a gate electrode on this insulating layer, thereby g e k e n n n z e i c h n e t that the semiconductor layer (33, 34, 35) has a first surface parallel to the surface of the substrate (36), second surfaces on either side of the first Surface parallel to the substrate surface, which is closer to the substrate surface lies as the first surface and lateral surfaces that each has the connect the first surface to the second, the drain and source zones respectively from the second surfaces to the respective part of the substrate surface below this extend and on the side surfaces and the respective end of the first surface are shaped so that the pn junction is essentially parallel to the lateral Surfaces and the channel zone is on the first surface. 2. Insulating gate field effect transistor with an island-shaped semiconductor layer on the surface of an insulating substrate, a source and a drain region in the semiconductor layer, a channel zone between source and drain, a gate insulating layer on the channel region and a gate electrode on this insulating layer, thereby g e k e n n -z e i c h n e t that the source zone (34) and drain zone (33) each have one first part (34 ', 33') which lies on the channel zone (35) and a first surface in the extension of the surface of the channel zone (35) has a second part (34 ″, 33 ''), which is to the side of this first part, has a second surface on a Height closer to the surface of the insulating substrate (36) than the first Surface of the first parts (34 ', 33') lies, and a bottom part on the main surface of the insulating substrate (36), and a third part (34 "', 33"') which is continuous the first (34 ', 33') and second (34 ", 33") part connects together and one third surface that slopes from the first surface of the first part to the second surface of the second part, and that the gate insulating layer (32) on the channel zone (35) and the first surface the first Parts (34 ', 33') of the drain and source zone is formed. 3. insulating layer field effect transistor according to claim 1, characterized in that g e k e n n n e i c h n e t that the distance (t1) between the house surface of the insulating substrate (36) and the first surface of the semiconductor layer 1,5 to 3 times greater than the distance (t2) between the main surface of the insulating Substrate (36) and the second surfaces of the semiconductor layer. 4. Insulated gate field effect transistor with an insulating substrate with a flat surface and a semiconductor layer on the flat surface of the insulating substrate, characterized in that the semiconductor layer first, second, third, fourth and fifth parts arranged directly next to one another (34 ", 34" ', 34' and 35 and 33 ', 33 "', 33"), the third part in the has essentially the greatest thickness of the five parts, the first and fifth parts essentially the same and smallest thickness and the second and fourth part ascending surfaces have a source region formed over the entire thickness of the first part is and extends through the top of the second part to the top of one end of the third part that a drain region extends in the entire thickness of the fifth Part is formed and extends through the upper piece of the fourth part to the upper Piece at the other end of the third part that extends a gate insulating layer on the third part and a gate electrode on the Gate insulating layer lies. 5. A process z # production of insulated gate field effect transistors, in that it contains the following steps: Training a silicon layer in the shape of an island with a main surface in a ^ <100! -Plane on the major surface of an insulating substrate; Formation of a gate insulating layer on the silicon layer; Forming a gate electrode layer on the gate insulating layer; Forming an etching mask layer on the conductive electrode layer; structuring the etching mask, the electrode layer and the in gate insulating layer of the same Arrangement in the plane; Etching the exposed silicon layer with a selective Etchant that has an etch rate for {100} planes of silicon that is greater istils for {111} planes of silicon to make the silicon layer in mesa shape forming a first surface in the {100} plane below the gate insulating layer, second surfaces in the {1O0} plane that are on either side of the first surface are closer to the main surface of the insulating substrate than the first surface, and side surfaces in the £ 111 # level, each with the first surface connects the second surfaces; Introduction of imperfections to form the source and drain regions to such an extent that under the second The surface imperfections extend to and from the bottom of the layer on the substrate the side surface the impurities up to a part below the gate electrode are sufficient.