DE19700854B4 - Method for producing an insulation layer for a semiconductor device - Google Patents
Method for producing an insulation layer for a semiconductor device Download PDFInfo
- Publication number
- DE19700854B4 DE19700854B4 DE19700854A DE19700854A DE19700854B4 DE 19700854 B4 DE19700854 B4 DE 19700854B4 DE 19700854 A DE19700854 A DE 19700854A DE 19700854 A DE19700854 A DE 19700854A DE 19700854 B4 DE19700854 B4 DE 19700854B4
- Authority
- DE
- Germany
- Prior art keywords
- layer
- insulation layer
- substrate
- isolation
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
Verfahren
zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung,
mit folgenden Schritten:
a) Bilden einer ersten und einer zweiten
Isolationsschicht (32, 33) übereinanderliegend
auf einem Substrat (31);
b) Strukturieren der ersten und der
zweiten Isolationsschicht (32, 33) zum Festlegen von ersten und
zweiten Isolationsbereichen (34, 35), wobei der zweite Isolationsbereich
(35) weiter ist als der erste Isolationsbereich (34);
c) Bilden
einer zusätzlichen
Isolationsschicht auf der gesamten resultierenden Oberfläche;
d)
isotropes Rückätzen der
zusätzlichen
Isolationsschicht, so daß im
ersten Isolationsbereich (34) eine diesen auffüllende Schutzschicht (36) und
am Bodenbereich des zweiten Isolationsbereichs (35) Seitenwandstücke (36a)
verbleiben;
e) Bilden einer Feldoxidschicht (37) im zweiten
Isolationsbereich (35) durch Oxidation;
f) Entfernen der Schutzschicht
(36) im ersten Isolationsbereich (34);
g) Ätzen des Substrats (31) im
ersten Isolationsbereich (34) bis zu einer vorbestimmten Tiefe,
um einen Graben (38) zu erhalten; und
h) Ausfüllen des
Grabens (38) mit einer...Method for producing an insulation layer for a semiconductor device, comprising the following steps:
a) forming a first and a second insulating layer (32, 33) superimposed on a substrate (31);
b) patterning the first and second insulating layers (32, 33) to define first and second isolation regions (34, 35), the second isolation region (35) being wider than the first isolation region (34);
c) forming an additional insulating layer on the entire resulting surface;
d) isotropic etching back of the additional insulating layer, so that in the first insulating region (34) a protective layer (36) filling up the latter and at the bottom region of the second insulating region (35) side wall pieces (36a) remain;
e) forming a field oxide layer (37) in the second isolation region (35) by oxidation;
f) removing the protective layer (36) in the first isolation region (34);
g) etching the substrate (31) in the first isolation region (34) to a predetermined depth to obtain a trench (38); and
h) filling in the trench (38) with a ...
Description
- Priorität: 26. Juni 1996 Korea (KR) Nr. 24092/1996Priority: June 26, 1996 Korea (KR) No. 24092/1996
Die vorliegende Erfindung bezieht sich auf ein Verfahren zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung, und inbesondere auf ein Verfahren zur Herstellung einer solchen Isolationsschicht, durch die die Isolationseigenschaften hochintegrierter Einrichtungen verbessert werden.The The present invention relates to a method of manufacture an insulation layer for a semiconductor device, and more particularly to a method of Production of such an insulating layer, through which the insulating properties of highly integrated Facilities are improved.
Ein
koventionelles Verfahren zur Bildung einer Isolationsschicht für eine Halbleitereinrichtung wird
nachfolgend unter Bezugnahme auf die
Gemäß
Wie
die
Gemäß
Beim konventionellen Verfahren zur Bildung der Isolationsschicht treten allerdings einige Nachteile auf. So ist die Kante des geätzten Bereichs des Substrats relativ scharf, so daß sich dort eine hohe elektrische Feldkonzentration ergibt, was zu einem Leckstrom führt. Wird dagegen ein ausgedehnterer Isolationsbereich gebildet, so ist auch der zu ätzende Bereich auf dem Substrat größer. Die Oberfläche des Isolationsbereichs wird dadurch unebener.At the conventional methods for forming the insulating layer occur however, some disadvantages. Such is the edge of the etched area of the substrate relatively sharp, so that there is a high electrical Field concentration results, resulting in a leakage current. Becomes on the other hand, a more extensive isolation area is formed, so too the area to be etched bigger on the substrate. The surface of the insulation area is thereby uneven.
Aus
der
Danach wird die Siliziumnitridschicht zwischen den Seitenwandbereichen im weiten Isolationsbereich entfernt, um die Oberfläche des Substrats freizulegen. Bevor dann durch thermische Oxidation ein Siliziumoxidfilm am Boden des weiten Isolationsbereichs ausgebildet wird, werden die Seitenwandstücke aus Siliziumoxid zusammen mit dem Schutzfilm aus Siliziumoxid im schmalen Isolationsbereich entfernt.After that the silicon nitride layer will be between the sidewall regions in the wide isolation area removed to the surface of the To expose substrate. Before then by thermal oxidation Silicon oxide film formed at the bottom of the wide isolation region becomes, the side wall pieces become of silicon oxide together with the protective film of silicon oxide in the narrow isolation area away.
Während der thermischen Oxidation zur Ausbildung des Siliziumoxidfilms dienen dann auf der Substratoberfläche liegende Abschnitte der Siliziumnitridschicht als Oxidationsschutzmasken.During thermal oxidation to Formation of the silicon oxide film then serve on the substrate surface lying portions of the silicon nitride layer as oxidation masks.
Nach der Durchführung der thermischen Oxidation werden die Siliziumnitridschichten entfernt und das freiliegende Substrat wird geätzt, um Grabenbereiche zu erhalten, die dann mit Siliziumoxid aufgefüllt werden.To the implementation the thermal oxidation, the silicon nitride layers are removed and the exposed substrate is etched to obtain trench areas then filled with silica become.
Die
Die
Weiter
ist es aus der
Die
Davon ausgehend liegt der Erfindung die Aufgabe zugrunde, ein weiteres Verfahren zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung bereitzustellen, das es auf einfache Weise ermöglicht, sowohl schmale als auch weite Isolationsbereiche zuverlässig auszubilden.From that Based on the object of the invention, another Method for producing an insulation layer for a semiconductor device which allows it to be easily handled, both narrow and also to reliably form wide insulation areas.
Diese Aufgabe wird durch das Verfahren nach Anspruch 1 gelöst.These The object is achieved by the method according to claim 1.
Dagegen finden sich vorteilhafte Ausgestaltungen der Erfindung in den nachgeordneten Unteransprüchen.On the other hand find advantageous embodiments of the invention in the subordinate Dependent claims.
Die Erfindung ermöglicht es somit, Isolationsbereiche größerer und geringerer Breite gleichzeitig durch einen photolithographischen Prozeß herzustellen.The Invention allows it thus, isolation areas larger and lesser width at the same time by a photolithographic Process to produce.
Nachfolgend wird die Erfindung unter Bezugnahme auf die Zeichnung im einzelnen beschrieben. Es zeigen:following the invention with reference to the drawings in detail described. Show it:
Die
Gemäß
Anschließend wird
auf die gesamte Oberfläche
der so erhaltenen Struktur eine zusätzliche Isolationsschicht/Schutzschicht
aufgebracht, und zwar durch ein CVD-Verfahren, also durch chemische Dampfabscheidung
im Vakuum. Die zusätzliche
Isolationsschicht/Schutzschicht kommt also auf der Siliziumnitridschicht
Sodann
wird die zusätzliche
Isolationsschicht/Schutzschicht entsprechend der
Wie
die
Entsprechend
der
Wie
die
Das
Zurückätzen der
dritten Isolationsschicht
In Übereinstimmung mit der Erfindung liegt die Isolationsschicht im schmaleren Isolationsbereich senkrecht zum Substrat bzw. zur Substratoberfläche. Dies vergrößert die Isolationseigenschaft der Einrichtung und verbessert somit deren Betriebszuverlässigkeit. Darüber hinaus lassen sich der schmalere Isolationsbereich und der weitere bzw. breitere Isolationsbereich durch einen fotolithografischen Prozeß gleichzeitig herausbilden, was deren Herstellung vereinfacht.In accordance with the invention, the insulating layer in the narrower isolation region is perpendicular to the substrate or to the substrate surface. This increases the insulating property of the device and thus improves its operational reliability. In addition, the narrower isolation region and the wider or wider isolation region can be achieved by a photolithographic process at the same time, which simplifies their manufacture.
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960024092A KR980006053A (en) | 1996-06-26 | 1996-06-26 | Method for forming a separation film of a semiconductor device |
KR24092/96 | 1996-06-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19700854A1 DE19700854A1 (en) | 1998-01-02 |
DE19700854B4 true DE19700854B4 (en) | 2007-04-05 |
Family
ID=19463615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19700854A Expired - Fee Related DE19700854B4 (en) | 1996-06-26 | 1997-01-13 | Method for producing an insulation layer for a semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH1050818A (en) |
KR (1) | KR980006053A (en) |
DE (1) | DE19700854B4 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000041419A (en) * | 1998-12-22 | 2000-07-15 | 김영환 | Method of forming device isolation region |
KR100824632B1 (en) * | 2006-08-31 | 2008-04-25 | 동부일렉트로닉스 주식회사 | Method of Manufacturing Semiconductor Device by 90nm Design Rule |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3715092A1 (en) * | 1986-05-09 | 1987-11-12 | Seiko Epson Corp | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT |
US4842675A (en) * | 1986-07-07 | 1989-06-27 | Texas Instruments Incorporated | Integrated circuit isolation process |
US5096848A (en) * | 1990-02-23 | 1992-03-17 | Sharp Kabushiki Kaisha | Method for forming semiconductor device isolating regions |
US5272117A (en) * | 1992-12-07 | 1993-12-21 | Motorola, Inc. | Method for planarizing a layer of material |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53148389A (en) * | 1977-05-31 | 1978-12-23 | Fujitsu Ltd | Manufacture for semiconductor device |
JPH05206263A (en) * | 1992-01-29 | 1993-08-13 | Sharp Corp | Manufacture of semiconductor device |
JPH06151578A (en) * | 1992-11-04 | 1994-05-31 | Hitachi Ltd | Semiconductor device and its manufacture |
JP3102197B2 (en) * | 1993-04-12 | 2000-10-23 | 富士電機株式会社 | Wafer dielectric isolation method |
US5362669A (en) * | 1993-06-24 | 1994-11-08 | Northern Telecom Limited | Method of making integrated circuits |
JPH07135247A (en) * | 1993-11-10 | 1995-05-23 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
-
1996
- 1996-06-26 KR KR1019960024092A patent/KR980006053A/en not_active Application Discontinuation
-
1997
- 1997-01-13 DE DE19700854A patent/DE19700854B4/en not_active Expired - Fee Related
- 1997-05-09 JP JP9134519A patent/JPH1050818A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3715092A1 (en) * | 1986-05-09 | 1987-11-12 | Seiko Epson Corp | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT |
US4842675A (en) * | 1986-07-07 | 1989-06-27 | Texas Instruments Incorporated | Integrated circuit isolation process |
US5096848A (en) * | 1990-02-23 | 1992-03-17 | Sharp Kabushiki Kaisha | Method for forming semiconductor device isolating regions |
US5272117A (en) * | 1992-12-07 | 1993-12-21 | Motorola, Inc. | Method for planarizing a layer of material |
Also Published As
Publication number | Publication date |
---|---|
JPH1050818A (en) | 1998-02-20 |
DE19700854A1 (en) | 1998-01-02 |
KR980006053A (en) | 1998-03-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |