DE19681705T1 - Verfahren und Einrichtung zum schnellen Decodieren von auf 00H- und 0FH-abgebildeten Instruktionen - Google Patents
Verfahren und Einrichtung zum schnellen Decodieren von auf 00H- und 0FH-abgebildeten InstruktionenInfo
- Publication number
- DE19681705T1 DE19681705T1 DE19681705T DE19681705T DE19681705T1 DE 19681705 T1 DE19681705 T1 DE 19681705T1 DE 19681705 T DE19681705 T DE 19681705T DE 19681705 T DE19681705 T DE 19681705T DE 19681705 T1 DE19681705 T1 DE 19681705T1
- Authority
- DE
- Germany
- Prior art keywords
- decoding instructions
- quickly decoding
- instructions mapped
- mapped
- quickly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/579,419 US5740392A (en) | 1995-12-27 | 1995-12-27 | Method and apparatus for fast decoding of 00H and OFH mapped instructions |
PCT/US1996/020828 WO1997024659A1 (en) | 1995-12-27 | 1996-12-27 | Method and apparatus for fast decoding of ooh and ofh mapped instructions |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19681705T1 true DE19681705T1 (de) | 1998-11-05 |
DE19681705C2 DE19681705C2 (de) | 2000-12-14 |
Family
ID=24316830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19681705T Expired - Lifetime DE19681705C2 (de) | 1995-12-27 | 1996-12-27 | Verfahren und Einrichtung zum schnellen Decodieren von 00H- und 0FH-abgebildeten Instruktionen |
Country Status (8)
Country | Link |
---|---|
US (1) | US5740392A (de) |
KR (1) | KR100286417B1 (de) |
AU (1) | AU1356497A (de) |
DE (1) | DE19681705C2 (de) |
GB (1) | GB2322211B (de) |
HK (1) | HK1015901A1 (de) |
WO (1) | WO1997024659A1 (de) |
ZA (1) | ZA9610675B (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE9704476L (sv) * | 1997-12-02 | 1999-06-23 | Ericsson Telefon Ab L M | Utökad instruktionsavkodning |
US6134650A (en) * | 1997-12-12 | 2000-10-17 | Advanced Micro Devices, Inc. | Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data |
US6061775A (en) * | 1997-12-12 | 2000-05-09 | Advanced Micro Devices, Inc. | Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types |
US5890006A (en) * | 1997-12-12 | 1999-03-30 | Advanced Micro Devices, Inc. | Apparatus for extracting instruction specific bytes from an instruction |
US6308257B1 (en) | 1999-04-20 | 2001-10-23 | Intel Corporation | Method and apparatus for generating boundary markers for an instruction stream including variable-length instructions |
US7711926B2 (en) * | 2001-04-18 | 2010-05-04 | Mips Technologies, Inc. | Mapping system and method for instruction set processing |
US7139900B2 (en) | 2003-06-23 | 2006-11-21 | Intel Corporation | Data packet arithmetic logic devices and methods |
US7917734B2 (en) | 2003-06-30 | 2011-03-29 | Intel Corporation | Determining length of instruction with multiple byte escape code based on information from other than opcode byte |
JP2007122626A (ja) * | 2005-10-31 | 2007-05-17 | Matsushita Electric Ind Co Ltd | マイクロプロセッサ |
KR100779109B1 (ko) * | 2006-09-22 | 2007-11-27 | 한국인터넷진흥원 | Rfid 코드 생성방법 |
US8281109B2 (en) * | 2007-12-27 | 2012-10-02 | Intel Corporation | Compressed instruction format |
WO2013101042A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Indicating a length of an instruction of a variable length instruction set |
US8930678B2 (en) * | 2012-04-26 | 2015-01-06 | Intel Corporation | Instruction and logic to length decode X86 instructions |
US11204768B2 (en) | 2019-11-06 | 2021-12-21 | Onnivation Llc | Instruction length based parallel instruction demarcator |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3711692A (en) * | 1971-03-15 | 1973-01-16 | Goodyear Aerospace Corp | Determination of number of ones in a data field by addition |
US3723715A (en) * | 1971-08-25 | 1973-03-27 | Ibm | Fast modulo threshold operator binary adder for multi-number additions |
US4161784A (en) * | 1978-01-05 | 1979-07-17 | Honeywell Information Systems, Inc. | Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands |
US4418383A (en) * | 1980-06-30 | 1983-11-29 | International Business Machines Corporation | Data flow component for processor and microprocessor systems |
US4393468A (en) * | 1981-03-26 | 1983-07-12 | Advanced Micro Devices, Inc. | Bit slice microprogrammable processor for signal processing applications |
US4498177A (en) * | 1982-08-30 | 1985-02-05 | Sperry Corporation | M Out of N code checker circuit |
US4707800A (en) * | 1985-03-04 | 1987-11-17 | Raytheon Company | Adder/substractor for variable length numbers |
JPS6297060A (ja) * | 1985-10-23 | 1987-05-06 | Mitsubishi Electric Corp | デイジタルシグナルプロセツサ |
US4989168A (en) * | 1987-11-30 | 1991-01-29 | Fujitsu Limited | Multiplying unit in a computer system, capable of population counting |
KR920007505B1 (ko) * | 1989-02-02 | 1992-09-04 | 정호선 | 신경회로망을 이용한 곱셈기 |
US5113515A (en) * | 1989-02-03 | 1992-05-12 | Digital Equipment Corporation | Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer |
US5187679A (en) * | 1991-06-05 | 1993-02-16 | International Business Machines Corporation | Generalized 7/3 counters |
GB2263987B (en) * | 1992-02-06 | 1996-03-06 | Intel Corp | End bit markers for instruction decode |
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
US5572682A (en) * | 1992-04-03 | 1996-11-05 | Cyrix Corporation | Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window |
-
1995
- 1995-12-27 US US08/579,419 patent/US5740392A/en not_active Expired - Lifetime
-
1996
- 1996-12-19 ZA ZA9610675A patent/ZA9610675B/xx unknown
- 1996-12-27 WO PCT/US1996/020828 patent/WO1997024659A1/en active IP Right Grant
- 1996-12-27 GB GB9812272A patent/GB2322211B/en not_active Expired - Lifetime
- 1996-12-27 DE DE19681705T patent/DE19681705C2/de not_active Expired - Lifetime
- 1996-12-27 KR KR1019980704971A patent/KR100286417B1/ko not_active IP Right Cessation
- 1996-12-27 AU AU13564/97A patent/AU1356497A/en not_active Abandoned
-
1999
- 1999-02-19 HK HK99100681A patent/HK1015901A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5740392A (en) | 1998-04-14 |
AU1356497A (en) | 1997-07-28 |
HK1015901A1 (en) | 1999-10-22 |
DE19681705C2 (de) | 2000-12-14 |
KR100286417B1 (ko) | 2001-04-16 |
WO1997024659A1 (en) | 1997-07-10 |
ZA9610675B (en) | 1997-08-22 |
GB2322211B (en) | 2000-08-02 |
GB2322211A (en) | 1998-08-19 |
GB9812272D0 (en) | 1998-08-05 |
KR19990076844A (ko) | 1999-10-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
8607 | Notification of search results after publication | ||
8607 | Notification of search results after publication | ||
8607 | Notification of search results after publication | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
R071 | Expiry of right |