DE19643688C2 - Method for controlling a cache memory unit with conflict-free parallel access to virtual, 2-dimensional address spaces - Google Patents

Abstract

Cache memory unit for use in parallel processors with N Z M processing units, which uses only local addresses that are bound to two-dimensional data structures - called objects. Each object is divided into virtual blocks of size S VB, h = (N + 1) Z 2 X in the horizontal direction and S VB, v = (M + 1) Z 2 Y in the vertical direction, X and Y being selectable. The data of the object are distributed to (N + 1) Z (M + 1) memory banks in such a way that exactly one physical block per set is occupied in each memory bank for each virtual block. Each memory bank consists of N MSet = S VB, v div (M + 1) logical sets, which in turn are composed of a freely selectable number of physical blocks of size S MBlock = S VB, h div (N + 1). The hit / miss detection takes place in the virtual object address space, the tag register containing the object number and the start address of the block in each dimension. The tag registers are integrated into the processing units themselves. When the data is transferred in blocks between the cache and the external main memory, due to the special distribution of the data over the banks in the main memory address space, adjacent data can be written in parallel to the cache memory banks or read from them.

Description

The invention relates to a method for controlling a Ca Memory unit for use in a parallel processor according to the preamble of claim 1.

With the advances in semiconductor technology, it is today possible microprocessors with several, working in parallel To integrate processing units monolithically and thus a processing power of several giga operations per Second to reach. Such processors require lei sustainable storage architectures to take advantage of the high ver provide the resulting data rate len. To the implementation effort for a Keeping such a processor as small as possible is often meh rere processing units of such a processor a ge assigned common control, which then synchronized identical operations on different data To run. Known techniques are SIMD (Single Instruc tion stream multiple data stream) processors, in which all existing processing units of a central control assigned or clustered SIMD architectures (Mul tiple SIMD: MSIMD), each with groups of processing units permanently or for a certain period of time Control can be assigned and work synchronously.

The parallel execution of an algorithm on such a synchronized group of processing units, in particular that of digital signal processing, leads to characteristic access patterns of the parallel processing units to the data to be processed. When processing common two-dimensional data structures, accesses in the form of a matrix with distances 2 ^x , x = 0, 1, 2,. , between the elements, see also the dissertation by K. Rönner, "A highly parallel RISC architecture optimized for image processing processes", VDI-Verlag 1995 , pp. 15-18.

The high memory tape required for parallel processors to provide wide, the during an access cycle clus of data required for parallel processing units if possible during a single storage cycle time be put. This can be achieved by using the Data appropriately on a number of memory banks be distributed. Conflict-free access then takes place if they are used to assign the data to the memory banks Dete distribution function ensures that everyone is allowed The maximum amount of data that can be accessed from a memory bank are needed, such as these parallel access ports owns.

According to the current state of the art, memory architectures are already known which permit conflict-free access to two-dimensionally arranged data for a given access scheme, for example from the book by Gössel / Rebel / Creutzburg, "Memory Architecture and Parallel Access", Akademie Verlag 1989 , the dissertation by Volkers, "A contribution to memory architectures of programmable multi-processors of image processing", VDI Verlag 1992 , and the patents DE 27 47 075, US 4,400,768 and US 4,051,551. The memory architectures described there each use a single two-dimensional virtual address space for addressing the data. The localization of the data distributed in each case on a number of memory banks takes place via defined functions which determine the associated memory bank and the address within this bank for each addressed date, the so-called distribution and address functions. This is achieved by arithmetic logic corresponding to the functions mentioned, which calculates the physical memory addresses from the virtual matrix addresses and, if appropriate, auxiliary registers, and selects the addressed memory blocks.

However, the previously known approaches have the disadvantage that that the number of elements of the virtual address space the Number of words actually in the memory banks must not exceed. The integration of such Storage in a hierarchical considered advantageous Storage organizations using a large main storage relatively slow access through a small buffer memory with a short access time, also called a cache, is supplemented and the local and temporal locality of the Data access of the algorithms is used in the mentioned memory architectures not applicable. This is there due to the fact that instead of short, on the size of the local memory limited addresses now ent address words who uses the size of the main memory address space have to. This increases the complexity of the used disproportionate arithmetic logic, increase at the same time the times required for the address calculation so that an integration in the usual with microprocessors Pipeline scheme leads to significant memory latency. Of the hit / miss detection necessary for caches, that in known cache architectures by comparing the Access address with the upper one stored in a tag register Part of the address from the main memory to the cache mirrored blocks of memory is not applied because by distributing the data across multiple banks a block-by-block organisa for conventional caches tion of the data in linear sequence in the cache is not opposed ben is (see the U.S. book by J. Hennessy / D. Patter  son: "Computer Architecture, a Quantitative Approach", Morgan Kaufmann Publishers, 1990, pp. 402-497).

The invention has for its object one for the monoli thical integration suitable, low-effort cache memory develop parallel access architecture that is suitable for N. M parallel, synchronous processing units on the one hand Read and write access to shared data structure ren in the form of matrices with N × M elements and degenerate matrices (vectors) with N or M elements and a should allow individual data words, where N and M are any Represents power of two. Address distances the size of a any power of two in any dimension between the el ment should be allowed. The allowable size of the data The actual size of the structure should consist of several Memory banks may exceed existing cache memory, when accessing data that is not in the cache this from a conventional one in the background Main memory reloaded.

In the method according to the invention, each becomes two-dimensional len data structure to which a group of synchronized Accesses processing units, its own, virtual, assigned two-dimensional address space, which in the following Ob is called jekt. The address space assigned to the data structure corresponds to this in its dimensions, the different Address spaces are distinguished by a consecutive number the. Data is addressed within an object exclusively with local virtual addresses within the Object address space. This offers a number of essential advantages le: On the one hand, the size is usually to be processed Objects well below the size of common main memory address spaces, therefore, the maximum size of the allowable object address space be kept correspondingly smaller, which is a reduction the effort for the address arithmetic and a corresponding  higher processing speed of the address arithmetic be works. Second, the time-consuming transformation of virtual addresses to physical memory addresses between addressing and addressing the word in the cache. This leads to a significant reduction in latency for such a memory. The transformation to physi Main memory addresses, on the other hand, are only stored in the block shows how the cache content was loaded or written or executed in the main memory, where this is far less is time critical.

The cache memory is also for the user or compiler completely transparent, d. H. requesting data from the Main memory or the write-back no longer required Data happens automatically. The very elaborate and compiler hostile management of a local limited in size Parallel access memory, according to the previous State of the art to be carried out by the user himself had to be omitted completely when using the invention, whereby at the same time, the hardware expenditure for such a memory is also lower than in the previously known solutions. Addressing data only with local position within a data structure instead of a main memory The address also simplifies programming considerably.

The introduction of the cache principle for a two-dimensional Address space also has the advantage that the typical in both Dimensions with different degrees of time and local location of algorithms of the two-dimensional digi tal signal processing from the Speicherar invention architecture is used much better than with caches after the current state of the art, which is only a linear, have one-dimensional address space.

The invention is explained below with reference to the drawing. The drawing shows:  

Fig. 1 is a block diagram of a parallel computer with synchronized processing units

Fig. 2 shows an example of a matrix-like access to an object

Fig. 3 shows the distribution of the data of an object to a number of memory banks and the introduction of virtual blocks in Objektadreßraum

Fig. 4 shows the arrangement of the data within an example selected memory bank

Fig. 5 shows the structure of an address computer unit for locating the data in memory

Fig. 6, the structure of a tag for localization of data in memory

The parallel computer of FIG. 1 comprises one or more groups of N. M with N, M = 1, 2,. , ., parallel, with each other synchronized processing units 10 , which can read and write via a memory crossbar 11 to access the cache memory 12 . The term processing unit 10 each includes an arithmetic logic unit together with a register file for temporary storage, an address computer, which can also be integrated into the arithmetic logic units, and hit / miss detection logic. The processing units 10 are controlled by one or more control units 15 , which also generate the addresses for the parallel access. The cache memory 12 consists of R. Q individual memory banks 13 , where R = N + 1 and Q = M + 1, and an I / O processor 14 . The I / O processor serves to transfer the data between the cache and external main memory, it can access the main memory 17 via a data and address bus 16 .

From the point of view of the processing units, the cache memory provides a large number of two-dimensional virtual address spaces, which are distinguished by an optional number, the object number. Fig. 2 shows an example of such a virtual address space, to the N = 2, M = 2 processing units accessed. Data 20 within the address space are addressed by a horizontal address component A _h 21 and a vertical address component A _v 22. FIG. 2 also shows the matrix accesses permitted for the address space for the example of FIG. 2. 2 processing units. A matrix access is characterized by the horizontal and vertical address components A _{h, R} and A _{v, R of} the reference element 23 , which represents the top left corner of the matrix. The position of the other elements results from the element distances D _h and D _v in the horizontal and vertical directions. The distances D _h and D _v may assume any powers of 2. If one or both distances are chosen to be 0, the matrix degenerates into a vector or scalar, the same data being then assigned to several processing units in accordance with FIG. 2.

Fig. 3 shows the distribution of the data of an address space to the memory banks of the cache memory of an example 2. 2 processing units. Depending on the dimensioning selected, 9 memory banks are required. Numbers 0-8 in Fig. 3 indicate which memory bank the date located at the corresponding location is physically assigned. For other N, M, the distribution is made accordingly, so that every R.-th date is assigned to a line of the same memory bank and the lines repeat with the frequency Q.

According to the invention, each object is now logically divided into two-dimensional virtual blocks ( 30 ), which represent the smallest common data structure that is managed by the cache. This division corresponds to the block division of the entire linear address space in a conventional cache. The difference to this is that the virtual blocks have two address dimensions and are not bound to the main memory address space, but to the local, virtual address space of each data structure. A virtual block thus represents a section of the object address space that extends over two dimensions. The size of the blocks S _{VB, H} in the horizontal direction and S _{VB, v} in the vertical direction results in S _{VB, h} = R. 2 ^X and S _{VB, v} = Q. 2 ^Y with X, Y = 0, 1, 2. , , freely selectable. FIG. 3 shows the division into virtual blocks 30 of this type , here again as an example for FIG. 2. 2 processing units and with S _{VB, h} = S _{VB, v} = 12.

Each of the total R. Q memory banks of the cache memory are now logically divided into a number of sets (N _MSet ), ( 40 ). Let N _MSet = S _{VB, V} div Q, where div is to be understood as an integer division. Each set is in turn divided into a number of blocks ( 41 ) to form several data words, which are referred to as physical blocks to distinguish them from the virtual blocks of the objects. The number of physical blocks N _MBlock can be chosen as desired, with N _MBlock preferably being _chosen to a power of 2 to reduce the address _{calculation effort} . To store a virtual block ( 30 ), a physical block ( 41 ) is allocated per bank in each set ( 40 ). The location of each data word contained in the access matrix at the location A _h , A _v within the object is then as follows:
Bank selection: distribution function

A _Bank = A _h modR + R. (A _v modQ) (Eq. 1)

Set selection: set function

A _MSet = (A _v modS _{VB, v} ) div Q = (A _v divQ) mod 2 ^Y (Eq. 2)

Selection of physical block: Any method for cache blocker replacement, e.g. B. least-recently-used, direct mapped or fully associative, see e.g. B. The U.S. book by D. Hennessy and D. Patterson: Computer Architecture - A Quantitative Approach, Morgan-Kaufmann, 1990. pp. 408-414
Offset address in the physical block: address function

A _PBlock = (A _h modS _{VB, h} ) div R = (A _h divR) mod 2 ^X (Eq. 3)

Fig. 4 shows the arrangement of the data of any selected object with the number "3" using the example of memory bank No. 0. The size of the virtual block corresponds to the example given in Fig. 3 (X, Y = 2). The remaining memory banks are structured accordingly and contain the remaining data assigned via the distribution function (Eq. 1).

In the practical implementation of the address computer, the fact is used that, according to equations Eq. 1 to Eq. 3 only division and modulus formation with R is required. The modulo operations 2 ^X and 2 ^Y in the ge equations can be determined without arithmetic effort by directly tapping the lowest bits of the intermediate results. FIG. 5 shows the exemplary implementation of an address computer with the parameters N = M = 2, R = Q = 3, S _{VB, v} = 12, S _{VB, h} = 12 and N _MSet = 4. An address computer corresponding to FIG. 5 is required once per processing unit. The address parameters of the matrix, which are characterized in FIG. 2, are passed through the program flow to all processing units which, based on their position in the matrix of the processing units by means of the address calculation unit according to FIG. 5, initially address A _h , A _v of them calculate the respectively assigned data word in the virtual address space and use it to calculate the position of the corresponding data word in the cache. The address computer consists only of two three-operand adders, two modulo and two division units with the width of the maximum address word width per component that is permissible for an object. For a different parameterization N, M, S _{VB, v} , S _{VB, h} only the values of the fixed value modulo or division units and the taps of the result bits change according to equations 1-3.

The hit / miss detection of the cache takes place via a tag register which, according to FIG. 6, contains the object number and the horizontal and vertical virtual block address A _{VBT, h} and A _{VBT, v} . These are defined as
Horizontal virtual block address:

A _{VBT, h} = A _{BS, h} div S _{vB, h} (Eq. 4)

Vertical virtual block address:

A _{VBT, v} = A _{BS, v} div S _{vB, v} (Eq. 5)

where A _{BS, h} , A _{BS, v represent} the beginning of the virtual block, ie the address components of the word with the lowest address in the virtual block, in the two-dimensional object address space.

Depending on the number of physical blocks N _MBlock per set, a tag register _file with N _MBlock tag registers is required for the cache unit. The tag register file can be selected once per synchronized group of N. M processing units are present, in which case N. M simultaneous access to the tag register file for hit / miss detection is necessary. It is less expensive to provide the tag register file once per processing unit, in which case only a single, simultaneous access is then required. In this case, the content of the tag register files is identical for all processing units. In contrast to conventional caches, the tag register file is then integrated directly into the processing units instead of being assigned to the cache blocks. As a result, the hit-miss comparison can be carried out simultaneously with the transport of the addresses through the memory crossbar, which significantly reduces the latency of the cache.

Depending on the selected block selection strategy, the content of one or more tags with intermediate results from the address calculation circuit according to FIG. 5 is compared per access to the cache. A hit is given if the object numbers of a tag and the local access address match and for this tag A _{VBT, h} = A _{VB, h} and A _{VBT, v} = A _{VB, v} with A _{VB, h} and A _{VB, h} corresponding to FIG. 5.

In the event of a hit, the cache, the position of the searched data word is determined via the address calculation circuit according to FIG. 5 and read from the position in question in the selected cache bank or written to it. In the event of a miss, the processing units which are synchronized with one another are stopped and the missing virtual block is reloaded via the I / O processor, and the associated tag register is updated. The I / O processor contains a transformation table which is used to transform the virtual addresses of the block into the linear main memory address space. For this purpose, for example, the techniques known from the US book: Hwang, Advanced Computer Architecture, McGraw-Hill, 1993, pp. 198-203 can be used.

According to the state of the art, an inter NEN cache memory the successive data words via a correspondingly wider external data bus in parallel loaded and then sequentially into the memory bank word for word written. Due to the distribution of be in the main memory neighboring data words on several cache banks and the selected distribution function is described when using the benen invention also a parallel enrollment of several ge data words loaded together in the different cache benches possible, which significantly shortens the reloading process and thus leads to an increase in system performance. Correspond can also when writing back a virtual block  kes several consecutive in the physical address space Data words read in parallel from the cache banks and in parallel written to the main memory via the external data bus become.

Claims (4)

1. Method for controlling a cache memory unit for use in a parallel processor that has at least one group with N. M contains synchronized parallel processing units ( 10 ), with N and M as any power of 2, consisting of R. Q, with R = N + 1, Q = M + 1, individual memory banks ( 13 ), each with a large number of addressable word memories, which can be sent to the N via a memory crossbar ( 11 ). M processing units are connected and an I / O processor ( 14 ), which can load data from an external main memory into the cache memory unit or write it back, with the property that the addressing of the data in the processing units via virtual, at each a data structure bound and a group of N. M processing units are assigned two-dimensional address spaces, each containing this data structure and representing objects that are distinguished by a sequential number, followed and regular access of the processing units in the form of a matrix to the object is made possible, with address distances between the individual elements the size of any power of two in any dimension, and the data contained in the address spaces by a function of the form A _h mod R + R. (A _v mod Q) are distributed over the memory banks, with A _{h representing} the horizontal and A _v the vertical address component of the individual data words in the object address space, characterized in that each object is divided into virtual blocks ( 30 ) of size S _{VB, h} = R. 2 ^X in the horizontal direction and S _{VB, v} = Q. 2 ^{Y is divided} in the vertical direction, with X and Y being 0, 1, 2, 3. , , can be chosen arbitrarily, as well as the R. Q memory banks of the cache memory are each divided into a number of sets ( 40 ) N _MSet = S _{VB, v} div Q, with div as an integer division operation, which again consists of any number of physical blocks ( 41 ) of size S _MBlock = S _{VB , h} div R exist, and the data of each virtual block are assigned so that for each virtual block ( 30 ) exactly one physical block ( 41 ) per set ( 40 ) is occupied in each memory bank and each data word of a matrix access to an object in a set with the number a _mset = (a _v div Q) mod 2 ^Y and is within the physical block (41) to the relative address a _pblock = (a _h div R) mod 2 ^X, wherein the selection of Blocks within the set by a block replacement strategy depending on the block start address or block usage frequency. 2. The method according to claim 1, characterized in that depending on the tag register of the cache, the number of the object, the horizontal block address A _{VBT, h} = A _{BS, h} div S _{vB, h} and the vertical block address A _{VBT, v} = A _{BS , v} div S _{vB, v} contains, where A _{BS, h} , A _{BS, v} the beginning of the virtual block, ie the address components of the data word contained in the block and the smallest address components A _h , A _v all contained in the virtual block Owns data words. 3. The method according to claim 1 or 2, characterized in that the day registers are not assigned to the cache banks ( 13 ) but are integrated in the processing units ( 10 ), the number of day registers being the number of physical blocks ( 41 ) per set ( 40 ) corresponds. 4. The method according to claim 1, characterized in that the Distribution of data on R. Q memory banks for parallel Le Sending and writing the data from or into the caches memory blocks from in the main memory address space to neighboring ones Addressed data words during the block-wise trans He used data between main memory and cache becomes.