DE19536401B4 - Method and device for coding and decoding data - Google Patents

Abstract

A method of encoding a data stream comprising:
a) an incoming data stream is split into parallel data streams during encoding by an entropy coder and variable length codewords are output from the entropy coder, the codewords representing the shared data stream;
b) the output variable length codewords are ordered in an order noted at the beginning of each codeword; and
c) the ordered variable length codewords are transformed into fixed length codewords.

Description

The The invention relates to methods and apparatus for coding and Decoding of data and in particular concerns the field of data compression and decompression systems; about that In addition, the invention relates to a method and a device for parallel coding and decoding of data in compression / decompression systems.

nowadays will data compression in large Scope especially for storing and transferring large amounts of data used. The prior art discloses various data compression techniques which can be divided into two broad categories, namely one lossy and lossless coding. lossy Encoding closes coding, which results in the loss of information, so that it no guarantee for a perfect reconstruction of the original or original data gives. With lossless compression, all information is restored and the data is compressed in a way that is one perfect reconstruction permits.

at lossless compression will be entered symbols in output codewords implemented. If the compression is successful, the codewords in less bits than the number of symbols entered. lossless Coding methods include dictionary methods coding (e.g., Lempel-Ziv), a run-length coding, an enumerative Coding and entropy coding.

Entropy coding consists of a lossless coding method in which attempts are made , data close to the entropy boundary using known or estimated symbol probabilities to compress. Entropy codes contain Huffman codes, arithmetic Codes and binary Entropy codes. binary Entropy encoders are lossless encoders which are only binary (yes / no) Decisions often act as the most likely symbol (MPS) and the least probable symbol (LPS). example from binary Entropy encoders contain IBM's Q coder and a coder referred to as the B coder. (Regarding more Information about the B-coder See US Patent No. 5,272,447 A entitled "Method and Apparatus for Entropy Coding" (J.D. Allen), filed on December 21, 1993 by the assignee of the present invention. See also M.J. Gormisch and J.D. Allen, "Finite State Machine Binary Entropy Coding, "Abstract in proc. Data Compression Conference, March 30, 1993, Snowbird, UT, p.449). The B-coder is a binary entropy coder which used a finite automaton for compression.

33 shows a block diagram of a known compression and decompression system with a binary entropy coder. To encode data into a text model (CM) 101 which translates the inputted data into a set or sequence of binary decisions and creates a context bin for each decision. Both the sequence of binary decisions and their associated context fans are of the context model 101 to the probability rating or estimation (PE) module 102 issued. The PE module 102 gets each text box and generates a probability score for each binary decision. The actual probability score is usually represented by a class called a P-class. Each P-class is used for a probability range. The PE module 102 Also, determines whether or not the binary decision (the result) is in the more probable state (ie, whether the decision corresponds to the MPS). A bitstream generator (BG) module 103 receives the probability score (ie the P-class) and the determination of whether the binary decision is probable or not as inputs. Accordingly, the BG module generates 103 a compressed stream that outputs zero or more bits to represent the original input data.

The context model provides for coding 104 a context pocket on the PE module 105 , the probability class (P class) on the BG module 107 on the basis of the context. The BG module 106 is intended to accommodate the probability class. According to the probability class and the compressed data, the BG module returns 106 back to one bit representing whether the binary decision (ie the event) is in the most probable state. The PE module 105 receives the bit, updates the probability score based on the received bit, and passes the result to the context model 104 back. The context model 104 gets the returned bit and uses it to generate the original data and to update the context bin for the next binary decision.

A difficulty with decoders that use binary entropy codes, such as IBM's Q-coder and B coders are that they are slow, even if they are hardware-based. This mode of operation requires a single large slow feedback loop. To re-render the decoding process, the context model uses earlier decoded data to create a context. The probability evaluation module uses the context to generate a probability class. The bitstream generator uses the likelihood class and the compressed data to determine if the next bit is the likely or improbable result. The probabilistic evaluation module uses the probable / improbable result to generate a result bit (and to update the probability score for the context). The result bit is used by the context model to update the evolution of previous data. All of these steps are required to decode a single bit. Since the context model must wait for the result bit to update its evolution before it can create the next context, the decoding of the next bit must wait. It should be avoided to wait for the coupling loop to complete before decoding the next bit. In other words, more than one bit or one codeword should be decoded as much as possible at a particular time to increase the rate at which compressed data is decoded.

A There is further difficulty with decoder with binary entropy codes in that data is more variable Length processed Need to become. In most cases the code words to be coded have variable lengths. On the other hand, code other systems variable length symbols (uncoded data). at For processing variable length data, the data must be at a bit level be moved to the correct next data for the decoder or to create a coding operation. These bit level manipulations on the data stream require expensive and / or slow hardware and / or software. Furthermore, in conventional Systems made this move in time-critical feedback loops which are the efficiency limit the decoder. It would So be beneficial, the bit level manipulation of the data stream from time-critical feedback loops so that parallelism could be applied to to increase the speed.

US 5,272,478 A discloses a method and apparatus for entropy coding. A state machine is provided which has a plurality of states. Each state has at least one transition pair. Each element of the transition pair comprises zero or more bits which are representative of the compact code to be output and the identification of the next state to be advanced. The transition pair reflects the output of a "yes" and a "no" response related to the probability of the data being compressed and whether the data falls within that probability.

Out US 5,374,916 A is a process for the automatic electronic identification of data types known. This process identifies the data type of an input data stream and then, in response to the identified data type, selects at least one data compression method from a set of data compression methods that provides an optimal compression ratio for that particular data type. This maximizes the compression ratio for the input data stream. The data compression process may further change the rate of compression during data compression.

Out US 5,045,852 A For example, a dynamic model for selecting during data compression is known. At least two models expire and are compared, and the best coding performance model for a block of compressed data is selected.

Out US 3,394,352 a method for coded communication is known. The number of symbols to be carried is minimized and consequently the transmission time is reduced. For this the most efficient code is determined. For this purpose, the symbols are processed by a plurality of encoders and the coded representation of the symbols is counted in terms of the number of symbols.

task The invention is a method of encoding a data stream to provide a faster encoding of a data stream allowed, without the traditional transmission paths to modify. Furthermore, a corresponding coding system, decoding system, Encoder and decoder are created.

above Task is through the objects the claims 1, 8, 61, 70, 75, 86, 88, 92 and 105 solved. Further embodiments go out of the ordinary claims out.

Of the Encoder and the decoder of the invention generate a balanced, parallel entropy system, which is both a real-time encoding as well as real-time decoding in a cheap, very fast Hardware performs.

Consequently are methods and devices for decompressing and compressing created by data. An encoder has to be used in one Compression system a decoder for decoding by means of Encoder generated information. The encoder of the invention concludes a coder for generating codeword information accordingly Data. The encoder also includes a rearrangement unit, the one coded data stream corresponding to the codeword information generated by the coder. The rearrangement unit has a pass count rearrangement unit, around codewords in a decode order, and a bitpack unit on, to codewords variable length to join nested words of fixed length and around the interleaved fixed length words in one of the decoders to deliver the required order.

following the invention will be described with reference to preferred embodiments to the accompanying drawings described in detail. Show it:

1A a block diagram of a coding system according to the invention;

1B a block diagram of an embodiment of a coding system according to the invention;

1C a block diagram of one embodiment of the decoding system of the invention, which processes context boxes in parallel;

1D a block diagram of an embodiment of the decoding system of the invention, which processes probability classes in parallel;

2 a non-interlaced code stream of the invention;

3 an embodiment of the interleaved code stream derived, for example, from a data set;

4 an example of a probability evaluation table and a bitstream generator for the R-Coder of the invention;

5 a block diagram of an embodiment of an encoder of the invention;

6 a block diagram of an embodiment of a bit generator of the invention;

7 a block diagram of an embodiment of a rearrangement unit of the invention;

8th a block diagram of one embodiment of the pass count reordering unit of the invention;

9 a block diagram of another embodiment of a sequence counter reordering unit of the invention;

10 a block diagram of an embodiment of a bit packing unit of the invention;

11 a block diagram of one embodiment of a packaging logic of the invention;

12 a block diagram of a coding bit generator of the invention;

13A a block diagram of an embodiment of the decoding system of the invention;

13B a block diagram of a decoder of the invention;

13C a block diagram of an embodiment of the FIFO structure of the invention;

14A an embodiment of a decoding pipeline of the invention;

14B an embodiment of a decoder of the invention;

15A a block diagram of an embodiment of a sliding unit of the invention;

15B a block diagram of another embodiment of a sliding unit of the invention;

16 a block diagram of a system with an external context model;

17 a block diagram of another system with an external context model;

18 a block diagram of an embodiment of a decoder of the invention;

19 a block diagram of an embodiment of a decoder with separate bit generators;

20 a block diagram of an embodiment of a bit generator of the invention;

21 a block diagram of an embodiment of a long pass unit of the invention;

22 a block diagram of an embodiment of a short pass unit of the invention;

23 a block diagram of one embodiment of an initialization and control logic of the invention;

24 a block diagram of an embodiment of rearrangement data using a "snooper"encoder;

25 a block diagram of another embodiment of a rearrangement unit;

26 a block diagram of another embodiment of a reordering unit using a mixed queue (merged queue);

27 a block diagram of a large bandwidth system using the invention;

28 a block diagram of a bandwidth adjustment system using the invention;

29 a block diagram of a real-time video system according to the invention;

30 an embodiment of a memory for coded data of the invention;

31 a timing diagram of the decoding process of the invention;

32 a graph of encoder efficiency versus MPS probability of the invention, and

33 a block diagram of a conventional binary entropy coder and decoder.

Now discloses a method and apparatus for parallel coding and decoding data. In the following description a number of specific details are given, such as a special number of bits, a number of encoders, specific ones Probabilities, data types, etc., to get an accurate understanding of preferred embodiments to provide the invention. For the expert is of course that the present invention without these specific details in the Practice performed can be. Likewise, known circuits are in block diagram form not shown in detail in order not to complicate the understanding of the invention unnecessarily.

Some portions of the detailed description which follow are presented in the form of algorithms and symbolic representations of operations on data bits in a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the content of their work to others skilled in the art. One Algorithm is here and generally considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical processing of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, linked, compared, or otherwise processed. It has always proven to be beneficial, principally for reasons of common application, to these signals as bits of values, elements, symbols, characters, terms, numbers, or the like. to refer.

It However, it should be remembered that all these and similar Terms are assigned to the corresponding physical quantities and only convenient terms that are applied to these sizes. If it does not run specially will become apparent or otherwise evident from the following discussions throughout the invention explanations, use terms such as, "processing" or "calculating" or "calculating" or "determining" or "displaying" or similar, to which Function and processes of a computer system or similar electronic computing device, which data, which as physical, (electronic) sizes in the computer system registers and memories are displayed, edited and other data transformed, which in similar Way as physical quantities in the Computing system memories or registers or other such information storage transfer or display devices are shown.

The The invention also relates to a device for carrying out the Operations. This device can be designed specifically for the required purposes, or it may comprise a general-purpose computer that selectively through activates or reconfigures a program stored in the computer becomes. The algorithms and displays shown here are not specifically to a specific computer or other device based. Different general purpose computers can work with programs accordingly used herein or it may prove to be an even more specialized facility perform, to perform the various process steps. The required structure a variety of these devices will be apparent from the following description. In addition, will not related to the invention any special programming language. Much more can A variety of programming languages are used to teach the lessons of the invention as described below.

Parallel entropy coding

The Invention provides a parallel entropy coding system. The system comprises an encoder and a decoder. In one embodiment leads the Encoders encode data in real time. In similar Way leads in one embodiment the decoder of the invention decodes data in real time by. The real-time coder and the real-time decoder form together a balanced coding system.

The The invention provides a system which provides lossless coded data decoded in parallel. The data is decoded in parallel with help of several decoding resources. Each of the multiple decoding resources is Data (e.g., codewords) assigned from the data stream to be decoded. The assignment of the Data stream occurs on the fly, with the decoding resources Simultaneously decode data to thereby parallel the data stream to decode. To allow data mapping in a way which enables efficient use of the decoding resources becomes the data stream orderly. This is called parallel processing of the data stream. The ordering of data allows, that each Decoding resource decodes any or all encoded data, without on a feedback to wait for the context model.

In 1A For example, a decoding system of the invention is shown without the conventional slow feedback loop. An input buffer 204 receives coded data (ie, code words) and a feedback signal from a decoder 205 and provides encoded data in a predetermined order (eg, context-bin order) to the decoder 205 of the invention which decodes the encoded data. The decoder 205 contains several decoders (z, .B. 205A . 205B . 205C , etc).

In one embodiment, each of the decoders provides 205A . 205B . 205C , etc. Data for a group of contexts. Each of the decoders in the decoder 205 returns encoded data for each context bin in its group of contexts from an input buffer 204 out. With the help of these data, each decoder generates 205A . 205B . 205C etc. the decoded data for each group of context fans. The context model is not required to map encoded data to a particular group of context fans.

The decoded data is received from the decoder 205 to a memory 207 for decoded data (eg 207A . 207B . 207C , etc.). This can be the memory 207 Store intermediate data that is neither coded nor uncoded data, such as run counts. In this case, the memory stores 207 Data in a compact, but not entropy-coded form.

An independently working context model 206 is provided to the previously decoded data from the memory 207 (ie 207A . 207B . 207C , etc.) in accordance with a feedback signal which it sends to the memory 207 emits. As a result, there are two independent feedback loops, one between the decoder 205 and the buffer 204 and a second between the context model 206 and the memory 207 , Since the large feedback loop is eliminated, the decoders are in the encoder 205 (eg 205A . 205B . 205C , etc) are able to decode their associated codewords as they come from the buffer 205 be received.

The Context model creates the memory part of the coding system and splits a record (e.g., a picture) of different categories (e.g. Context subjects) based on the memory up. In the invention, the context fans are called independently ordered records considered. In one embodiment has every group of context fans their own probability rating model and each context box has its own state (being probability assessment models to be shared). Therefore, every context box could be one another probability assessment model and / or use another bitstream generator. Consequently are the data is ordered or processed in parallel, and data from the Data streams are associated with the individual encoders for encoding.

Parallelism the classic Add entropy coding model

In order to arrange the data stream in parallel, the data may be divided according to a context, a probability, a tiling, a codeword sequence (based on codewords), etc. Reordering the encoded data stream, regardless of parallelism, is one method used to arrange data or probability in parallel in another point. A parallel coder portion of an encoding system of the invention to which data has been supplied that has been differentiated by a context model (CM) is shown in FIG 1B shown.

In 1B the context-dependent parallel encoding part has a context model (CM) 214 , Probability Assessment Modules (PEMs) 215 to 217 and bitstream generators (BGs) 218 to 220 on. The context model 214 is intended to receive coded input data and is also compatible with the PE modules 215 to 217 connected, in turn, with bitstream generators 218 to 220 are connected, which code streams 1, 2 and 3 deliver. Each PEM and BG pair has a coder. Therefore, the parallel encoder is shown with three coders. Although only three parallel coders are shown, any number of coders may be used.

The context model 214 splits a data stream into different contexts in the same way as a conventional context model and delivers the multiple streams to the parallel hardware encoding resources. Individual contexts or groups of contexts are based on separate Probability Assessors (PEMs) 215 to 217 and bit generators (BGs) 218 to 220 directed, each emit a coded stream.

1C Fig. 10 is a block diagram of one embodiment of the decoding portion of the decoding system of the invention. In 1C is a context-dependent parallel decoder with BGs 221 to 223 , PEMs 224 to 226 and a CM 227 shown. Code streams 1 to 3 are BGs 221 to 223 connected, which also with PEMs 224 to 226 are connected. The PEMs 224 to 226 are also with the CM 227 connected, which outputs the reconstructed input data. The input comes from several code streams, which are shown as code streams 1 to 3. A code stream is assigned to each PEM and BG. Each of the bitstream generators (BG) 221 to 223 returns a bit representing whether the binary decision is in a more probable state than the PEMs 224 to 226 to return decoded bits (eg the binary decision). Each of the PEMs 224 to 226 is one of the BGs 221 to 223 which indicates which code to use to generate a data stream from the input code stream. The CM 227 generates a decoded data stream to select the decoded bits from the data stream generators in the correct order to thereby regenerate the original data. Consequently, the CM gets 227 the decompressed data bit from the corresponding PEM and BG which actually reorder the data into the original order. The controller for this embodiment flows in the reverse direction of the data stream. The BG and PEM can decode data before using the CM 227 needed, and one or more bits in advance. On the other hand, the CM 227 request (but not receive) one bit from a BG and a PEM and then request one or more bits from other BGs and PEMs before using the initially requested bit.

In the 1C The configuration shown is designed to tightly couple the PEM and the BG. The IBM Q encoder is a good example of a coder with a tightly coupled PEM and BG. Local feedback loops between these two components are not a fundamental limitation in system design. In another interpretation, the PEM could differentiate the data and deliver it to parallel BG units. Consequently, it would only be a CM and PEM, and the BG will be divided. Adaptive Huffman coding and finite state machine coding could be used in this way.

A similar decoding system that uses the PEM to differentiate the data and send it to parallel BGs is in FIG 1D shown. In this case, probability classes are handled in parallel and each bitstream generator is associated with a specific probability class and is aware of the result. In 1D are the coded data streams 1 to 3 to one of several bit stream generators (eg BG 232 . 233 . 234 , etc.), which are connected to receive them. Each of the bitstream generators is connected to the PEM 235 connected, in turn, with the CM 236 connected is. In this configuration, each of the bit stream generators decodes coded data, and the decoding results are received from the PEM 235 (instead of the CM 236 ). Each of the bit stream generators receives coded data from a source associated with a probability class (ie, where the coded data may be from any context box). The PEM 235 selects the bitstream generators using a likelihood class. The likelihood class is dictated by the context box provided by the CM 236 is provided. In this way, decoded data is generated by processing probability classes in parallel.

It There are numerous designs from the parallel coding systems of the invention. In one embodiment can the coded data streams, the several context fans to be nested in a stream which passes through the requirements of the different coders is ordered. In a embodiment According to the invention, the coded data are arranged so that each Coder constantly although the encoded data is supplied to the decoder fed in a stream become. The present invention works with all data types, including Image data.

With Help small simple coders that are inexpensive in integrated Circuits can be subdivided, can be coded Data decoded quickly in parallel. In one embodiment are the encoders in hardware using Field Programmable Gate Array (FPGA) chips or with the help of an application specific integrated circuit (ASIC) chip executed. The combination of parallelism and simple bitstream generators allows the decoding of coded Data at speeds exceeding those of conventional Decoder lie, the compression efficiency of the conventional Decoding systems is maintained or exceeded.

Channel ordering of several streams

There are many execution results and problems that affect system execution. Some of these are mentioned below. However, use the in 1B and 1C (and 1D ) illustrated embodiments, the multiple code streams. Systems with parallel channels that could be adapted to this embodiment are conceivable: multiple telephone lines, multiple heads from a disk unit, etc. In some applications, only one channel is available or suitable. Instead, if multiple channels are required, there may be poor bandwidth utilization due to the particular nature of the individual code streams.

In one embodiment, the code streams are concentrated and output contiguously to the decoder. A divider header contains pointers to the initial bit location of each stream. 2 represents an embodiment of the arrangement of this data. In 2 show three pointers 301 to 303 the output location in the lumped code of code streams 1, 2 and 3, respectively. The complete, compressed data file is available in a buffer at the decoder. If necessary, the codewords are retrieved from the correct location via the correct pointer. The pointer is then updated to the next codeword in this codestream.

This method requires a whole encoded frame to be used in the decoder and for practical purposes Purpose in the encoder is to save. If a real-time system or less bursty data flow is required, then two frame buffers may be used for banking both at the encoder and at the decoder.

Data order regarding codeword order

One Decoder decodes codewords in a given deterministic order. In parallel Encoding is the order of the code stream requests deterministic. Consequently, if enough the codewords of parallel code streams be nested in the correct order on the encoder, a single code stream. The codewords are then sent to the decoder in the same order on a just-in-time basis. On the decoder determines Model the decoder the codeword order and pack the codewords into a single stream. This model can be a current decoder be.

A Difficulty in handing over The data to the parallel decoding elements is obtained when data variable lengths to have. Removing a stream of variable length codewords requires one Bit shift unit to the codewords align. Bit shift units are often expensive and / or slow, when running in hardware are. The control of the bit shift unit depends on the size of the particular one Codewords off. This control of a feedback loop prevents the existence Move variable lengths done quickly becomes. The effectiveness, multiple decoders a single stream supply, can not be realized if the process fails to grab the current is performed in a single bit shift unit that is not fast is enough to supply the multiple decoders.

at the solution, which is offered in the invention, the problem is coded Distribute data to the parallel encoders, from the alignment the codewords variable lengths for a Decoding separated. The codewords in each independent Data streams are packed into words of fixed length, so-called nested ones Words. At the decoder end of the channel, these can be nested Words on the parallel decoder units using fast-acting, hard-wired data lines and a simple control circuit be distributed.

It is convenient to have a nested word length greater than the maximum word length so that at least enough bits to complete a codeword are included in each nested word. The nested words may then contain many codewords and parts of codewords. 3 illustrates, by way of example, the nesting of a set of parallel code streams.

These words are nested according to the request to the decoder. Each independent decoder gets a whole nested word. The bit shift operation is now performed locally on each decoder, thereby maintaining the system's parallelism. In 3 is the first codeword in each interleaved word, the lowest remaining codeword in the set. For example, the first interleaved words come from a code stream 1 which starts with the lowest codeword (ie, # 1). This is followed by the first interleaved word in code stream 2 and then the first interleaved word in code stream 3. However, the next low codeword that is not completely contained in an already ordered interleaved word is # 7. Consequently, the next word is in the Stream the second interleaved word of the code stream 2.

In another order is based on the order in which the latter Set of nested words (e.g., the codeword starting with codeword # 8 in stream 1, the Codeword starting with # 7 in stream 2, the codeword with code # 11 begins in stream 3) is inserted into the interleaved code stream are nested, on the first codeword of the previous sentence words (e.g., the codeword beginning with codeword # 1 in stream 1, the codeword starting with codeword # 2 in stream 2, the codeword, that begins with the codeword # 4 in stream 3) and they are from the nested word out in the first codeword with the lowest Number up to the nested word with the first codeword with the highest number orderly. Consequently, in this case, since the nested word, that begins with the codeword # 1, the first was, the next one nested Word in stream 1 the first of the second group of nested words, which are to be inserted into the nested stream, whereupon the next nested Word in the stream 2 and the next nested word in stream 3 follows. After the second group nested words inserted into the nested stream, that would be next nested word in stream 2 will be the next nested word which has been inserted into the stream since the codeword # 7 is the lowest The codeword of the second set of nested words is (what the codeword # 8 in stream 1 and then codeword # 11 in stream 3 follows).

The Use the current decoder as the model for the data stream is responsible for the execution choice and delay, to generate the interleaved stream. There are no results huge costs for Duplex systems that have both encoders and decoders. This can be different on every parallel set of data words Length (or different size) generalized be processed in one of the deterministic order become.

Code types and bitstream generators for parallel decoding

at of the invention existing encoders, such as Q-coder or B-coder, as the bit-stream generating elements be used, which are arranged in parallel. However, too other codes and encoders are used. The encoders and theirs associated codes used in the present invention are simple encoders.

at The invention provides for using a bitstream generator with a simple code instead of a complex code, like the arithmetic Code used by the Q-coder or the codes with multiple states, those from the B coder have been used, benefits. A simple code is advantageous because the hardware execution much faster and easier, and requires less silicon as a complex code.

One Another advantage of the invention is that the coding efficiency improves can be. A code which is a finite set of state information can not faultlessly set the Shannon entropy limit for each probability to meet. Known hardware executing codes in which a single bitstream generator multiple probabilities or contexts can handle, have restrictions, which reduce the coding efficiency. Fixing the restrictions the for several contexts or probability classes are necessary, allows using codes that are closer approach the Shannon entropy threshold.

R-codes

Of the Code (and encoder) used in one embodiment of the invention is, is called R-code. R codes are adaptive codes that a changeable one Convert number of identical input symbols into a codeword. In one embodiment the R-codes are parameterized so that many different probabilities can be treated with a single decoder design. Furthermore can the R codes of the invention by a simple very fast hardware be decoded.

In the invention, the R codes are used by an R-coder to perform coding or decoding. In one embodiment, an R-coder is a bitstream generator combined with a probability weighting module. For example, in 33 an R-encoder is the combination of a probability weighting module 102 and a bitstream generator 103 and the combination of a probability rating module 105 with a bitstream generator 106 contain.

Put codewords runs the most likely symbol (MPS). An MPS produces the result a binary one Decision with more than 50% probability. On the other hand The least probable symbol (LPS) represents the result a binary one Decision with less than 50% probability. If two Results are equally likely, it does not matter which one with MPS or LPS, as long as both the encoder and also the decoder to make the same name. The resulting Bit sequence in the compressed file is in Table 1 for one given parameters, referred to as MAXRUN is.

Table - Biter Generation Coding

To encode, the number of MPSs in a run is counted by a simple counter. If this count equals the MAXRUN count, a 0 codeword is output to the code stream and the counter is reset. If an LPS is encountered, then a 1 followed by bits N which uniquely describe the number of MPS symbols before the LPS is injected into the code stream. (There are many ways to allocate the N bits to describe the pass length.) Again, the counter is reset. The number of bits required for N depends on the value of MAXRUN. One's (1's) complement of the codewords could also be used.

Around to decode when the first bit in the code stream is 0, the Value of MAXRUN in the MPS counter and the LPS indicator is cleared. Then the 0 bit is thrown away. If the first bit is a 1, then the following bits are checked to get the Extract bits N, and the corresponding count (N) is set in the MPS counter, and the LPS indicator is set. Then the code stream bits, which contain the 1N codeword, thrown away.

R codes are generated according to the specifications in Table 1. The definition of a given R code Rx (k) is defined by MAX-RUN, for example:
MAXRUN for Rx (k) = x * 2k ^-1
consequently:
MAXRUN for R2 (k) = 2 · 2 ^k-1
MAXRUN for R3 (k) = 3 x 2 ^k-1
etc...

R codes are a subset of Golomb codes. Note that Rice codes use only R2 (•) codes. The R codes of the invention allow the use of both R2 (k) and R3 (k) codes and, if necessary, other Rn (k) codes. In one embodiment, R2 (k) and R3 (k) are used. Rn exists for n = 2 and n is equal to an odd number (eg, R2, R3, R5, R7, R9, R11, R13, R15). In one embodiment, for the R2 (k) code, the pass count r is encoded in N; the pass count r is written in k bits so that 1N is represented with (k + 1) bits. Similarly, in one embodiment, for an R3 (k) code, bits N may contain 1Bit to indicate whether n <2 ^(k-1) or n≥2 ^(k-1) , and either (k-1) or k bits to indicate the pass count r, so that the variable N is represented by a total of k and (k + 1) bits, respectively. In other embodiments, the 1's complement of N could be used in the codeword. In this case, the MPS aims to "generate code streams with many 0's or LPS aims to generate code streams with many 1's.

tables FIGS. 2-5 illustrate some efficient R codes that are used in a embodiment of the invention have been used. It should be noted that others Run-length code can also be used in the invention. An example of an alternative Run-length code for R2 (2) is shown in Table 6. Tables 7 and 8 show examples of the codes, in one embodiment have been used.

Table 8 - Another Alternative R2 (2) Code

Probability assessment model for R codes

In one embodiment, the R2 (0) code does not encode: an input of 0 is encoded into a 0, and an input of 1 is encoded into a 1 (or vice versa), and is optimally equal to 50% for probabilities. The R2 (1) code of the preferred embodiment is optimal for probabilities close to 0.707 (ie 70.7%), and the R3 (1) code is optimal for the 0.794 probability (79.4%). The R2 (2) code is optimal for the 0.841 probability (84.1%). Table 7 illustrates the near optimal runlength code, where the likelihood offset is determined by the following equation:
Probability Offset = -log ₂ (LPS) Table 9

The Codes are nearly optimal, so that the probability range, as by the probability offset is displayed, the space is covered relatively evenly, even if the optimal probabilities are not that much in the higher one k values differ as in the low k values.

Now, reference is made to the probability that an R code is optimal. In fact, only R2 (2) hits the entropy curve. A real consideration shows for which probability range a very specific R-code is better than all R-codes in a given class. The following tables provide the probability ranges for the class of R2 codes and for the class of R2 and R3 codes.

For the class For R2 codes from 0 to 12, the ranges in Table 10 below apply. For example, if only R2 codes are used then R2 (0) is the best if 0.50 ≤ probability ≤ 0.6180. Similarly, R2 (1) is the best if 0.6180 ≤ Probability ≤ 0.7862.

Table 10 - R2 codes from 0 to 12

For the class of R2 and R3 codes are the solutions in Table 11 below. For example, if R2 and R3 codes R2 (1) is the best, if: 0.6180 ≤ Probability ≤ 0.7549.

Table 11 - R2 and R3 codes are lengths less than or equal to 13 bits

One R2 (k) for a fixed k becomes a track length code called. However, a fixed k is only the best for a probability range. It should be noted that, when encoded near an optimal probability, an R-code according to the invention a 0 and 1N codewords used with approximately the same frequency.

With in other words, in one half In time, the R-coder of the invention outputs a code, and in the other half In time, the R-coder outputs the other code. By checking the Number of 0 and 1N codewords A statement can be made as to whether to use the best code is. That is, if too many 1N codewords are output, then the passage length becomes too long; on the other hand, when too many 0 codewords output, the run length too short.

The Probability rating model used by Langdon has been tested the first bit of each codeword to determine if the source probability is above or below the current estimate (See G. G. Langdon, "An Adaptive Run-Length Coding Algorithm ", IBM Technical Disclosure Bulletin, Vol. 26, No. 7B, December 1983). Based on this finding, k is increased or decreased. If, for example A code word indicating MPS is considered to be the Probability Estimate low. Therefore, according to Langdon k around 1 for every 0 codewords increased. If a codeword that reads less than MAXRUN MPS indicates what LPS (e.g., 1N codeword) is seen, is the Probability Estimate too high. Consequently, according to Langdon k around 1 for every 1N codeword is lowered.

The The present invention leaves a more complex probability rating to than simply increasing or Decrease k by 1 for each codeword. The invention includes a Probability score module state which is the one to use Code sets. Many states can use the same code. Codes become states using a state table assigned.

In an embodiment of the invention changes the probability estimate of each delivered codeword. consequently elevated or the probability score module lowers the probability estimate dependent on whether a codeword starts with a 0 or a 1. If, for example a "0" code word is output becomes, it comes to an increase the estimate of the MPS probability. However, if a "1" code word is output, the Estimates of the MPS probability lowered.

The well-known Langdon coder used only R2 (k) codes and increased or decreased k for each codeword. By contrast, the invention uses R2 (k) and R3 (k) codes in conjunction with the state table to match the adaptation rate to the application. That is, if it is a small amount of stationary data, the adaptation must be faster to result in optimal coding, and if there is a larger amount of stationary data, the adaptation time may be longer so that the coding can be chosen to to achieve better compression in the rest of the data. Where a variable number of state changes may occur, specific application characteristics may also affect the rate of adaptation. Because of the nature of the R codes, the rating for R codes is simple and requires little hardware while being very powerful. In 32 this is illustrated by a graph in which the coding efficiency (the code length, as registered with respect to entropy) is plotted against an MPS probability. 32 Figure 4 shows how some of the R codes of the invention cover the probability space. As an example shows 32 in that for an MPS probability of approximately 0.55, the efficiency of the R2 (0) code is 1.01 of the entropy limit (or 1% worse than this). In contrast, the R2 (1) code has an efficiency of 1.09 of the entropy limit (or 9% worse than this). This example shows that using the wrong code for this particular low probability case causes a loss of 8% in coding efficiency.

The incorporation of the R3 (k) codes makes it possible to cover more probability space with a greater efficiency. An example of a probability evaluation status bar according to the invention is shown in FIG 5 shown. The table in 5 shows both a state counter and the code associated with each of the separate states of the table. The table contains both positive and negative states. The table has 37 positive states and 37 negative states, including zero states. The negative states mean another MPS than the negative states. In one embodiment, the negative states may be used when MPS is 1, and the positive states may be used when MPS is 0 or vice versa. In the 5 The table shown is just an example; other tables may have more or fewer states and a different state mapping.

At first the encoder is in state 0 which is the R2 (0) code (i.e., no code) for the Probability Estimate is equal to 0.50. After each codeword is processed, the state counter in dependence is incremented or decremented by the first bit of the codeword. In a embodiment elevated a code word of 0 the size of the memory. Therefore, a change in the state is added by each codeword the state counter performed. In other words, the probability score module changes that Status. However, you can successive states be assigned to the same code. In this case, the probability rating without a change reached by codes at each codeword. In other words, the condition is for each codeword changed; however, at certain times, the condition becomes the same probabilities displayed. For example, all states 5 to -5 use the R2 (0) code, while the conditions 6 to 11 and -6 to -11 Use the R2 (1) code. With the help of the state table of the invention can do a probability assessment in a nonlinear way stay with the same encoder.

It should also be noted that more states are included with the same low-likelihood R-code, because the loss of efficiency when the wrong code is used at low probabilities is large. The type of runlength code state table is to transmit between states after each codeword. In a state table designed to change codes with each state change when switching between states at the low probabilities, the code switches between a code which is very close to the entropy efficiency limit and a code which is far is away from the entropy efficiency limit. Consequently, a disadvantage (in the form of the number of coded data bits) in the transition between Zu staged. Conventional probability assessment modules, such as the Langdon Probability Assessment Module, lose their effectiveness because of this disadvantage.

In the run length codes higher Probability is the downside to the wrong code not so great. Thus, in the invention, additional states become added lower probabilities, so that the changes in the waver between the two correct codes are raised, whereby the coding inadequacy becomes smaller.

In certain embodiments The encoder may have an initial one Have probability rating state. In other words, the coders could in a predetermined state, for example state 18, kick off. In one embodiment could another state table can be used so that some conditions for the few first symbols would be used for a quick adaptation admit, and a second state table could be for the remaining symbols for one slow adaptation can be used to fine-tune the probability score to enable. On this way, the encoder can be able to get a more effective code earlier to use in the encoding process. In another embodiment could the code stream is an initial one Probability estimate for specify each context. In one embodiment, the increments or decrements not according to one fixed number (e.g., 1). Instead, the probability assessment state through a changeable Number according to the amount of data already encountered or the change in the data (their stability) be incremented. Examples of such tables are in Tables 21 to 25 described below.

If the state table is symmetrical, as the example table of 4 shows that only half of it (including the zero state) needs to be saved or executed in hardware. In one embodiment, the state number is stored in a sign magnitude (one's) complement form to take advantage of the symmetry. In this way, the table can be used by taking the absolute value of the ones complement number to determine the state and to verify the sign, thereby determining whether MPS is a 1 or a 0. This allows for the hardware needed to increment and decrement the state to be reduced, since the absolute value of the state is used to index the table, and computing the absolute value of ones complement number is trivial. In another embodiment, with respect to greater hardware efficiency, a state table may be replaced by a hardwired or programmable state device. A hardwired state to encode a converter is an implementation of the state table.

Overview of the balanced parallel Entropy coding

The The invention provides a balanced parallel entropy coding system which Both real-time encoding and real-time decoding include what been done in a very fast / inexpensive hardware is. The present invention can be found in many lossless Encoding applications, including real-time compression / decompression data on recordable optical disks or magnetic disks, Real-time compression / decompression of computer network data, a Real-time compression / decompression of image data in a compressed Frame memory in a multifunction device (e.g., copier, facsimile machine, scanner, Printer, etc.) and real-time compression / decompression of sound data; however, the invention is not limited thereto.

One Specifying the performance of the encoder requires some Attention. It's easy to design a coder that has a certain rate for the originals Data is obtained in a sufficiently fast coded data channel are entered. In many applications, however, it is the goal at the encoder, to efficiently use the coded data channel. An encoded data channel usage is determined by the maximum burst rate of the original data interface, by the encoding speed and narrowed the compression achieved on the data. The effect of this Effects must about some taken into account local data volumes which depends on the buffering in the encoder. It is desirable to have an encoder that efficiently processes the encoded data channel uses while the coding speed and high compression is maintained and the maximum burst rate is still set.

in the Next, the encoder of the invention will be described. A decoder, which can be used in conjunction with the encoder is also described.

Real-time encoding at of the present invention

5 Figure 4 is a block diagram of the coding system of the invention. In one embodiment, the encoder of the invention performs real-time coding. In 5 closes the coding system 600 an encoder 602 one containing a context (CM) and state memory 603 connected to coded information in the form of codeword information 604 according to the original data 601 to create. A codeword information 604 creates a rearrangement unit 606 in cooperation with a reordering memory 607 , a coded data stream 608 , Here is the coding system 600 is not limited to working with codewords, and in other embodiments may operate on discrete analog waveforms, variable-length bit patterns, channel symbols, alphabets, events, etc. within the teachings of the invention.

The encoder 602 includes a context model (CM), a probability estimator (PEM), and a bitstream generator (BG). The context model and the probability evaluator (PEM) in the encoder 602 are essentially identical to the corresponding units in the decoder (except for the direction of the data flow). The bit generator of the coder 602 corresponds to the decoder bit generator and will be described below. The result of coding by means of the encoder 602 is the output in the form of zero or more bits representing the original data. In one embodiment, the output of the bitstream generator also includes one or more control signals. These control signals provide a control path to the data in the bit stream. In one embodiment, the codeword information may include a scroll indicator start, an end of a scroll indicator, a codeword, and an index that identifies the pass count (which is from the context or probability class) for the codeword. An embodiment of the bit generator of the invention will be described below.

The rearrangement unit 606 picks up the bits and control signals from the bitstream generator (if any) of the decoder 602 have been generated and generates coded data. In one embodiment, the encoded data is from the rearrangement unit 606 a stream of nested words. One embodiment carries the rearrangement unit 606 performs two functions, namely, moves codewords from the end of iterations generated by the coder to the beginning of sweeps, if necessary by the decoder, and combines codewords of variable length with interleaved words of fixed length and outputs them in the correct order required by the decoder.

The rearrangement unit 606 temporarily uses a reordering memory 607 , In an embodiment in which coding is performed at a workstation, the reordering memory may 607 over 100 megabytes in size. In the balanced system of the invention, the reordering memory is 607 much smaller (eg approximately 1 Kbyte) and fixed. Thus, in one embodiment, real-time encoding is performed using a fixed-size memory, even if this increases the memory required by the decoder or increases the bit rate (for example, if an output is made before the completion of a run). The decoder of the invention is capable of determining the effects of the reordering unit's limited memory by means of, for example, implicit, explicit or current signaling (as will be described below). The rearrangement unit 606 has a finite memory available for reordering; however, the "needed" memory is not bound. Both the effect of a finite memory for a trailing end to the beginning of a traversal queue and for reordering nested words must be considered.

In an embodiment does that Coding system (and the corresponding decoding system) of the invention encoding (or decoding) using a single integrated Circuit chips through. In another embodiment, a contains single integrated circuit, the coding system of the invention, including its Encoder, decoder and memory. A separate external memory can be added to support coding. A multichip module or an integrated circuit can include both the encoding / decoding hardware and the memory.

With The coding system of the invention may attempt to reduce the effective Increase bandwidth by up to a factor of N When the compression reached is less than N: 1, then the coded data channel is fully exploited, however, the achieved effective bandwidth increase is only equal the compression rate. If the compression achieved is greater than N: 1, then the effective bandwidth is reached, with a additional bandwidth is writable. In both cases must the reached compression over a local one Area of the data, which by the present in the coding system Buffer value is set.

The bit generator for the encoder the invention

6 shows an embodiment of the encoder bit generator of the invention. The bit generator 701 is intended to receive a probability class and an uncoded bit (eg, an MPS or LPS display) as inputs. The bit generator gives according to the input signals 701 several signals. Two of the output signals are control signals indicating the start of the start and the end of a pass (each codeword representing a pass), a start signal 711 or a final signal 712 represent. It is possible to start and stop a run at the same time. When a pass starts or ends, it has an "index" output signal 713 an indication of the probability class (or context) for the uncoded bit. In one embodiment, an index output signal 713 a combination of the probability class for the bit and bank identification for systems in which each probability class is replicated in multiple memory banks. A codeword output 714 is used to get a codeword from the bit generator 701 spend when a passage ends.

A store 702 is with the bit generator 701 and contains the pass count for a given probability class. During a bit generation the bit generator reads 701 from the store 702 with the help of the index (eg the probability class). After reading the memory 702 performs the bit generator 701 a biter production in the following manner. First, when the sweep count is zero, a start signal 711 asserted to indicate the start of a pass. If the uncoded bit is equal to the LPS, then the end signal will be 712 asserted to indicate the end of the run. If the uncoded bit is equal to an LPS, the codeword output becomes 714 is set to indicate that the codeword is a 1N codeword, and the pass count is cleared, eg set to zero (since it is the end of the pass). If the uncoded bit is not equal to the LPS, then the pass count is incremented and a check is made if the pass count equals the maximum count for the code. If so, the end signal becomes 712 asserted the codeword output 714 is set to zero and the pass count is cleared (eg the count is set to zero). If the test determines that the pass count is not equal to the maximum for the code, then the pass count is incremented. The index signal 713 represents the likelihood class that has been obtained as an input signal.

In the invention, the generation of 1N codewords is performed so that their length can be determined without additional information. Table 12 illustrates 1N codeword representations of R3 (2) codewords for the decoder and encoder. The decoder expects the "1" bit in a "1N" codeword to be the least significant bit (LSB) and the "N" count portion to be in the proper MSB ... LSB order. In the decoder, the variable length codeword can not be distinguished from zero padding without knowing which particular code is being used. In the coder, the codeword is reversed and the position of the most significant "1" bit indicates the length of "1N" codewords , In order to generate codewords in an encoder row in sequence, the complement of the count must be reversed. This can be achieved by reversing the 13-bit count and shifting it to align with the LSB. As will be described in detail below, the bit packing unit reverses the codewords in the decoder order. However, this reversal of codewords does not increase the complexity of the bitpack unit 606 because she has to somehow perform a push.

Table 12 - "" 2N "codeword representations for R3 (2) codewords

For R3 codes also requires generating "N" codewords that this Bit following the "1" indicates whether a short or a long count is present.

By Using multiple memory banks allows the invention is a pipelining. For example, in case of one Multi-port memory a read operation for a memory for an uncoded bit before while a read operation on the memory for the previous uncoded Bit occurs.

An Altera AHDL scan design

A embodiment The encoder bit generator of the invention has an FPGA. The Execution treated all R2 and R3 codes up to R2 (12). The AHDL (Altera Hardware Description Voice) source code is listed below.

The design has several parts, as in 12 is shown. First is "ENCBG" 1301 the bulk of the design having the logic to handle the start, finish, and continuation of passes. Second, "KEXPAND" 1302 is used to extend the probability class to the maximum run length, a variable length mask, and the length of the first long code word for R3 codes. "KEXPAND" 1303 is identical to the decoder function with the same name. Third, the "LPSCW" takes 1304 takes part in a count value and information about the probability class in the form of input values and generates the correct "1N" codeword.

The execution uses two pipeline stages. During the first pipeline stage the count is incremented, the probability class is extended, and a subtraction and a comparison for long R3 codewords is carried out. The rest Operations are during the second pipeline stage.

The rearrangement unit the invention

7 Figure 13 is a block diagram of one embodiment of the rearrangement unit. In 8th the rearrangement unit 6 has a passage count rearrangement unit 801 and a bit packing unit 802 on. The rearrangement unit 801 moves codewords from the end of sweeps, as generated by the coder, to the beginning of sweeps, as needed by the decoder, while the bit packing unit 802 Combining variable-length codewords in interleaved fixed-length words and output them in the correct order required by the decoder.

A "snooper" decoder can used to rearrange a decoder, a decoder is contained in the encoder and creates requests for data in an order in which the codewords are needed for the actual decoder. To support a "Snooper" decoder, you can a reordering of pass counts independently for each Electricity performed become. For Decoders that can be easily modeled can have multiple timestamps (time stamped) Snakes or a single merging queue used to allow reordering. In one embodiment can rearrange each codeword using a serpentine data structure be achieved and is independent by using multiple encoded data streams. As the reordering performed will be described below.

The first shuffling operation performed in the encoder is to re-order each of the pass values so that the pass value is specified at the beginning of the pass (if the decoder for a Decoding is necessary). This reordering is required because the encoder can not determine until the end of a run, what a pass count (and a codeword) is. Consequently, the resulting pass count, which has been generated in the coding, rearranged so that the decoder in capable of the pass counts back to correctly decode into the data stream.

In 7 has the rearrangement unit 606 of the invention, a pass counter reordering unit 801 and a bit packing unit 802 on. The rearrangement unit 804 is provided to receive a plurality of input signals, which is a start signal 711 , a final signal 712 , an index signal 713 and a codeword 714 contain. These signals will be described in detail in connection with the pass count shuffling unit 8th described. The rearrangement unit generates according to the input signals 801 a codeword 803 and a signal 804 , The signal 804 indicates when to reset the count-through value. The codeword 803 is from the bitpacking unit 802 added. According to the code word 803 generates the bitpacking unit 802 nested words 805 , The rearrangement unit 801 and the bitpacking unit 802 will be described later in detail.

Pass count shuffling

As described above the decoder codewords at the time when the beginning of the data by the codeword coded, is needed. However, the encoder does not know the identity of the codeword to the end of the data encoded by the codeword have been.

A block diagram of one embodiment of the pass count shuffling unit 801 is determined by 8th described. The embodiment described adapts to four interleaved streams, each interleaved word 16 Bits, and the codewords vary in length from 1 to 13 bits. In such a case, the rearrangement unit 300 in the pipeline system to handle all streams. Further, an encoder which assigns pass classes to probability classes is used so that the maximum number of pass counts that can be active at any one time is small, and it becomes in this embodiment accepted at 25. The invention is not limited to four interleaved streams, interleaved 16-bit words or codeword lengths of 1 to 13 bits and may be used for more or fewer interlaced streams of more or less than 16 bits and for codeword lengths different from 1 bit to more than 13 bits.

In 8th is a pointer counter 901 provided to an index input signal 713 and generates an address output signal which is connected to an input of a multiplexer (MUX). 902 connected is. Two more inputs of the MUX 902 are intended to provide an address in the form of a header pointer from a header counter 903 and an address in the form of a tail pointer from a tracking counter 905 take. The output signal of the MUX 902 is an address used to access a codeword memory 908 is used.

An index input signal 713 is also as an input to the mux 905 intended. Another entrance of the MUX 905 is to the codeword input signal 719 coupled. The output of the MUX 905 is with an input of a validity module 906 and a data bus 907 connected. The data bus 907 is with a codeword memory 908 and an input of the MUX 905 connected. Likewise with the data bus 907 an output of a control module 909 connected. A start input signal 711 and an end input signal 712 are provided to inputs to the control module 909 to separate. The output signals of the validity module 906 have the codeword output 803 and the signal 809 on ( 7 ). The rearrangement unit 801 also has control logic (which is not shown so as not to obscure the invention) about the operations of the various components of the rearrangement unit 801 to coordinate.

To repeat, an index input signal 713 identifies a pass. In one embodiment, the index indicates one of 25 probability classes. In such a case, five bits are needed to represent the index. If multiple banks of probability classes are used then additional bits may be required to specify the particular arrangement. In one embodiment, the index input signal identifies the likelihood class for the pass count. A codeword input signal 714 is the codeword when the end of a run occurs and it becomes a "do not care" otherwise. Start input signals 711 and end input signals 712 are control signals which indicate whether a run begins, ends, or both. A pass begins or ends at the same time if the pass consists of a single uncoded bit.

The rearrangement unit 801 orders the pass counts generated by the bit generator according to their input signals. A codeword memory 908 stores codewords during reordering. In one embodiment, the codeword memory is 908 greater than the number of pass counts that can be active at a particular time. This leads to a better compression. In fact, if the code word memory is less than the number of pass counts that can be active at a particular time, this would limit the number of active pass counts to a number that could be held in the memory. In a system that provides good compression, it often happens that while accumulating data for a long swept count codeword, many codewords start (or perhaps end) with short sweep counts. This requires a large memory to avoid forcing the long run out before it is finished.

The pointer memory 901 stores addresses for codeword storage locations for probability classes that are in the middle of a run, and addresses a codeword memory 908 in the way of a direct access. The pointer memory 901 has a location for the address in the codeword memory 908 for every probability class that can be in the middle of a run. Once a pass is completed for a particular probability class, the address that is in the pointer memory becomes 901 stored for this probability class, used to access a codeword memory 908 access, and the terminated codeword is at this point in the codeword memory 908 written. Until then, this location contained in the codeword memory 908 an invalid entry. Consequently, the pointer memory stores 901 the location of the invalid codeword for each pass count.

The head counter 903 and the lag counter 904 also generate addresses to access the codeword memory 908 access. With the help of the counter 903 and 904 may be the codeword memory 908 as a queue or a circular buffer (eg a FIFO memory). The tracking counter 904 contains the address of the next available location in the codeword memory 908 to insert a codeword into memory 908 permit. The head counter 903 contains the address in memory 908 of the next code word to be output. In other words, the head counter 903 contains the codeword memory address of the next codeword from the memory 908 is to delete. A location for each possible index (eg, a probability class) in the pointer store 901 is used to remember where the lag counter 904 was when a run was started so that the correct codeword at this point of the codeword memory 908 can be placed when the pass ends.

A control module 903 generates a valid signal as part of the data stored in the codeword memory 908 are stored to indicate whether an entry stores valid memory word data or not. For example, if the valid bit is a logical 1, then the codeword location contains valid data. However, if the valid bit is at logic 0, then the codeword location contains invalid data. A validation module 905 detects when a memory location contains a valid codeword each time a codeword is out of memory 809 is read. In one embodiment, the validation module feels 907 whether the memory location is a valid codeword or a special invalid code.

When a new pass starts, an invalid data entry in the code word memory becomes 908 , The invalid data entry acts as a wildcard in the data stream stored in memory 908 is stored, so that the code word for the pass in the memory can be stored in the correct location to ensure proper ordering (to model the decoder) when the pass is completed. In one embodiment, the invalid data entry terminates the index via the MUX 905 and an invalid indication (eg, an invalid bit) from the control module 909 one. The address in the code word memory 908 at which the invalid entry is stored is from a trailer pointer 904 entered and then in the pointer memory 901 as a remainder of the location for the pass count in the codeword memory 908 saved. The rest of the data, between the head pointer 903 and the tracking pointer 904 In the storage room 908 complete pass counts (eg, unordered pass counts). The maximum number of invalid memory locations is 0 to | -1, where | the number of pass counts is. If a codeword is complete at the end of a pass, the pass count will be in memory 908 with the address in the pointer memory 901 is stored, filled.

When a run starts, the index for the run is in memory 908 stored so that when the memory 908 is full, but the run has not ended yet, the index in connection with the signal 804 is used to reset the corresponding pass counter. In addition to the memory of codewords and indexes in memory 908 For example, a bit called the "valid" bit is used to indicate which of these types of data is stored.

If a pass does not start or end, the pass count reorder unit is empty. When a pass starts and a pass does not end, and when the memory is full, then a codeword from the memory 908 issued. The codeword that is issued is the codeword that has been stored at the address in the header 903 is included for this probability class. Then, if a pass starts and a pass does not end, the index input signal will be (regardless of whether the memory is full) 713 in the store 908 over the mux 903 at the by the tracking pointer 904 enrolled in certain address. The tracking pointer 904 will then be in the lag memory 903 written to an address which is represented by the data in the index input signal 713 are determined (eg at the point in the pointer memory 901 for the probability class). After writing the tail pointer 904 becomes the trailer pointer 904 incremented.

If a pass ends and a pass does not start then the address in the pointer memory becomes 901 is stored according to the index (probability class), read out and used as the location in the codeword memory to obtain the completed word in the codeword input signal 714 save.

When one pass starts and one pass ends (ie one pass both starts and ends at the same time) and when the memory is full, then a codeword from the memory becomes 908 issued. When a pass starts and one pass ends (regardless of whether the memory is full) the codeword input signal 714 in the store 908 at the by the tracking pointer 904 written address. The tracking pointer 904 is then incremented to get the next available location (eg it is incremented by 1).

In the invention, a rearranging unit 801 Output code words at different times. In one embodiment, codewords may be output if they are valid or invalid. Codewords may be issued if they are valid, if there is a condition that the memory is full, and a pass is not completed. Invalid codewords may also be output to maintain a minimum rate (ie, rate control). Likewise, invalid codewords may be output to the codeword memory 908 when all data has undergone a pass count reordering, or when a pass count shuffling unit is placed in the middle of a code word memory 908 as a result of a reset operation jumps. In such a case, the decoder must remember that the encoder is operating in this way.

As described above, a codeword is output when the codeword memory 908 is full. Once the memory is full, if an input (ie, starting a new code word) in the memory 908 is made, an output signal from the memory 908 issued. Refreshing to an entry does not cause an output signal from the memory 908 when there is a condition that the memory is full. That is, the completion of a pass following the writing of the resulting codeword into a previously allocated memory location does not cause an output signal to occur when the memory is full. Similarly, if a pass ends and the corresponding address in the pointer memory 901 and the address in the head counter 903 they are the same, the codeword is delivered immediately and the co-counter 903 can then be incremented without affecting the codeword memory 908 access. In one embodiment, there is a condition that the memory is full when the tracking pointer 904 equal to the head pointer 903 is after the tracking pointer has been incremented. Consequently, as soon as the trailing pointer equals 904 has been incremented, the control logic in the rearrangement unit 801 the tracking pointer 904 in the head pointer 903 and if they are the same, the control logic determines that the codeword memory 908 is full, and that a codeword should be issued. In another embodiment, codewords may be issued before the memory is full. For example, if the part of the queue addressed by the header contains valid codewords, it is output. This requires that the beginning of the queue be repeatedly tested to determine the state of the code words therein. The codeword memory 908 is emptied at the end of a file encoding.

From the rearrangement unit 801 A code word is output by first providing a value (eg, a data value) from the disc 908 is read at an address, which by the head pointer 903 is specified. The outputting of codewords is controlled and coordinated by means of the control logic. The validity module 906 performs a check to determine if the value is a codeword. In other words, the validity module 906 determines if the codeword is valid. In one embodiment, the validation module 906 determine the validity of an entry by checking the validity bit that has been stored with each entry. If the value is a codeword (ie the codeword is valid), then the value is output as a codeword. If, on the other hand, the value is not a codeword, ie the codeword is invalid), then any codeword may be output that has a pass of MPSs that is at least as long as the current sweep count. The "0" codeword is a codeword that correctly represents the current run and can be output. After the output has been performed, the head pointer will become 903 to the next place in the code word memory 908 incremented. On the other hand, with the help of "1N" with the shortest allowable run lengths of the decoder, it can only check if a codeword has been pushed out before giving out an LPS.

In one embodiment, the rearrangement unit operates 801 with two clock cycles. In the first clock cycle, inputs to the reordering unit 801 added. In the second clock cycle, an output arrives at the codeword memory 908 in front.

Although codewords can be output when a head pointer 903 addressed a valid codeword, it may be desirable in some embodiments to output only one codeword when the buffer is full. This causes the system to have a fixed delay in the form of a number of codewords rather than a variable delay. If the memory 908 is a predetermined number of codewords, is between the time at which a run starts and is input and when it is issued, the delay is the number of codewords since an output has not been made until it is full. Consequently, there is a constant delay in the codewords. The reordering delay is still variable with other measures, such as the amount of coded or original data. If a memory 908 is filled prior to generating an output signal, a code word per cycle is generated by the output signal.

If a codeword location is marked as invalid, the unused codes used to store identification, for which pass count this is (i.e., the context bin or probability class, which fill the place must, will stored there). This information is useful to the case to treat at which the memory is full. In particular, can the information is used to indicate to the bit generator the existence Codeword for this special run length was not finished, and that she now has to be ended. In such a case, a decision is made to invalidate a codeword due to the condition that the memory is full is, may have occurred. Consequently, when the system displays the Pass count resets the information if, in terms of bit generators and pass counts, the system starts to start again.

Regarding the Index input may be for pipelining reasons if banks of probability classes used, the index contain a bank identification. This means, it can have multiple pass counts for one give very specific probability class. For example, two Durchlaufzählwerte for the 80% code can be used if first one and then the other is used.

Since the codewords have variable length, they must be in memory 908 are stored in a way that their length is determined. Although it would be possible to explicitly save the size, this word would minimize memory usage. For R codes, a value of zero in memory may be a one-bit "0" Codeword and the "1N" codewords can be stored so that a priority coder can be used to determine the length for the first "1" bit.

If the memory 908 one with multiple inputs (eg, two inputs), this implementation can be pipelined to handle one codeword per clock cycle. Because on one place memory 908 Access from multiple inputs could be a location in memory 908 can be described as if an invalid code word is to be stored, while another part can be read, as when a code word is output. In such a case, multiplexers must be multiplied to support the data and address buses.

If however, the encoder outputs a "0" codeword, and a pass counter resets, since the codeword memory is full, the decoder must do the same. This requires that the Decoder models the encoder codeword queue. As this is done will be explained below.

Around To save performance in CMOS implementations, counters for "| N" codewords can be effective are made when "0" code words are issued for invalid runs become. This means, since a "1N" codeword to be decoded is valid, while only a "0" code word will be invalid can.

Alternative embodiment, based on context

9 Figure 13 is a block diagram for another embodiment of a pass count shuffling unit which rearranges data received according to a context (which is opposite to a probabilistic class). The rearrangement unit 1000 performs a rearrangement using the R codes. In 9 contains the unit 1000 a pointer memory 1001 , a head counter 1002 , a tracking counter 1003 , a data multiplexer (MUX) 1004 , an address mux 1005 , a length calculation block 1006 , a sense of validity 1007 and a codeword memory 1008 , The memory 1008 stores codewords during reordering. The memory 101 stores addresses for codeword storage locations for context fans that are in the middle of a run. Through the counters 1002 and 1003 can be a codeword memory 1008 as a queue or a circular buffer and additionally in the manner of a direct access by the pointer memory 101 be addressed. For R codes, storing a zero value in memory may indicate a one-bit "0" codeword and the "1N" codewords may be stored so that a priority coder may be used to determine the length of the first "1" bit. A length calculation block or module 1008 works like a priority encoder. (If other variable-length codes were used, it would be more memory-efficient to add a "1" bit to add the start of the codeword, rather than adding ₂ bits to log to explicitly store the length.) The Rearrangement Unit 1000 has a "backstage" control logic on the components 1001 to 1008 to coordinate and control.

The operation of the rearrangement unit 1000 is very similar to the rearrangement unit based on probability estimates. When a new pass starts, then an invalid entry, which includes the context bin, becomes the codeword store 1008 written at the address, which by the tracking pointer 1003 is displayed. An address of the tail pointer 1003 will then be in the pointer memory 101 stored at the address of the context bin of the current pass count. The tracking counter 1003 is then incremented. When a pass ends, the pointer in the pointer counter becomes 1001 , which corresponds to the pass count, from the pointer 1001 read, and the codeword is parallel in the codeword memory 1008 written in a place specified by the pointer. If a pass neither starts nor ends and if there is a spot in the code word memory 1008 which is indicated by the address of the head pointer 1004 is determined, does not contain invalid data, the codeword addressed by the head pointer is read in and output. The head pointer 1004 is then incremented. In the event that a pass starts and ends at the same time, the codeword becomes the codeword memory 1008 at the by the tracking pointer 1003 written address and then the tracking pointer 1003 incremented.

Similarly, if one pass ends and the corresponding address in the pointer memory 1001 and the address in the header 1002 they are the same, the codeword output immediately, and the value in the header 1002 can be incremented without going to the codeword memory 1008 recourse.

For pass count "context" systems, each context requests a location in the pointer store 1001 so that the width of the BG and PEM state memory can be extended to implement this memory. The width of the pointer memory 1001 is equal to the size needed for a codeword memory address. The number of digits in the code word memory 1008 can be chosen by the developer in a very specific implementation. The limited size of this memory reduces the com pression efficiency, so that it is a cost / compression trade-off. The width of the codeword memory is equal to the size of the largest codeword plus one bit for a valid / invalid indication.

One Example with the R2 (2) code shown in Table 13 is used to illustrate a reordering. Table 14 shows the data to be reordered (0 = MPS, probable res symbol, 1 = LPS, less probable symbol), which are referred to as context. There are only two contexts. The uncoded bit count shows time in uncoded bit clock cycles. Start and end of runs will be displayed, and codewords be at the end of runs shown.

Table 13 - R2 (2) Code

Table 14 - Examples of data to be encoded

The shuffling operation for the example data is shown in Table 15. A codeword memory for four digits 0 through 3 is used, which is large enough not to overflow in this example. Each line shows the status of the system after an operation which is either the run start or run end for a particular context or the output of a codeword. An "x" is used to indicate memory locations that are "do not care". For some uncoded bits neither a run starts it still ends, so that the rearrangement unit is empty. For coded bits that terminate passes, one or more codewords may be output which may cause several changes in the system state.

Table 15 - Example of reordering operations

In Table 15 initializes the head and tail pointers to zero, which indicates that nothing is contained in the code word memory (e.g., the queue).

Of the Pointer memory is represented with two memory locations, namely one for every context. Every job has "do not care" values in front of you Bit number 1. The codeword memory is represented with a depth of four codewords, which are all initially "do not care" values.

According to the data obtained for the bit number 1, the head pointer remains aiming at the codeword storage location 0. Since the decoder expects data, the next available codeword storage location, 0, is assigned to the codeword and an invalid value is written into the memory location 0. Since the context is zero, the address of the codeword location associated with the codeword is written to a pointer location for the null context (pointer location 0). Consequently, a "0" is added to the pointer memory 0 stored. The tracking pointer is incremented to the next codeword memory location 1.

Corresponding the data corresponding to the number of bits 2, the pointer remains on the aligned first memory location (since there was no output is to be incremented). Since the data is the second context, context 1 context, the next codeword location will be the codeword assigned as a codeword storage location 1, as by the Trailing pointer is displayed and an invalid value is written to the digit. The address, codeword location 1, is placed in the pointer memory location written that corresponds to the context 1. That is, the Address of the second codeword memory location is in the pointer memory location 1 written. The tracking pointer is then incremented.

Corresponding the data corresponding to the bit number 3 is the rearrangement unit empty, as a pass does not start or end.

Corresponding the data corresponding to the number of bits 4 becomes one end of a pass for context 1 is displayed. Therefore, the codeword becomes "101" in FIG the codeword location allocated to context 1 is written (Codeword location 1), as by the pointer location for context 1 is displayed. The head and tail pointers remain the same and the value in the pointer location for context 1 will not return used; so he is "do not care".

Corresponding the data corresponding to the number of bits 5 is the rearrangement unit empty, as a pass does not start or end. According to the Data corresponding to the bit number 6 comes the same type of operations as described above for Bit 2 ahead.

Corresponding the data corresponding to a bit number 7 comes the end of the pass for the codeword for context 0 ago. In this case, the codeword becomes "0" in the codeword storage location written (codeword storage location 0), as indicated by the pointer location for context 0 (pointer location 0). Then the value at the pointer memory location does not become again used so that he is a "do not care" value. As well contains the codeword storage location determined by the head pointer is, valid Dates. Therefore, the valid Data is output and the head pointer is incremented. Through a Incrementing the head store will be to another codeword location shown a valid Code word contains. Consequently, this codeword is output and becomes the head pointer again incremented. In this example, codewords are output if they are okay, which, in contrast, is when the Code word memory completely is full.

One Processing the uncoded bits comes according to the above Description constantly in front. The codeword storage locations are not completely determined Accessible to contexts made, so that codewords of one out of context at a very specific codeword location while encoding a data file.

The bit packing unit

A bit packing unit is in 3 in which data that has been processed by the reordering unit before and after a bitpacking are shown. In 3 There are shown 16 variable length codewords numbered 1 through 16 to indicate the order of use by the decoder. Each codeword is assigned to one of three coded streams. The data in each encoded stream is broken into fixed-length words called nested words. (In this case, a single codeword of variable length can be broken into two nested words). In this example, the nested words are placed in a single nested stream so that the order in the first variable length (or partial codeword) codeword in a particular nested word determines the order of the nested word. Other types of ordering criteria can be performed. The advantage of nesting multiple encoded streams is that a single encoded data channel can be used to transfer data, and variable-length shifting for each stream can be performed in parallel or in a pipeline.

The bitpacking unit 802 of the invention obtains the variable length codewords from the pass count reordering unit 803 and pack them into nested words. The unit 802 has a logic to perform the handling of variable length codewords, and a merged queue reordering unit to output fixed length interleaved words in the correct order. In one embodiment, the codewords are obtained from the reordering unit at a rate of up to one codeword per clock cycle. A block diagram of one embodiment of the bitpacking unit 802 is in 10 shown. In the following embodiment, four nested streams are used, each nested word being 16 bits; the codewords vary in length from 1 to 13 bits. In one embodiment, a single bitpacking unit is provided in pipeline form to handle all streams. If the unit 802 The invention uses a two-port memory (or a register file), it can output one interleaved word per clock cycle. This may be faster than required to maintain the remainder of the encoder.

In 10 indicates the bitpack unit 802 a packing logic 1101 , an electricity meter 1102 , a store 1103 , Tracking pointer 1104 and a head counter 1105 on. The packing logic 1101 is provided to receive the codewords and is connected to the electricity meter 1102 connected, which also with the memory 1103 connected is. Likewise is the memory 1103 with tracking pointers 1104 and head counters 1105 connected.

The electricity meter 1102 holds the track of the interleaved stream to which the current input codeword is assigned. In one embodiment, the electricity meter counts 1102 repeats the streams from 0 to N-1, where N is the number of streams. As soon as an electricity meter 1102 When N reaches 1, it starts counting again from zero. In one embodiment, the electricity meter is 1102 a two-bit counter and counts from 0 to 3 (for four interleaved streams). In one embodiment, the electricity meter initializes 1102 to zero (eg via a global reset).

The packing logic 1101 The current input codeword mixes with previously input codewords to form interlaced codewords. The length of each of the codewords may change. Therefore, the packing logic packs 1101 these codewords of variable length in words of fixed length. The nested codewords used by the packing logic 1101 are generated to the memory 1103 Ordered and placed in the store 1103 saved up to the right time to give it up. In one embodiment, the memory is 1103 static random access memory (SRAM) or 64-bit word register file.

The nested words are in memory 1103 saved. In the invention, the size of the memory 1103 big enough to handle two cases. One case is the normal operation case where an interleaved stream has minimum length codewords and the other interleaved streams have codewords of maximum length. This first case requires (3 × 3 = 39) memory locations. The other case is the initialization case, where again one stream has short codewords or such minimum length and the others have long codewords or those of maximum length. For the second case, where (2 × 3 × 13 = 76) memory locations are sufficient, the operation of the PEM allows a closer bound of 76.

The memory 1103 in cooperation with the electricity meter 1102 and the trailing hands 1104 perform a reordering. The electricity meter 1102 shows a current flow from memory 1103 receiving codewords. Each nested stream is associated with at least one trail pointer. trailing pointer 1104 and the head counter 1105 perform a reordering of the codewords. The reason for two tracking pointers per stream follows from interleaving the word N, which is required by the decoder when data in an interleaved word N-1 contains the start of the next code word. A tracking pointer determines the location in the memory 1103 to store the next nested words from a given nested stream. The other tracking pointer determines the location in memory to store the nested word after the next one. This allows the location of an interleaved word N to be specified when the decoder request timing of the interleaved word N-1 is known. In one embodiment, the pointers are eight 6-bit registers (two tracking pointers per stream).

In one embodiment, the tracking pointers are at the coding start 1104 set so that the first eight interleaved words (two from each stream) in memory 1103 one after the other from each stream. After an initialization is done every time the packing logic 1101 a new nested word for a particular code stream begins, the "next" trailing pointer to a value of the "after next" tail buffer of the code stream is set to the next available memory location. As a result, there are two trailing hands for each stream. In another embodiment, only one trail pointer is used for each stream and it indicates where the next nested word in the memory 1203 to save.

The head store 1105 is used to set the location of the next nested word to be used by the bitpack unit 802 issue. In the described embodiment, the head counter 1105 a 6-bit counter, which is incremented to deliver an entire interlaced word at a particular time.

The memory 1103 which is to be used in addition to rearrangement may also be used as FIFO buffering between the encoder and the channel. It may be desirable to have this memory which is larger than what is required for reordering so that a FIFO Most-Full signal may be used to "stall" the encoder when the Channel with the encoder can not keep up. A one bit per cycle encoder can not generate one bit word per cycle. If an encoder is well matched to a channel, the channel can not accommodate a nested word every cycle, and some FIFO buffering is necessary. For example, a channel that can accept a 16-bit interleaved word every 32 cycles would be a well-adapted design for an effective 2: 1 bandwidth expansion if the compression was 2: 1 or greater.

The packing logic of invention

A block diagram of the packing logic is in 11 shown. In 11 has the packing logic 1101 a size unit 1201 , a set of accumulators 1202 , a sliding unit 1203 , a MUx 1204 , a set of registers 1205 and an OR logic 1206 on. The size unit 1201 is intended to record codewords and is equipped with accumulators 1202 connected. The accumulators both the codewords are to the sliding unit 1203 coupled. The sliding unit 1203 is with the mux 1204 and the OR logic 1206 connected. The MUX 1204 is also with registers 1205 and an output of the OR logic 1206 connected. The registers are also with the OR logic 1206 connected.

In one embodiment, codewords are input to a 13-bit bus with unused zeroed bits. These zeroed unused bits are adjacent to the "1" in "1N" codewords so that a priority encoder is in the size unit 1201 can be used to determine the length of the "1N" codewords and to produce a size for "0" codewords.

batteries 1202 have several accumulators, one for each interleaved stream. The accumulator for each interleaved stream receives a record of the number of bits already in the current interleaved word. In one embodiment, each accumulator has a 4-bit adder (with carry) and a 4-bit register used for each stream. In one embodiment, the output of the adder is the output of the accumulator. In another embodiment, the output of the register is the output of the accumulator. With the help of the size of the codewords, in the size unit 1201 The accumulators will determine the number of bits to shift to concatenate the current codeword in the register containing the current interleaved word for that stream.

Based on the current value of the accumulator, the shifter aligns the current word to follow any previous codewords in the interleaved word. As a result, data in the encoder is shifted in the decoder order. The output of the sliding Einheti 1203 are 28 bits which deal with the case where a 13 bit codeword must be appended to 15 bits in the current interleaved word so that bits from the current codeword end up into the higher 12 bits of the 28 bits to be output. The sliding unit works here 1203 without feedback, and thus can be processed in the pipeline system. In one embodiment, the sliding unit 1203 a barrel shift unit.

register 1205 store bits in the current nested words. In one embodiment, a 16-bit register holds previous bits in the current interleaved word for each interleaved stream.

Initially, a code word of a current from the shift unit 1203 get as a size unit 1201 indicates the size of the codeword on the accumulator which corresponds to the current. The accumulator has an initial value of 0, which has been set via a global reset. Since the accumulator value is zero, the codeword will not be shifted and will then be using the OR logic 1206 where the contents of the register correspond to the stream. However, in some embodiments, 1N codewords must be shifted to be properly aligned, even at the start of a nested word. This register can be initiated at zero, and clearly the result of the OR operation is the codeword in the rightmost bit positions of the output of the OR logic 1206 to put, and are about MUX 1204 fed back to the register for storage up to the next codeword from the stream. Consequently, initially the shift unit operates 1203 as a passage. The number of bits in the first codeword are now stored in the accumulator. Upon receiving the next codeword for this stream, the value in the accumulator will be sent to the shifter 1203 and the codeword is left to the number of bits for combining with any previously entered bits in moved to the nested word. Zeros are placed in the other bit positions in the shifted word. Bits from the register that correspond to the stream will be bits from the shifter 1203 with the help of the OR logic 1206 postponed. If the accumulator generates a carry indication (eg, a signal), then more bits are required to complete the current interleaved word, and the data resulting from the OR operation is passed through the MUX 1204 rescued to the register. In one embodiment, the MUX 1204 a 2: 1 multiplexer. When the accumulator generates a carry, the 16 bits of the ORDERed data are from the OR logic 1206 a complete nested word and are then output. The MUX 1204 causes the register to be replaced with any additional (eg, the upper 12 bits of the 28 bits provided by the shift unit 1203 after the first 16 is loaded, and pad the remainder with zeroes.

The controller will work for both the MUX 1204 as well as for outputting the interleaved word has the carry signal from the accumulator. In one embodiment, the multiplexer 1204 sixteen 12: 1 multiplexers with four of them, with an input value that is always zero.

Shuffling options

The invention provides many options for performing reordering on the data. For example, in a system having multiple code streams, the code streams must be reordered in nested words, as in FIG 3 is shown. The invention therefore provides numerous ways to achieve reordering into nested words.

One method for reordering data in nested words is to use a so-called snooper decoder as described in US Pat 24 is shown. In 24 are multiple pass count reordering units 2501A-n provided to receive codeword information together with the codeword stream. Each unit generates a codeword output value and a magnitude output value. A separate bitpack logic unit ( 1101 ), such as bit packing units 2502A-n are provided to receive the codeword and magnitude output values from one of the reordering units 2501A-n. Bitpackungs logic units 2502A-n make nested words, which are both the MUX 2503 as well as the decoder 2504 be supplied. The decoder 2504 creates a select control signal from the MUX 2503 is received and shows the mux 2503 which nested word is to be output to the code stream.

Each encoded data stream has a pass count shuffle unit which is a pass count shuffle unit 801 in 7 having. Each bitpack unit combines variable length codewords into fixed length codewords, for example 8, 16 or 32 bits per word. Each bitpack unit includes registers and a shift circuit as described above. The decoder 2504 has a fully operational decoder (including BG, PEM, and CM) which can access nested words from all bitpack units (either on separate buses, as in FIG 24 represented, or via a common bus). If the decoder 2504 has selected a nested word of one of the bitpack units, that word is transferred into the code stream. Since the decoder on the receiving side requests the data in the same order as the identical snooper decoder, the interleaved words are transmitted in the correct order.

One Encoder with a snooper decoder can work in half a duplex system be attractive, since the snooper decoder also as a normal Decoder can be used. An advantage of this snooper decoder solution is the applicability to a termininistic coder. Alternative solutions, which will be discussed below without dependence from a snooper decoder use simpler models of the decoder, to reduce hardware costs. For the decoders, which are several codewords in the same clock cycle, modeling the decoder not be possible with less hardware than a decoder itself, which requires the use of a Snooper decoder. As follows is still described exist for decoders, which only mostly decode one codeword per cycle, simpler models.

Another technique for rearranging data for pipelined decoder systems, which usually decode one codeword per clock cycle, is based on the fact that the only information needed to model the decoder requirements for coded data is to change the order of the codecs Knowing codewords (taking into account all codewords, not the codewords for each coded datastream independently). If a timestamp is assigned to each codeword, if it sets the swept count reordering unit, which bit-packed nested word the oldest timestamp associated with it has the next interleaved codeword to be output.

An exemplary encoder rearranging unit is shown in block diagram form in FIG 25 shown. In 25 the encoding system is the same as it is in 24 except that timestamp information is provided for each pass count reorder unit 2501A-1 is obtained. This timestamp information also becomes bitpacking units 2502A-1 further promoted. Bitpackeinheiten 2502A-n see nested words on the MUX 2503 and their associated timestamps to the logic 2601 in front. The logic 2601 creates a control signal at the MUX 2503 to select the nested word to be output in the code stream.

In this embodiment, the snooper encoder is replaced by a simple comparator which determines which of the bitpack units 2502A-n has a codeword (or part of a codeword) with the oldest timestamp. Such a system appears on the MUX 2503 in the form of several snakes with timestamps. The logic 2601 simply choose between different snakes. The logic of each of the units 2503A-n changes only slightly (from a rearrangement unit 801 off) to write a timestamp when a run starts. Each rearrangement unit 2501A-n is equipped to store the timestamp in the codeword memory. Storing timestamps with enough bits to enumerate each codeword in the encoded data stream is sufficient, however, in some embodiments fewer bits may be used.

The Steps associated with multiple timestamped queues are briefly described below. These steps are the encoder operation. No simplification is provided for the cases when a run starts with the same codeword as well ends. The operations can be for each coded symbol to be checked (although in practice not all tests have to be carried out). nested Words are assumed to be 32 bits in size.

The Decoder operations are similar, although the codewords do not need to be secured in line. It is still necessary the timestamp of the codewords secure in the queue.

The function of the timestamps explained above is used to store the order information of the codeword r. An equivalent way of expressing the same concept is by using a single queue for all codewords, ie a merged snake. In the mixed snake system, as in 26 is a single pass count shuffle unit 2701 used for all nested streams. The rearrangement unit 2701 generates codeword size and current output values on bitpack units 2502A-n , the nested words to the mux 2503 and position information to the logic 2702 submit which MUX 2503 signals to output nested words as part of the code stream.

For any streams The reordering memory stores a nested stream ID for each Code word. Each nested stream has its own head pointer. When a bitpack unit needs more data, the corresponding one becomes Header used to retrieve as many codewords as needed to to form a new interlaced word. This can be a mistake be at many codeword storage locations to determine which ones Are parts of the right stream. Alternatively, this may be Look in the code word memory for additional fields to include a linked one List.

A other method to currents according to the invention to nest, use a mixed snake with a solid one Current assignment. This method uses a single tracking pointer, as in the case of the mixed queue, so no time stamps required are. Likewise, multiple headers are used in the previous case so that it There is no overhead to the data from a very specific stream leave. To achieve this, the assignment of codewords corresponding to nested currents the following default for N streams carried out: A codeword M is assigned to a stream M modulo (mod) N. nested streams can codewords from any context or probability class according to this Have method. If the number of streams is a power of two, can M mod N are calculated by throwing away some of the higher order bits become. For example, the codeword reordering memory with 12 bits are addressed and four nested streams are used become. The tracking pointer is 12 bits long, and the two least significant ones Bits identify the encoded stream for the next codeword. Four head pointer with 10 bits each are implicitly each of the four possible ones Combinations of the two least significant bits assigned. Either the trailing and the head pointers are incremented as normal binary counters.

In At the decoder, the shift unit has registers to nested words save. The sliding unit provides aligned accordingly encoded data in the bit generator. If the bit generator has some encoded data, it informs the sliding unit. The Sliding unit presented properly aligned Data from the next nested electricity. If the number of encoded data streams is N, has the sliding unit N - 1 Clock cycles to push out the data used, and maybe one to request another nested codeword before that special one nested power is reused.

The decoder of the invention

The The invention comprises a decoder comprising the real-time coder with a supports limited rearrangement storage. In one embodiment contains the decoder reduces memory requirements and complexity in which a pass count for every Probability class is preserved instead of every context box.

An embodiment the decoder system of the invention

13A FIG. 4 illustrates a block diagram of one embodiment of the decoder hardware system of the invention. In FIG 13A has the decoder system 1400 a FIFO structure 1401 , Decoder 1402 , a store 1403 and a context model 1404 on. The decoder 1402 includes several decoders. Coded data 1410 be from the FIFO structure 1401 which encoded data is sent to the decoder 1402 emits. The decoder 1402 are with the memory 1403 and the context model 1404 connected. The context model 1404 is also with the memory 1403 connected. At an exit of the context model 1404 become the decoded data 1411 issued.

In the system 1400 become the coded data 1410 which are in the FIFO structure 1401 be entered, ordered and nested. The FIFO structure 1401 contains data in the correct order. The streams are sent to the encoders 1402 issued. The decoder 1402 demand from these streams in a serial and deterministic order. Although the order in which decoder 1402 the coded data Request is non-trivial, it is not arbitrary. By ordering the codewords in that order in the encoder, rather than in the decoder, coded data can be interleaved in a single stream. In another embodiment, coded data 1410 have a single stream of unconnected data, with data appended to the data stream for each context bin, context class or likelihood class. In this case, the FIFO 1410 through a storage area 1410 replaced to record all decoded data before sending the data to the decoder 1402 be passed so that the data can be properly segmented.

If the coded data 1410 from the FIFO 1401 be recorded, determines the context model 1404 the current context field. In one embodiment, the context model determines 1404 the current context box based on previous pixels and / or bits. Although not shown, a line buffering may be used for the context model 1404 be included. The line buffering provides the necessary data or form (template), using the context model 1404 sets the current context tray. For example, if the context model is based on pixel values near the current pixel, line buffering may be used to store nearby the pixel values of those pixels that are used to create the specific context.

The decoding system asks for the context box 1400 the decode state of the memory 1403 for the current context tray. In one embodiment, the decoder state reads in the probability evaluation module (PM) state and the bit generator state. The PEM state determines which code to use to decode new codewords. The bit generator state maintains a record of the bits in the current run. The state is on decoders 1402 from the store 1403 out according to one through the contextual model 1404 provided address provided. The address accesses a location in the memory 1403 to, which stores the information corresponding to the context model.

Once the decode state for the current context tray from memory 1403 has been queried from, sets the system 1400 the next decompressed bit and processing the decoder state. decoder 1402 then, if necessary, decode the new codeword and / or update the pass count. The PEM state is updated if necessary, as well as the bit generation state. The decoder 1403 then write the new encoding state to memory 1403 ,

13B represents an embodiment of the invention. In 14B the decoder has a shift logic 1431 , a bit generator logic 1432 , a "new k" logic 1433 , a PEM update logic 1434 , a new codeword logic 1435 , a PEM state cache logic 1436 , a coding mask logic 1437 , a Coding MaxPL, Mask and R3 split expansion logic 1438 , a decoding logic 1439 , a multiplexer 1440 and a pass count updating logic 1441 on. The sliding logic 1431 is provided to the coded data input 1443 as well as the state input 1442 (from memory) to accept. The output signal of the shift logic 1431 is also an input to the biter generation logic 1432 , the "new-k" generation logic 1433 and the PEM update logic 1432 intended. The biter generation logic 1432 is also provided to the state input 1442 and generates the decoded data output value at the context model. The "new k" logic 1433 generates an output signal to an input of the encoding mask logic 1437 is created. The PEM update logic 1434 is also sent to a state input 1432 created and generates the state output signal (memory). The state input 1442 also gets to inputs of the re-encode word logic 1435 and the PEM state encoding logic 1436 created. The output of the logic 1436 is from the expansinslogik 1438 added. The exit of the expansion logic 1438 is with the decoding logic 1539 and also with the updating logic 1441 connected. The other input to the decode logic is at the output of the encoder mask logic 1437 connected. the output of the decoding logic 1439 is with an input of the mux 1440 connected. The other entrance of the MUX 1440 is with the state input 1442 connected. The selection input of the MUX 1440 is with the output of the new codeword logic 1435 connected. The output of the MUX 1440 , the expansion logic 1438 and the logic 1437 are with inputs of the update logic 1441 connected. The output of the logic 1441 is included in the state output to the memory.

The sliding logic 1431 moves data from the code stream. Based on the coded data input and the state input, the logic generates 1432 encoded data on the context model. The logic 1433 also uses the data shifted in and the state input to produce a new value of k. In one embodiment, the logic uses 1431 the PEM state and the first bit of encoded data to produce the new value of k. Based on the new k value generates the logic 1437 an RLZ mask for the next codeword. The RLZ mask for the next codeword is then sent to the Decoding logic 1439 and the updating logic 1441 issued.

The logic 1434 updates the PEM state. In one embodiment, the PEM state is updated using the present state. The current state is then delivered to the memory. The new codeword logic 1431 determines if a new codeword is needed. The PEM logic 1436 determined the code for decoding using the state input 1442 , The code becomes the expansion logic 1438 entered to generate the maximum run length, the current mask and an R3 split value. The logic 1439 decodes the codeword to produce a pass count output. The MUX 1440 either selects the output from the decode logic 1439 or the state input 1442 at the logic 1441 which updates the pass count.

The decoding system 1400 including the decoder 1430 The invention works in a pipeline fashion. In one embodiment, the decoding system determines 1400 In the invention, context fans evaluate probabilities, decode codewords, and generate bits for pass count each in a pipelined manner. In one embodiment, the pipeline structure of the decoding system is in 14A shown. In 14A For example, one embodiment of the pipeline decoding process of the invention is shown in six levels numbered 1 through 6.

In the first stage, the current context box is determined ( 1501 ). In the second stage, after the context box has been determined, a memory read occurs ( 1402 ), wherein the current decode state for the context tray is retrieved from the memory. As stated above, the decode state includes the PEM and bit generator states.

In the third stage of the pipeline decoding process of the invention, a decompressed bit is generated ( 1503 ). As a result, one bit is available on the context model. Two more operations happen during the third stage. The PEM state is converted into a code type ( 1504 ), and it is determined whether a new codeword must be decoded in the third stage ( 1505 ).

During the fourth stage, the decoding system processes a codeword and / or updates the pass count (FIG. 1506 ). Several sub-operations are involved in processing a codeword and updating the pass count. For example, a codeword is decoded to set the next pass count, or the pass count is updated for the current codeword ( 1506 ). If necessary, when new codewords are decoded, multiple coded data is polled from the input FIFO. Another sub-operation occurring in the fourth stage is updating the PEM state ( 1507 ). Lastly, in the fourth stage of the decode pipeline, the new PEM state is used to determine what the runlength zero codeword (to be described later) is for the next code when the sweep count of the current codeword is zero ( 1508 ). During the fifth stage of the decoding pipeline of the invention, the decoder state is written into memory along with an updated PEM state ( 1509 ), and shifting begins for the next codeword ( 1510 ). In the sixth stage, the shift to the next codeword is completed ( 1510 ).

The Pipeline coding of the invention actually begins with a decision whether the decoding process too start is. This statement is based on whether there is enough data to represent the decoder of the invention. If not enough Data from the FIFO, the decoding system gets stuck (Stalled). In another case, the decoding system may get stuck remain when decoded data is submitted to a peripheral facility which is unable to receive the data from the decoder have been submitted to record how they are generated. For example can if the decoder is a delivery to a video display interface and the video circuit assigned to it, the video is too slow be so that the Decoder must be stopped to get a video.

As soon as the decision has been made to start the decoding process, the current context is determined by the context model. In the invention, the current context subject is checked by checking the previous data detected. Such previous data can be found in Line buffers can be stored and can take data from the current one Line and / or previous lines, for example in one Context model for a given bit. Bits of line buffer (s) can be constructed using a model (template) regarding the previous data, so that the context box for the current Data selected accordingly will, whether the previous examining Data matches the model. These line buffers contain bit shift registers. A pattern can be for every bit plane of a n bit image can be used.

In one embodiment, the context tray is selected by providing an address to a memory during the next pipeline stage. The address may contain a predetermined number of bits, such as 3 bits, to identify the bit-plane. With the help of three bits, the bit position in pixel data can be identified. The form used to determine the context can also be represented as part of the address. The bits used to identify the bit-plane and the bits identifying the shape can be combined to generate an address for a specific location in memory that contains the state information for the context slot specified by those bits. For example, by using three bits to determine the bit position in a particular pixel and by using the zen previous bits in the same position in each of the previous pixels in the model, a 13 bit context address can be generated.

With the help of the address generated by the context model, the memory (eg RAM) is accessed to obtain the state information. Of the. State contains the PEM state. The PEM state includes the current probabilistic estimate. Since more than one state uses the same code, the PEM state includes a probability class or a code determination, but not an index in a table, such as those in 4 shown table. If a table, like the one in 4 is used, the PEM state provides the most probable symbol (MPS) as a means to identify whether the current PEM state is located on the positive or negative side of the table. The bit generation state may include the count value and an indication of whether an LPS is present. In one embodiment, the current pass MPS value is also included to decode the next codeword. In the invention, the bit generator state is stored in the memory to reduce the space required for the flow counters. If the space cost in the system is low for each context, then the biter generation state need not be stored in memory.

As soon as the fourth stage has been turned on, become a new bit generator state and a PEM state written to memory. Likewise, in the fifth Stage the coded data stream with the next codeword shifted. The shift operation is completed in the sixth stage.

In 13C is a block diagram of one embodiment of a FIFO structure 1401 of the invention, based on which a nested word buffering for two decoder is explained. A number of decoders may be supported by the teachings of the invention. As shown, the input data and the FIFO are wide enough to hold two interlaced words. FIFO 1401 has a FIFO 1460 , Register 1461 and 1462 , MUXs 1463 and 1464 and a control block 1465 on. The two input codewords are used as the input nested words. Inputs to MUX 1463 are with the outputs of registers 1461 and 1462 connected. The control block 1465 is provided to control signals to FIFO 1460 , Registers 1461 and 1462 and at the muxs 1463 and 1464 to accomplish. Nested words are the output data (output data 1 and 2) provided to two decoders. Each decoder uses a request signal to indicate that the current word has been used and a new word is needed next. The request signals from the decoders are sent to inputs of the control block 1,465 created. The control block 1465 Also outputs a FIFO request signal to request more data from the memory.

• *X bedeutet "dont' care"

Initially, the FIFO and registers 1461 and 1462 filled with data, and it becomes a valid flip-flop in the control unit 1465 set. Each time a request comes, the control block generates 1,465 the data according to the logic shown in Table 16. Table 16

• * X means "do not care"

14B FIG. 4 illustrates another conceptual view of the decoder of the invention 14B For example, variable length (encoded) data is input to an encoder. The decoder outputs (decoded) fixed length data. The output data is coupled as a delayed feedback, which is taken as an input to the decoder. In the decoder of the invention, variable-length shifting used in decoding is based on decoded data available after a certain delay. The feedback delay does not reduce the throughput to the delay tolerant decoder.

The inputted variable length data is divided into interleaved fixed length words, as in connection with 3 is described. The decoder uses the fixed length words as described below in connection with 15 is described. The decoder and a delay model a pipeline decoder as used in conjunction with 14 and 32 or several parallel decoders, as used in conjunction with 1A to 1D are described. Thus, the invention provides a delay tolerant decoder. The delay tolerant decoders of the invention allow variable length data to be handled in parallel.

conventional Decoders (e.g., Huffman decoders) are not always delay tolerant. Information resulting from decoding all previous code words is required to perform the variable-length displacement, the is necessary to the next Code word to decode. On the other hand, the invention provides delay tolerant Decoder.

Move in the decoding system

Of the Decoder of the invention provides a shift logic to the interleaved Move words in the right bit generator for decoding. The shifting unit of the invention does not require a special type initial characters "by context" or "probability" - parallelism. A coder is assumed which transmits a codeword M to the stream M mod N (M% N in C language), where N is the number of streams. In the invention, coded data is represented from the current stream, until a codeword is requested. Only then will the data be on the next Power switched.

15 Figure 1 illustrates an embodiment of the shift unit for the decoder of the invention. The sliding unit 1600 is designed for four data streams. This leaves four clock cycles for each shift operation to. The nested words have 16 bits and the longest code word has 13 bits. In 15 has the sliding unit 1600 four registers 1601 to 1604 which are provided to receive inputs from the interleaved coded data. The outputs of the respective registers 1601 to 1604 are as inputs to MUX 1605 intended. The output of MUX 1605 is with the entrance of a barrel barrel unit 1606 connected. The output value of the sliding unit 1606 is also an input to a register 1706 , to MUX & Register 1608 to 1610 and a size unit 1611 intended. The output of the size unit 1611 is with an accumulator 1612 connected. An output of the accumulator 1612 is to the sliding unit 1606 fed back. An output of the register 1607 is as an input to MUX & Register 1608 intended. An output from MUX & Register 1608 is as an input to MUX & Register 1309 intended. An output of MUX & Register is as an input to MUX & Register 1610 intended. The output value of MUX & Register 1610 is the aligned encoded data value. In one embodiment, the registers are 1601 to 1604 16 bit register, the shift unit 1606 is a 16 bit to 13 bit shift unit and the accumulator 1612 is a 4-bit accumulator.

The registers 1601 to 1604 pick up 16-bit words from the FIFO and give them to the shifter 1601 one. At least 32 Bits of the uncoded data are always at the shift unit 1606 intended. The four registers 1601 to 1604 are initialized to begin with two 16-bit words of coded data. Thus, there is always at least one new codeword available for each stream.

For R codes, the codeword size unit determines 1611 whether there is a "0" or "1N" codeword, and if it is a "1N" codeword, how many bits are after the "1" part of the current codeword. The size unit intended for the same function has already been associated with 11 described. For other codes, determining the size of a codeword is known.

The sliding unit 1600 has a FIFO consisting of four registers, three of which have multiplexed inputs. Each register of registers 1607 to 1610 holds at least one codeword so that the width of the registers and the multiplexers 13 Bits is to accommodate the longest possible codeword. Each register also has a control flip-flop (not shown) associated with it, which indicates when a particular register contains a codeword or when it is on the shift unit 1606 waiting to create a codeword.

The FIFO is never empty. Only one word can be used per clock cycle and only one codeword can be shifted per clock cycle. The delay to perform the move is compensated because the system starts four code words in advance. As each codeword is shifted to be aligned coded data output, the other codewords become in the registers 1607 to 1610 moved down. If the codeword is left in the FIFO in the register 1620 is stored, causes the sliding unit 1606 that code words from registers 1601 to 1604 over the mux 1605 be read out to the registers 1607 to 1609 to fill. The FIFO can be designed to match the register 1607 to fill again with the next codeword as soon as its codeword in the register 1608 is moved.

The sliding unit 1606 , a codeword size calculator 1611 and an accumulator selection unit 1612 handle the variable length move. The accumulator 1216 has four registers, one for each coded data stream, which contain the alignment of the current codeword for each data stream. The accumulator 1214 is a 4-bit accumulator used to control the sliding unit 1606 is used. The accumulator 1612 increases its value by the value of the codeword size unit 1611 has been entered. If the accumulator 1612 overflows (eg ever so, if the shift count 16 or larger), the registers become 1601 to 1604 shifted clock-controlled. Any other 16 bit shift causes a new 32 bit word to be requested from the FIFO. The input value at the accumulator 1611 is the size of the codeword determined by the current code and the first one or the first two bits of the current codeword. In some embodiments, the registers 1601 to 1604 are initialized with the encoded data before decoding can begin.

When a codeword is requested by the system, the registers in the FIFO are clocked so that codewords are moved in the direction of the output. When the sliding unit 1601 is ready to supply a new codeword, it is multiplexed into the first empty register in the FIFO.

In this embodiment, the next codeword signal is received in the bit generator before the decision to switch streams is made. If it can not be guaranteed that the next codeword signal will be received by the bit generator prior to the decision to switch streams, a look-ahead system, such as one shown in FIG 15B is shown used. In 15B is a shift register 1620 , in which a look ahead is applied, shown in the form of a block diagram. The sliding unit 1620 has a sliding unit 1600 which produces outputs of the current encoded data and the next encoded data. The current coded data is sent to an input of a code word preprocessing logic unit 1621 and to an input of a codeword processing unit 1622 created. The next coded data is sent to an input of a code word preprocessing logic unit 1622 created. Outputs from the two logic units 1621 and 1622 be to inputs of a mux 1623 created. The output of MUX 1623 is with another input of codeword processing logic 1624 connected.

The logic using the codeword is divided into two parts, codeword preprocessing logic and codeword processing logic. Two identical pipeline preprocessing units 1621 and 1622 work before the nested stream can be moved. One of the preprocessing units 1621 and 1622 generates the correct information when the power is switched, and the other generates the information when the power is not switched. When the power is switched, the output signal will be output from the multiplexer at the correct codeword preprocessing 1623 to the codeword processing logic 1624 which terminates the operation with the correct codeword.

Off-chip memory and context model

In an embodiment it may be desired be, many chips for to use external storage or external context models. In these embodiments is it desirable the delay between generating a bit and having it available of the bit available on the context model, where several integrated circuits are used.

16 Figure 12 shows a block diagram of one embodiment of a system with both an external context model chip 1701 as well as an encoder chip 1702 with a memory for every context. Here, only the units that are relevant to the context model in the encoding chip are shown; this contains the coding chip 1702 a bit generation, a probabilistic evaluation, etc. In 16 has the coding chip 1702 a context model 1703 zeroth order, context models 1704 and 1705 , a selection logic 1706 , a memory controller 1707 and a memory 1708 on. The context model 1703 zeroth order and the context models 1704 and 1705 generate output signals which are applied to inputs of the selection logic 1706 be created. Another output of the selection logic 1706 is with an output of the external context model chip 1701 connected. The output of the logic 1706 is with an input of the memory 1708 connected. With an input of the memory 1708 is also an output of the memory controller 1707 connected.

About the selection logic 1706 can either be an external context model or an internal context model (eg the context model 1703 zeroth order, the context model 1704 and 1705 ) be used. About the selection logic 1706 can be the internal zero-order part of the context model 1703 be used even if the external context model 1701 is used. The context model 1703 zeroth order creates one bit or more while the external context model chips 1701 the rest is generated. For example, the immediately preceding bits may be fed back and from the context model 1703 be found again while previous bits in the external context model 1701 walk. In this way, time-critical information remains on the chip. As a result, an off-chip communication delay for just generated bits is excluded.

17 Figure 12 is a block diagram of a system with an external context model, external memory 1803 and a coding chip 1802 , In 17 become some memory address lines from the external context model 1801 while others are "zero-order" in the encoding chip 1802 be controlled. That is, the context of the immediately preceding encoding cycle is driven by the zero order context model. This allows the encoder chip to provide the context information from the immediately preceding cycle with a minimum transfer delay. The context model chip 1802 precedes the remainder of the context information, which uses bits that have only been decoded in the previous cycle, and therefore takes into account a transmission delay. In many cases, the context information from the immediately preceding cycle is a zero order Markov state, and the context information of others in the previous cycle is a higher order Markov state. In the 17 The illustrated embodiment eliminates a transmission delay that results in an out-of-order model in the external context model chip 1802 adheres. However, there may still be a context-bin determination with a bit-generated delay due to the decode chip 1802 and the memory 1803 give.

To Note that too another memory architecture could be used. For example can a chip with the context model and a memory on one Chip and the encoder can be used on another chip. As well For example, a system can use a coding chip with an internal memory for some Contexts is used and have an external memory, which for other contexts is used.

Bit generators with one Storage

18 shows a decoder with a pipeline bit generator with memory. In 18 points the decoder 1900 a context model 1901 , a store 1902 , a PEM state-coding block 1903 , a pipeline bit generator 1905 , a store 1904 and a sliding unit 1906 on. The input of the context model 1901 indicates the decoded data from the pipeline bitstream generator 1905 on. At the entrances of the sliding unit 1906 the coded data is obtained. The outcome of the contextual model 1901 is with an input at the store 1902 connected. The output of the memory 1902 is with the PEM block 1903 connected. The output of the PEM block 1903 and the aligned coded data at the output of the shifter 1906 be to inputs of the bit generator 1905 created. The memory 1904 is also by a bidirectional bus with the bit generator 1905 connected, and the output of the bit generator 1905 are the decoded data.

The context model 1904 returns a context tray corresponding to encoded data at its inputs. The context model is called a context-based address for access to memory 1902 used to obtain a probabilistic state. The probability state is from the PEM module 1903 which generates the probability class according to the probability state. The likelihood class is then considered an address for accessing the memory 1904 used to get the pass count; this is then from the bit generator 1905 used to generate the decoded data.

In one embodiment, the memory 1902 a (1024 × 7 bit) memory (where 1024 is the number of different contexts) while the memory is being stored 1404 has a (25 × 14 bit) memory (where 25 is the number of different pass counts).

There Bitgeneratorzustände (Durchlaufzählwerte, etc), probability classes, not context fans, are assigned it's an extra Pipeline delay before a bit is available on the context model. As an update a bit generator state lasts several clock cycles (the bit generator state memory causes a delay) become several bit generator states for every Speed class used. For example, if the pipeline is six clock cycles, then the bit generator state memory six entries per probability class. the counter is used to select correct memory location. Even with multiple entries per probability class, the size of the memory is usually less than the number of contexts. The memory can either with several benches SRAM or with a multi-pass register file.

There a pass count can be assigned to multiple contexts, an embodiment must the probability evaluation state from one or more contexts. In one embodiment becomes the PEM state of the context which causes a pass end updated. Instead of reading, modifying or writing one Durchlaufzählwerts Again, a pass count can be requested before it can be reread be used as soon as the modification is completed.

31 Fig. 12 illustrates a timing diagram of a decoding operation in an embodiment of the invention. In 32 For example, a three-cycle decoding operation is described. Signal names are listed in the left-hand column of the timing diagram. The validity of a signal during any cycle is indicated by a dash during (or part of) the cycle. In certain cases, the unit or logic responsive to generating the signal or applying the valid signal is shown in the dashed block in the valid signal display. In each case, the specific elements and units shown are also provided.

• * CM = Textmodell, SH = Schiebeeinheit, BS = Bit Generator, PEM = Wahrscheinlichkeitsbewertungsmodul
• ** [italics} bedeutet Abhängigkeiten von vorherigem Taktzyklus
• ✝✝ In einer Ausführungsform wird die meiste kombinatorische Logik für ein Aktualisieren des PEM Zustands in dem "PEM-Tabellen"-Schritt durchgeführt; "PEM-Aktualisieren" ist einfach eine Multiplexoperation

A portion of the signal that extends into another cycle shows the validity of the signal only for that period of time, in which the signal is shown that extends into the other cycle. Certain signals are shown which are valid separately for more than one cycle. An example of this is the temp swept count signal, which is valid at one location at the end of the second cycle, and then again during the third cycle. This indicates that the signal is to be registered only at the end of the cycle. A list dependencies is also shown in Table 17 below, which depicts the dependencies for the same or previous clock cycle at the instant that the signal specifies as valid. Table 17

• * CM = text model, SH = shift unit, BS = bit generator, PEM = probability evaluation module
• ** [italics] means dependencies from previous clock cycle
• In one embodiment, most combinatorial logic is performed for updating the PEM state in the "PEM Table"step; PEM update is simply a multiplex operation

Implicit signaling

In some embodiments, the decoder must model in the coder's finite reorder buffer. In one embodiment, this modeling is achieved with implicit signaling. As previously explained with respect to the coder, when a codeword is started in the coder, space in the corresponding buffer is reserved for the codeword in the order in which the codewords should be placed on the canal. If the last slot in a buffer is reserved for a new codeword then some codewords are placed in the compressed bitstream, whether or not they have now been completely determined.

If a partial codeword must be terminated, a codeword can be selected, which is short and correctly specifies the symbols received so far. For example, in an R-coding system, if necessary, a codeword for a series of 100 MPSs in a pass code with 128 maximum run lengths prematurely to complete, the code word for 128 MPSs are used, since this correctly the first 100 symbols specified.

on the other hand can a codeword specifying 100 MPSs followed by an LPS, be used. When the codeword has been completed, it will turn off removed from the reorder buffer and added to the code stream. hereby can previously completed codewords be placed in the code stream. If forcing the completion of a partial codeword for removing a codeword leads to the full buffer, then coding can continue. If a buffer is still full, then the next codeword has to be completed again and added to the code stream become. This process lasts until the buffer that was full is no longer full is. The decoder may signal the encoder for implicit signaling model using a counter for every Bitgenerator state information storage location is used.

In an embodiment every run counter has (Probability class in this Biespiel) a counter, which the same size as the Heading or tracking counter in the encoders (e.g., 6 bits). Every time a new pass is started (a new code word is queried), the corresponding count with the size of the codeword memory loaded. Every time a run is started (a new codeword is queried) are all counters decremented. Any counter, which reaches zero, causes the corresponding pass count deleted is deleted (and the existing LPS becomes).

Options for signaling for finite Storage

One Real-time coding in the invention requires the decoder to make runs of MPSs that are not challenged by an LPS and not the ones that are treated maximum run length are. This happens when the encoder passes through MPSs starts but does not have a enough limited reordering memory, to wait until the run is completed. This condition requires that one new code word to decode, and next time this context box is used; this condition must be signaled to the decoder. Three possible Ways to modify the decoder will be described below.

If the buffer is full, the must pass count for the Context tray or the probability class that is forced out is reset become. To do this effectively, is a store of the context bin or the probability class useful in the codeword memory. Because this only on runs needed which does not yet have an associated codeword, the memory, which is used to store the codeword, shared become. In some system, instead of an incomplete one Word out bits in the context / likelihood class of the (or any) codeword being forced in the buffer not cleared when the buffer is full. The decoder notice this and use the appropriate (wrong) context box or the corresponding probability class.

at In a stream signaling, codewords are used to do this signal to the decoder. In one embodiment, the R2 (k) - and R3 (k) code definitions changed, by non-maximum run lengths from MPS that is not followed by an LPS. This can be done carried out be that one bit added to the codeword which should occur with the lowest probability. This allows a uniquely decodable prefix for the non-maximum run-length counts. Table 18 shows a replacement for R2 (2) codes, which allows one to signal in the stream. The disadvantages This method is that the R-code decoding logic changed must become, and that it There are compression costs every time the codeword is the least Probability occurs.

Table 18

In some embodiments leads the Decoder an implicit signaling by means of timestamps by. A counter holds one Track the current "time" by incrementing every time a codeword is required. If, however, a Codeword is started, the current "time" is in saved to the Co dewort memory. After that The first time a codeword is used, the corresponding stored "time" value plus the size of the coder rearrangement buffer is stored compared with the current "time". If the current "time" is greater, an implicit signal is generated so that a new code word is required becomes. Consequently, the limited reordering memory is in the encoder been simulated. In one embodiment if enough bits are used for "time" values, so that everyone Code words enumerated can be.

Around reduce the required memory, the number of bits, which for The timestamps used are kept to a minimum. If the timestamps use a small number of bits so that time values to be used again, must be watched that all Old timestamps are noted before the meter re-uses starts. Here, N is the size of the number Address bits for Queue or the bit generator state memory. timestamps with (N + 1) bits be used. The bit generator state memory must have several Have accesses, maybe two read and two write requests per decoded bit. A counter is used to cyclically grant the bit generator state memory go through once for each decoded bit is incremented. A storage location that is too old, will be deleted, so that one new code word is queried, if it is needed in the future. This guarantees that everyone Checking timestamps, before any time value is used again.

If the bit generator state memory is smaller than the queue, can the count rate (the timestamp counter) and the required memory bandwidth can be reduced because of each timestamp (one per bit generator state memory) only once the number of cycles tested must become, which are needed to use the whole snake. Also can storing the time stamps in another memory the required Reduce memory bandwidth. In a system, which uses "0" partial-word code words do not need timestamps for "1N" codewords checked to become. In a system, the "1N" codewords for partial runs is used only to check the timestamp before generating an LPS becomes.

In some embodiments becomes an implicit signaling with a snake during one Decoding done. The method may be useful in half a duplex system, in which the hardware for a coding during of decoding available is. The effect of the snake is mostly the same as during the Coding. If a new codeword is required, its index becomes placed in the queue and marked as invalid. If the data are completed by a codeword, their snake entry as valid marked. When data is queued to allow room for new codewords create, if the removed data is marked as invalid are the bit generator state information from this index deleted. This deletion operation may require that Bitgenerator state memory may support an additional write operation.

Explicit signaling, on the other hand, reports a buffer overflow in the form of compressed data. An example of this is to have an additional context pocket used once for each normal context-bin decode or once for each codeword being decoded. Bits coming from the extra context box indicate when the condition is occurring at which a new codeword is needed, and a new codeword must be decoded for the corresponding normal context bin. In this case, the codewords for this particular context need to be properly redrawn. Since the use of this context is a function of anything known about the reordering unit (usually it is used only once for each codeword), the memory required to reorder the additional context can be limited or implicitly modeled. Likewise, the possible codes for this additional context may be limited.

One implicit signaling models the limited encoder buffer, when decoded to produce a signal indicating that a new one is being generated Codeword must be decoded. In one embodiment becomes a timestamp for get every context. In one embodiment, the reorder buffer becomes finite size of the encoder directly modeled. In a half duplex system, since the encoder rearranging circuit while of decoding available These are used to generate the signals for the decoder.

As exactly one implicit signaling is achieved depends on the details of how the encoder recognizes the full buffer state and treated. In a mixed snake system with Fixed allocation may involve the use of multiple head choices allow what "buffer full "means. With a corresponding design of the decoder, a corresponding Model are measured.

The following describes an encoder operation, and a model for use by the encoder in a mixed queue with a fixed stream allocation, in parallel with a probability system. For this example, consider the reorder buffer 256 There should be four interleaving streams, and each word should be 16 bits. If the buffer 256 Contains entries, an entry must be made to a bitpacker (eg, a bitpack unit) before the entry for the 257th codeword can be placed in the queue. If necessary, entries can be forced out earlier. In some systems, removing the first entry in the buffer requires removing enough bits to complete an entire coded codeword. Therefore, if 1 bit codewords are possible, removal of a codeword 0 may also require removal of codewords 4, 8, 12, ... 52, 56, 60 for nested 16 bit words. To ensure that all of these buffer inputs have valid entries, since the memory is full, forcing an entry to be filled may be performed to addresses 64, 192 from the location where a new word is entered (256 - 16 x 4 = 192).

In The decoder has a counter for every Probability. If a new codeword is used to create a Run to start is the counter loaded with 192. If at any time a new codeword if any probability is used, all counters are decremented. If any counter reaches zero, the run length becomes for this Probability zero is set (and the existing LPS flag becomes deleted).

It may be beneficial to multiple RAM banks (a multi-speed memory, a simulation with a fast memory, etc.), and a bank for every coded data stream. This allows all bitpack units Record data simultaneously so that reading multiple codewords for one very particular current does not hinder reading at other currents.

In other systems need several bit packing units for a single memory based on a codeword order decide how it is stored in the buffer. In these systems removing a request from a buffer may be a nested one Do not complete word. Each bit unit usually takes a fraction of a nested word due to. Each bitpack unit takes at least a number of bits equal to the shortest Codeword lengths are (e.g., 1 bit) and at most a number of bits equal to the largest codeword length (e.g., 13 bits). Nested words can not be delivered until the complete are and must be in the initialization order. In this example For example, a bitpack unit for buffering may have 13 nested words; this is the maximum number of nested words using codewords maximum length completed who can, while one other stream has a pending word pending, the codewords are min Length absorbs.

A system in which each codeword requires two writes and one read at a memory may be less desirable for a hardware implementation than a system that performs two writes and two reads. If this is the case for the exemplary four stream system If desired, bitpack units 1 and 2 could share a memory read cycle and bitpack units 1 and 3 could share a different read cycle (or any other combination). Although this would not reduce the size of the buffering required, it would allow a higher transfer rate in the bitpack unit. This may allow bitpack units to better utilize the capacity of the encoded data channel.

Systems with a memory fixed size

One Advantage of a system that has multiple bit generator states higher Probability class, is that the system is lossy Support coding can if a memory of a fixed size overflows. This can be done with image compression for one However, frame buffers and other applications may be useful store only a limited amount of encoded data.

For systems with a memory of fixed size, be the multiple bit generator states for every probability each associated with a portion of the data. For example, each could eight states a very specific bit level for eight bit data to be assigned. In this case, a sliding unit becomes each Part of the data assigned, in contrast to sliding units, the one after the other Generate codeword. It should be noted that the data is not covered by a Bitebene must be shared. Likewise, no interleaving is performed in the encoder; everyone Part of the data is simply bit-packed. A memory becomes everyone Part of the data assigned.

A Memory management for coded data is for Systems that store all the data in a fixed-size memory, and for Systems that transmit data to a channel with a maximum allowed bandwidth. In these two systems is a moderate deterioration in a lossy system desired. Different data streams will be for data used with varying importance so that few important streams saved or not transferred can be if there is not enough memory or bandwidth available.

When memory is used, the encoded data must be stored so that it can be accessed so that less important data streams can be discarded without losing the ability to decode important data streams. Since coded data has a variable length, dynamic memory allocation can be used. 30 shows, for example, a dynamic memory allocation unit for three coded data streams. A register file 3100 (or other memory) holds one pointer for each data stream plus another pointer to indicate the next free memory location. The memory 3101 is divided into pages of fixed size.

At first Each pointer associated with a stream points to the beginning one memory page, and the free pointer to the next available memory page. Coded data from a very specific stream will be sent to one Memory location saved by the corresponding pointer is addressed. The pointer is then incremented to the next memory location.

If the pointer is the maximum for When the current page is reached, the following results. The address of the Start the next free page (which is stored in the free pointer) is with stored on the current page (either a part of the coded Data store or a separate store or register file could be used). The current pointer will be on the next free one Page set and then incremented. These actions arrange one new memory page to a very specific power and create connections, that the Assignment order during of the decoding can be determined.

If all pages in the memory are used and it gets more data out Given a data stream, one of three things can be done. In all three cases becomes a memory associated with the least important data stream is to be assigned to a more important data stream again and it No more data is stored on the least important data stream.

First just becomes the page that is just the least important Power used, assigned to the more important data. Because the typical Entropy coders use internal state information, all go lost the least important data previously in this Page are stored.

Second, the page currently being used by the least important stream is simply assigned to the more important data stream. Unlike the previous case, the pointer is placed at the bottom of the page, and as more important data is written to the page, the corresponding pointer becomes decremented. This has the advantage of getting the least important data at the top of the page if the more important data stream does not require the entire page.

thirdly instead of the current page with the least important data again will allocate any page of least important data reassigned. This requires that the coded Data for all pages independent are to be coded from each other, which reduces the achieved compression becomes. This also requires that the uncoded data, the corresponding to the start / beginning of all pages. Since one of the least important data can be thrown away, is more flexibility in terms of a reasonable deterioration in lossy coding available. The third alternative may be particularly attractive in a system which achieves a fixed compression rate over areas of the image. A specified number of memory pages can be in one area be assigned to the image. Whether less important data withheld or not, may depend on the compression in the particular Area is reached. (The memory associated with an area is not complete be exploited when requiring lossless compression which requires less than the allocated amount of memory). One Achieving a fixed compression rate in an area of the image can support any access to the image area.

The Ability, To write data in each page from both ends can be used will improve the overall memory available in the system to use. If all pages are assigned, a page that can be has enough free space at the end for one use of the end from being assigned. The possibility, to use both ends of a page must be balanced against the cost be to keep a track to the point where the two data types fit (this is difficult for the case that one of the Data types was not important and could easily be written about it).

Now Consider a system in which data is transmitted in a channel instead of being stored in a memory. Memory pages firmer To become size but only one page per stream is needed. (Or maybe two if needed after the ping-pong method to buffer for to create the channel, so that while one is written, the other is read out for output). When a memory page is full, it is transferred to the channel, and the storage location can be used again as soon as the page is transferred is. In some applications can change the page size of the memory the size of data packets, which have been used in the channel or be a multiple of a packet size.

In some transmission systems, For example, ATM (Asynchronous Transfermode) can be Priority Packets be assigned. ATM has two priority levels, a priority one and a secondary one. secondary Packages are only transmitted if enough bandwidth available is. A threshold can be used to determine which ones streams are priority and which secondary are. Another method would be to use a threshold at the encoder, around streams not to transfer which were less important than a threshold.

Separate bit generators for each code

19 Figure 12 is a block diagram of a system with separate bit generators for each code. In 19 has the decoding system 2000 a context model 2001 , a store 2002 , a PEM state coding block 2003 , a decoder 2004 , Bit generators 2005A-n and a disk unit 2006 on. The outcome of the contextual model 2001 is with an input of the memory 2002 connected. The output of the memory 2002 is with an input of the PEM block 2003 connected. The exit of the block 2003 is with an input of the decoder 2004 connected. The output of the decoder 2004 is as a sharing for bit generators 2005A-n intended. bit generators 2005A-n are provided to receive encoded data from the sliding unit 2006 have been delivered.

The context model 2001 , the memory 2002 and the PEM block 2003 work similar to their counterparts in 18 , The context model 2001 creates a context tray. The memory 2002 returns a probabilistic state based on the context bin. The probability state is from the PEM block 2003 which generates a probability class for each probability state. The decoder 2004 gives one of the bit generators 2005A-n for coding the probability class free. (The decoder 2004 is an M on 2 ^M -De coding circuit which corresponds to a (74 × 138 3: 8) decoder, which is known - and is not an entropy coding decoder). Because each code has a separate bit generator, some bit generators can use codes, not R codes. In particular, a code for probabilities close to 60% can be used to calculate the probability space between the two better cover R2 (0) and R2 (1). For example, Table 19 shows such a code.

Table 19

Around the desired To achieve speed, if necessary, a pre-decode be performed by one or more bits to guarantee that decoded Data is readily available. In some embodiments To avoid the need, add a large pass count update every clock cycle, both codeword decoding as well as the run count for long Split codes.

Of the Bitegenerator for R2 (0) codes is straightforward. A codeword is required every time when a bit is requested. The generated bit is just that Codeword (XORed with the MPS).

codes for a short time Run lengths For example, R2 (1), R3 (1), R2 (2), and R3 (2) become the following treated. All bits in a codeword are decoded and in one State device which has a small counter (1, 2 or 3 bits) and an LPS bit. The counter and the LPS bit work as an R-code decoder.

For longer codes, such as R2 (k) and R3 (k) for k> 2, bit generators are divided into two units, as in 20 is shown. In 20 is a bit generator structure for R2 (k) codes for k> 2 with one unit 2101 for a short run and a unit 2102 shown for a long run. Although the structure is used at R2 (k> 2), its operation is similar to R3 (k> 2) codes (and is familiar to those skilled in the art).

The unit 2101 for a short pass is provided to provide an enable signal and a codeword [0 .. 2] as inputs to the bit generator and a signal of "all zeros" and a count zero signal (indicating a count of zero), both of the unit 2102 for long run, record. Accordingly, there is the unit at these entrances 2101 a decoded bit and an indication of the next signal, thereby signaling that a new codeword is needed. The unit 2101 Also generates a count enable signal, a counter charge signal, and a "max count" signal to the unit 2102 for a long run. The unit 2102 is also provided to receive codewords [k ... 3] as an input to the bit generator.

The unit 2102 handles runs up to a length of 4 and corresponds to an R2 (2) bit generator. In one embodiment, the unit is 2101 same for all R2 (k> 2) codes. The purpose of the unit 2102 for a long pass is to determine when to spend the last 1 to 4 bits of the pass. The unit 2102 has inputs, an AND logic and a counter, which vary in size with k.

An execution of the count unit 2102 for a long run is in 21 shown. In 21 indicates the unit 2102 an AND logic 2201 provided to receive the codeword [k ... 3], and outputs a signal "all ones" as a logical 1 when all the bits in the codeword are 1 ', thereby indicating that the current one Codeword is a 1N codeword, and that the pass count is less than 4. Likewise is a non-logic 2202 provided to receive the codeword and to invert it. The output of the non-logic 2202 is with an input of a bit counter 2203 connected. The bit counter 2203 and the count enable signal, the counter load signal and the "count max" signal. The bit counter generates according to the input signals 2203 a signal "count zero".

In one embodiment, the counter is 2003 a k-2 bit counter and is used to break long pass counts in runs of four MPSs and possibly some remainder. The count enable signal indicates that four MPSs have been issued and the counter should be decremented. The counter load signal is used when "1N" codewords are decoded and the counter with the complement of codeword bits k is to be loaded by 3. The signal "Count max." is used when "0" codewords are decoded and loads the counter with the maximum value. The output signal "count zero" indicates when the counter is zero.

An embodiment of the counting unit 2102 for a short run is in 22 shown. 22 contains the counting unit of a control module 2301 , a 2-bit counter 2302 and a 3-bit counter 2303 , The control module 2301 receives the enable signal (the codeword [0 ... 2], and all the "zero count" ones and signals from the long sweep count unit.) The 2-bit counter is used to count four bit sweeps of MPSs that are part of longer runs, one AR (2) counter and one LPS bit (3 bits total) 2303 are used to generate the 1 to 4 bits at the end of a run. The enable input signal indicates that a bit should be generated at the bit output. The input signal "count zero" indicates, if it is not asserted, that one pass of four MPSs should be issued. However, if de MPS counter 2302 reaches zero, the count enable output is asserted. When the input signal "count zero" is asserted, either the R2 (2) counter, the LPS, is used or a new codeword is decoded and the next output is asserted.

When the new codeword is decoded, the actions taken are determined by the codeword input. If the input is a "0" codeword, the MPS counter becomes 2302 used, and the output "Count max." is asserted. For "1N" codewords, the first three bits of the codeword become the R282) counter and LPS 2303 and the counter charge output is asserted. If all input ones are asserted, then the R2 (2) counter and LPS become 2303 used to generate bits. Otherwise, the MPS counter is used until the zero count input signal is asserted.

From From a symmetrical perspective, the number of codes would be small for the System to work well, usually 25 or less. The size of the multiplexer, the for Bit and the next Code word related outputs needed and the decoder for enabling a particular bit generator must be for a quick Operation be limited. Likewise, the code word from the sliding unit does not have to too high for to be a high speed operation.

separate Bit generators for Each code allows pipeline processing. If all codewords off could result in processing of at least three bits codewords in two cycles instead of one in the form of a pipeline become. This can double the speed of the decoder be when the bit counter were a limiting part of the system. One way to achieve this is in that on the codeword with a run length zero (the codeword indicates exactly one LPS) follows a bit which the next uncoded bit is. These could are referred to as RN (k) + 1 codes, and would always be at least two bits encode. R2 (0) codewords and maybe some of the other short codewords need for an appropriate one Speed not to be connected to a pipeline.

separate Bit generators are themselves suitable for use in conjunction an implicit signaling. An implicit signaling for one Coding with a finite memory can be achieved in the following way become. Each bit generator has a counter the size of one Queue address, for example, has 9 bits if a queue used with a size 512 becomes. Every time a new codeword is used by a bit generator becomes, becomes the counter loaded with the maximum value. Every time a bit generator turns on Code word requests are the counters for all Bit generators are reduced in size. Every time a counter is zero reached, the corresponding bit generator state is deleted (for example, the MPS counter the R2 (2) counter and LPS and the counter for one long pass count will be deleted). As a deletion can happen even if a very specific bit generator does not is released, there is no difficulty with used up Counts.

Memory initialization for each context specialist

In cases where a memory for each context pocket receives probability score information, additional memory bandwidth may be required to initialize the decoder (eg, memory) very quickly. Fast initializing the decoder can be a problem if the decoder has many contexts and they all need to be cleared. If the decoder has many contexts (1K or more) and the memory can not be erased globally, an unacceptable large number of clock cycles would be required to erase the memory.

Around Quickly clear contexts, use some embodiments invention an extra bit, which is referred to here as the initialized status bit, the is saved with every context. Consequently, an additional Bit in the PEM state (e.g., 8 bits) for saved every context.

The memory for each context box and the initialization control logic are in 23 shown. In 23 is a context store 2401 with a register 2402 connected. In one embodiment, the register 2402 a one-bit register which indicates the current correct state for the initialized state partition. The registry 2402 is with an input of an XOR logic 2403 connected. Another input to the XOR logic 2403 is saved with an output with 2401 connected is. The output of the XOR logic 2403 is the valid signal and with an input of a control logic 2404 connected. Other inputs of the control logic 2404 are with the output of the counter 2405 and the next context switch signal. The output of the control logic 2404 is with dialing inputs from MUXs 2406 to 2407 and with an input of a counter 2405 connected. Another output of the control logic 2404 is with the dialing input of MUX 2408 connected. The inputs of MUX 2406 are with the output of a counter 2405 and the context-box ad. The output of MUX 2406 is with the store 2401 connected. The inputs of MUX 2407 are connected to the new PEM state and zero. The output of MUX 2407 is with input of the memory 2401 and the initial PEM state is with the input of MUX 2408 connected. The output of MUX 2408 is the PEM state output.

The value in the register 2402 completes every decode operation (ie, every set, not every decoded bit). The XOR logic 2403 compares the validity of the accessed memory location with the register value to determine if the accessed memory location is valid for that decoding operation. This is done using the XOR logic 2403 reached to return the initialized status bit to the proper state in the register 2402 fits. When data is in memory 2401 are not valid, then causes the control logic 2404 in that the data in the state are to be ignored on the coding logic and that the initial PEM state is to be used instead. This is done with the help of MUX 2403 reached. When a new PEM state is written to memory, the initialized bit is brought to the current value of the register so that it is considered valid when accessed again.

Each context-bin memory entry must be an initialized status bit that is brought to the current value of the register before another decode operation can begin. The counter 2405 iterates through all memory locations to make sure they are initialized. However, if a context tray is used but its PEM state is not updated, the unused write cycle may be used to store the memory location in the counter 2405 has been shown to test or update. After a decode operation is completed, if the counter 2405 has not reached the maximum value, the remaining contexts are initialized before the next operation begins. The following logic is used to control an operation:

PEM with fast adaptation

Of the PEM used in the present invention may be an adaptation scheme included, for a faster adaptation regardless of the available amount of data to allow Invention may enable decoding to be faster at first adapt and slow down to adapt as more data becomes available, as a means to make a more precise proposal or estimated value to accomplish. Furthermore, the PEM may be in a field programmable word order (FPGA) to or an ASIC implementation of a PEM state table / device be.

The Tables 20 to 25 below describe a number of probability score state devices. Some tables do not use R3 codes or use long Codes to reduce hardware costs. All tables except the Table 20 uses special fast "adapting" states that are used to adapt quickly at code start until the first LPS occurs. These fast adaptation states are initialized in the tables. For example in Table 21, when decoding begins, the current state a state 0. When an MPS occurs, the decoder goes to state 35 over. As long as MPSs occur, the decoder goes from state 35, finally goes he over to state 28. If at any time an LPS occurs, the decoder goes off starting from the fast adaptation states to a state over which represents the correct probability state for the data that have been obtained to that extent.

For each table goes after getting a certain number of MPSs that Decoder of fast Adaptierzuständen. In the desired embodiment there is no, since the fast Adaptierzustände have been stimulated Mechanism to go back to this except the coding process becomes started again. In other embodiments, the state table be designed according to these fast Adaptierzustände again to allow faster adaptation. In the invention is it for the decoder possible, faster to reach the more staggered codes, thereby possibly to gain improved compression. The fast adaptation can for a specific table by changing the table entry for one current state 0 are eliminated so that the table is only one State up or down depending on the entered Data passes.

• * Schalten für MPS

Tabelle 21

• * Schalten für MPS

Tabelle 22

• * Schalten MPS

Tabelle 23

• * Schalten MPS

Tabelle 24

• * Schalten MPS

Tabelle 25

• * Schalten MPS

For all tables, the data for each state is the code for that state, the next state for a positive current value and the next state for a negative current value (bottom). Asterisks indicate conditions where the MPS must be changed to a negative current value. Table 20

• * Switching for MPS

Table 21

• * Switching for MPS

Table 22

• * Turn on MPS

Table 23

• * Turn on MPS

Table 24

• * Turn on MPS

Table 25

• * Turn on MPS

One Adding a fast addition to a probability move only helps with the coding start. Other methods can be applied to an adaptation during to improve the coding when the statistical value of a context tray change faster than the previously described PEM state tables can follow.

A Method to get a fast adaptation during encoding, It is an acceleration term to the current PEM state value add. This acceleration could be housed in a PEM state table by any code a constant number of times (e.g., 8) is repeated. Then one can Acceleration term M (e.g., a positive integer) is added or from the current state, when updated, so it is become. If M is 1, the system works the same as one without an acceleration and it comes to the slowest adaptation. If M greater than 1, there is a faster adaptation. At first M can any value greater than 1 to initially provide a fast adaptation.

A Method of the invention to update the value of M based on the number of consecutive codewords. For example, if a predetermined number of codewords has occurred consecutively, then the value of M is increased. If for example, four consecutive code words "0" "0" "0" "0" or "1N" "1N" "1N" "1N", then the value of M is increased. In contrast, a switching pattern between "0" and "1N" codewords may be used to decrease the value of M. For example, if four successive codewords "0" "1N" "0" "1N" or "1N" "0" "1N" "0", then the value of M is lowered.

at another acceleration method uses state tables in which each code is repeated S times, where S is a positive integer is. S is an inverse acceleration parameter. If S is one, the adaptation is fast, and when S is larger, the adaptation slows down. The value of S may initially be set to 1 to get a fast adaptation at first. With help a similar one Method of any of the above may be the value of S are updated when four consecutive codewords are "0" "0" "0" "0" or "1N" "1N" "1N" "1N". In such a Case, the value of S is lowered. In contrast, when four consecutive codewords "0" "1N" "0" "1N" or "1N" "0" "1N" "0", the value of S increases.

The Definition of consecutive codewords can have multiple meanings have. In a "context" system, successive ones can be used Codewords on consecutive codewords in a context box clues. In a "probability" system can be consecutive Codewords on consecutive codewords in a probability class clues. On the other hand, in each system successive codewords on codewords globally to point out (without consideration to a context or probability class). For this three examples and the memory bits required to make a Codewords history to get, 3 × number contextual subjects, 3 × number of probability classes or 3. Maintaining one Acceleration for every context compartment can create the best adaptation. As a bad Often track for a global change in the uncoded data, Global determination of acceleration can also be a good one Create adaptation.

System applications

One Success of any compression system is memory requirements for one Reduce the record. The parallel system of the invention may for one Application to serve as a substitute, running through a lossless Fully filled coding system and can be applied to systems that use sound, Text, databases, computers or other digital data, signals or symbols work. For example, lossless coding systems include a facsimile compression, a database compression, a compression graphical bitmap images and a compression of transform coefficients in image compression standards, like JPEG and MPEG. The invention enables a small efficient hardware implementation and relatively fast software implementation, so that's it a good choice for yourself There are applications that do not require high speed.

The actual advantage that the invention has over the prior art is the possibility of very high speed operation, especially in decoding. In this way, costly high-speed channels can be fully exploited with the aid of the invention, such as high-speed computer networks, satellites and terrestrial radio channels. 28 illustrates such a system in which radio data or a high-speed computer network data to a decoding system 2801 which parallels the data to produce output data. Current hardware entropy (such as the Q-Coder) would slow down the throughput of these systems. All of these systems are designed to have a high bandwidth at high cost. It is counterproductive to have a decoder with slow passage. The parallel system of the invention not only accommodates these high bandwidths, but actually increases the effective bandwidth since the data can be transmitted in compressed form.

The parallel operating system of the invention is also applicable to obtain effective bandwidth outside moderately fast channels such as ISDN, CD-ROM and SCSI. Such a bandwidth adjustment system is in 28 shown where data from sources, such as a DC-ROM, Ethernet, a narrow computer standard interface (SCSI) or other similar source are sent to a decoding system 2901 which receives and decodes the data to produce an output signal. These channels are even faster than some current coders. Often, these channels are used to service a data source that requires more bandwidth than the channel has, such as real-time video or computer-based multimedia systems. The system of the invention can perform the role of bandwidth adaptation.

The system of the invention is an excellent choice for an entropy coder part of a real-time video system similar to the high-definition television system (HDTV) and MPEG video standards. Such a system is in 29 shown. In 29 the real-time video system has a decoding system 3001 on which works with compressed image data. The system 3001 decodes the data and passes it to a lossy decoder 3002 from. The lossy decoder could be the transform color conversion and subsampling part of an HDTV or MPEG decoder. The display 3003 can be a TV or video monitor.

consequently are a method and apparatus for parallel decoding and encoding data.

Claims (115)

Method for encoding a data stream, the comprising: a) an incoming data stream will be in parallel streams while the coding is divided by an entropy coder and it becomes from the entropy coder codewords variable length output, the codewords represent the shared data stream; b) the output codewords variable Be length ordered in an order held at the beginning of each codeword is; and c) become the ordered variable length code words in codewords fixed length transformed. The method of claim 1, wherein each of the Number of codewords is issued at the beginning of each pass. The method of claim 1, wherein the step generating coded data further combining variable codewords Length in Data structures of fixed length having. The method of claim 3, wherein each of the data structures fixed length has a nested word. The method of claim 4, wherein coded data are output such that codewords in a decoding order are ordered. The method of claim 1, wherein code words are ordered become. The method of claim 1, wherein the step generating codeword information comprising the steps of: Produce that of a probability state of a codeword; Select one Bit generation codes based on the probability state; and Accessing a memory to receive the bit generation code associated pass count to obtain. Coding system for coding a data stream, with one Entropy coder intended to record the data stream is to code words variable length and further comprising a plurality of codewords from the entropy coder generated and output in parallel, and a rearrangement unit, which is connected to the entropy coder to get out of the parallel generated codewords variable length generate a code stream, wherein the reordering unit code words, the have been generated by the encoder in a decoder order rearranges, based on data at the beginning of part of the data stream represented by each codeword. A coding system according to claim 8, wherein the rearrangement unit the codewords in such a way as to indicate codeword size. Coding system according to claim 9, wherein 1n codewords so that the most significant "1" bit indicates the length of each codeword. The coding system of claim 8, wherein the rearranging unit comprises at least one sweep count shuffle unit for generating each of the plurality of codewords in the codeword information at the beginning of each sweep, and at least one bit pack unit for combining variable length codewords into fixed length data structures ren. A coding system according to claim 11, wherein each the data structures of fixed length has a nested word. Coding system according to claim 8, having a memory, which is connected to the rearrangement unit to code words in to save an order. A coding system according to claim 8, wherein the encoder having: a context model; a probability estimation module, which is connected to the context model; and a bit generator structure, which is associated with the probability estimator module Codeword to generate according to the data stream. The coding system of claim 14, wherein the encoder a memory having a number of pass counts stores, and in which the memory using probability classes from the probability estimation module is accessed to one of the number of pass counts to the bit generator for to provide output as part of the codeword information. The coding system of claim 14, wherein the bit generator structure having: a bit generator corresponding to codeword information an index and an MPS / LPS display, and one memory connected to the bit generator to indicate a pass count to deliver the bit generator, where the bit generator is the memory based on the index reads and a bit generation based on Performs data, obtained from reading the memory. The coding system of claim 16, wherein the codeword information a first signal indicating whether the MPS / LPS indicator is starting a pass, a second signal indicating whether the MPS / LPS indicator has the end of a pass, and an output codeword having. A coding system according to claim 11, wherein the at least a bitpack unit sorts nested words to the encoded one Generate data stream as interleaved streams corresponding to a nth previous codeword in each nested word each Electricity is ordered. The coding system of claim 11, wherein the rearrangement unit a snooper decoder for selecting nested words, which have been delivered in the code stream. The coding system of claim 19, wherein the rearrangement unit a number of pass count shuffling units which are connected to a number of bitpack units, wherein each of the number of bitpacking units generates nested words, and the snooper decoder a nested word out of the number nested words as an output in the code stream selects. A coding system according to claim 8, wherein the codeword information contains a timestamp, and wherein the rearrangement unit further comprises logic, around nested words deliver based on associated timestamps. The coding system of claim 21, wherein the rearrangement unit a number of pass count shuffling units which are connected to a number of bitpack units, and where the logic causes nested words to be based be submitted on the associated timestamps. A coding system according to claim 22, wherein nested ones words based on the oldest Timestamp are delivered. A coding system according to claim 11, wherein a only snake codewords to a number of bitpack units, and in which the number Bitpackers nested words to output as part of the code stream generated. The coding system of claim 24, wherein the single queue includes a single pass count shuffling unit, and wherein the logic outputs the next interleaved word as part of the code stream. A coding system according to claim 11, wherein a only snake codewords to a single bitpack unit. The coding system of claim 8, wherein the rearrangement unit a pass count reordering unit for reordering run counts, by placing each codeword at the beginning of a run and a bitpack unit provided to encode codewords from the pass count reorder unit to get to codewords into a number of nested words fixed length too combine and the number of nested words of fixed length in one To deliver from a decoder required order. The coding system of claim 27, wherein the rearrangement unit further comprising a memory for storing codewords during reordering. The coding system of claim 27, wherein the encoder a context model, a probability assessment module, associated with the context, and one with the probability score module having associated bitstream generator. The coding system of claim 29, wherein the pass count shuffling unit further comprising: a first memory to code words to to save; a first indicator and a second indicator, to address the first memory as a queue, the first indicator on a first entry shows that as an output of the first memory, and the second indicator points to a second entry, available as a next available and unassigned one Memory location has been determined in the first memory. Coding system according to claim 30, having a pointer memory for storing address information, the digits in the first Memory matches that currently for storing codewords for each Index is determined. The coding system of claim 31, wherein each one Index displays a probability class. The coding system of claim 31, wherein each one Index displays at least one context. The coding system of claim 27, wherein the rearrangement unit a codeword memory queue for storing codewords, a Header connected to the codeword memory queue, by at least one memory location of at least one code word for outputting from the codeword memory queue, and a tracking pointer has at least one memory location for insertion of codewords in to display the codeword storage queue. The coding system of claim 34, wherein each one Codeword entry in the codeword memory queue a validity indicator contains and further comprising a codeword from the codeword memory queue is issued when the head pointer specifies the address of the code word and the validity indicator for the Code word of validity displays. The coding system of claim 27, wherein the bitpack unit a bit packing logic to code words from the rearrangement unit record and codewords in encrypted words for one Number of streams to mix. The coding system of claim 36, wherein the bit packing logic further comprising a number of accumulators and a number of registers, wherein each of the number of registers is one of the number of accumulators and one of the number of streams where each register is for storing a nested one Word for its associated power and each accumulator the next location in the assigned Register for storing a current code word for the stream indicates that each code word for one of the number of streams to the Content of the register attached This is one of the number of streams based on the value in the associated accumulator, is assigned. A coding system according to claim 37, comprising a shift unit connected to said number of accumulators for shifting code words in accordance with at least one of said plurality of accumulators, wherein codewords for appending to contents in one of the plurality of registers are shifted based on an accumulator value to pack parts of at least two codewords into each interleaved word. Coding system according to claim 36, with a reordering memory, around nested words in an order determined by the decoder. Coding system according to claim 39, comprising a number Pointers that correspond to a number of nested streams wherein each of the number of pointers is a location in the reordering memory for the next nested word for each of the number of streams certainly. Coding system according to claim 27, with a number Pass count-reordering, wherein each of the pass count reordering units one of the coded data streams associated with a number of bitpack units that, when each of the Number of bitpack units with a particular one of Number of pass count shuffling units connected, nested words for each coded data stream is generated, and with a decoder to the nested words from the number of bit pack units as the coded output signal select. Coding system according to claim 27, with a number Pass count-reordering, wherein each of the pass count reordering units one of the coded data streams is assigned and generates a number of codewords and a timestamp, each of the number of codewords associated with a number of bitpack units for generating interleaved ones words for each coded data stream and with a logic to each of the nested words, based on timestamps of codewords in each of the nested ones words, select. The coding system of claim 42, wherein the logic select a nested word, that's a codeword with the oldest Contains timestamp, from a number of nested words for each output of the encoder. The coding system of claim 27, wherein the bitpack unit comprises a number of bitpack units connected to code words one of a number of streams and further comprising logic to interleave words for output from each of the number of bitpacking units based on the next stream select. The coding system of claim 27, wherein the rearrangement unit further comprising a finite memory. Coding system according to claim 8 or 27 for entropy coding of data, with an index generator for generating indices based on the data, and a state table connected is a probability estimate based on the indices to create, the state table a first number states and a second number of states where each of the states corresponds to a code, and further where transitions between different Codes corresponding to the first number of states are faster occur when transitioning between states in the first number states is called, as transitions between different codes that correspond to the second number states when in the passed over to the second number of states becomes. A coding system according to claim 46, wherein the first Number of states only for a predetermined number of indexes is used. A coding system according to claim 46, wherein the first Number of states only for a predetermined number of indexes is used initially index the state table. The coding system of claim 46, wherein each one the first number of states an R2 code is assigned. A coding system according to claim 47, wherein the first Number of states at least one transition to the second number of states contains so that the state table turns out to the second number states the first number of states after the predetermined number of indices passes. A coding system according to claim 46, wherein each the first number of states associated with a different code. The coding system of claim 46, wherein the state table from one of the first number states to one of the second number of states corresponding to one of at least probable symbol passes. A coding system according to claim 46, wherein said state means increases a state according to a most probable symbol. Coding system according to claim 8 or 27 for entropy coding of data, with an index generator for generating indices based on the data, and a state table connected is a probability estimate based on the indices wherein the state table includes a number of states, wherein each of the states corresponds to a code and each code in the state table corresponds to one is repeated a predetermined number of times, being a transition between states the state table is based on an acceleration term, which is modifiable such that a first transition rate between states that while a first time period occurs, from a second transition rate while a second period of time. The coding system of claim 54, wherein the state table by modifying the PEM state by the acceleration term is incremented or decremented, is updated. A coding system according to claim 55, wherein no adaptive acceleration occurs when the acceleration term is a has a predetermined number. The coding system of claim 55, wherein the acceleration term updated on the basis of the number of consecutive codewords becomes. A coding system according to claim 57, wherein successive ones codewords successive codewords in a context. A coding system according to claim 57, wherein successive ones codewords successive codewords in a probability class. The coding system of claim 55, wherein the acceleration term is updated based on the number of alternating codewords. Decoding system with entropy decoder for decoding a data stream of entropy coded codewords, with a number Bitstream generators for receiving the data stream, and one State table associated with the number of bitstream generators is a probability estimate to the number of bitstream generators the number of bitstream generators being decoded Result for each codeword in the data stream according to the probability estimate Help of a Rn (k) code for generates multiple values of n, and further wherein the state table a first number of states and a second number of states contains and transitions between States transitions between Codes match, with transitions between different codes in the first number of states occur faster than transitions between Codes in the second number states. A decoding system according to claim 61, wherein the first number of states each contains an R2 (k) code. A decoding system according to claim 61, wherein the first number of states only during an initialization is used. An entropy decoder decoding system for decoding a data stream of entropy coded codewords, comprising a plurality of bitstream generators for receiving data from the data stream, and a state table coupled to provide probability estimates based on the indices, the state table including a number of states, wherein each of the states corresponds to a code and each code in the state table is repeated a predetermined number of times, transitioning between states of the state table based on an acceleration term that is modifiable such that a first transition rate between states during a first time period is different from a second transition rate during a second time period. The decoding system of claim 61, wherein each one Code in the state table repeated a constant number of times becomes. A decoding system according to claim 65, wherein the State table by modifying the PEM state by a Acceleration term is updated. A decoding system according to claim 66, wherein no adaptive acceleration occurs when the acceleration term is a has a predetermined number. The decoding system of claim 66, wherein the Acceleration term based on the number of consecutive codewords is updated. The decoding system of claim 66, wherein the Update acceleration term based on the number of alternating codewords becomes. Decoding system with entropy decoder for decoding a data stream of interlaced entropy coded words, with one Sliding unit for variable lengths for recording the data stream and for moving codewords output correctly aligned coded data, wherein the disk unit for variable Lengths one Has number of registers, a run length decoder compatible with the Sliding unit for variable lengths is connected to the properly aligned, encoded data as codewords for determining the codeword type; a probability estimation module, which is connected to the run-length decoder is to get the code for the run-length decoder to determine, so the run-length decoder a run length and an indication is generated as to whether the LPS corresponds to each codeword occurred. A decoding system according to claim 70, wherein a Part of the number of registers connected to data from one others of the number of registers or of the data stream. A decoding system according to claim 70, wherein the Sliding unit for variable lengths a barrel shift unit to retrieve data from the data stream to move to the number of registers. A decoding system according to claim 70, wherein the Sliding unit for variable lengths a FIFO having a number of registers, each of the registers Data as an input from the interleaved coded data absorbs, and at least one of the number registers is connected, around codewords from another of the number of registers. A decoding system according to claim 70, wherein the Sliding unit comprising: a first number of registers connected is to code words each of the first number of registers having a particular one Stream codewords generated; a multiplexer connected to codeword data from each of the first number of registers as an input and codewords from one of the number of streams to deliver at a certain time; one tonne sliding unit, which is connected to the output of the multiplexer to codeword data from the multiplexer for shift output as aligned coded data; a Logic that is connected to the shift unit by a number of bits to move the codeword, and a FIFO with a number of registers connected to code words of the multiplexer, the FIFO having a number of registers contains wherein each of the plurality of registers receives data as an input from the interleaved coded data, and at least one of the Number of registers is connected to code words from another of the Record number of registers. An entropy decoder decoding system for decoding a data stream of entropy-coded data, comprising a FIFO structure connected to receive the data; a context model for providing contexts; a memory associated with the context model for storing state information and providing state information in response to any context provided by the context model; a number of decoders connected to receive coded data from the FIFO structure, and the are connected to the memory to decode codewords supplied from the FIFO structure using state information from the memory, the number of decoders being provided so that iteration numbers for a number of codes can be generated. The decoding system of claim 75, wherein the FIFO structure coded data to the number of decoders independent of Supplies context and probability class. A decoding system according to claim 75, wherein the Decoder memory for storing for pass counts points to pass counts to store on the basis of a probability class is accessible. The decoding system of claim 75, wherein the FIFO structure data for two of the number of decoders creates. The decoding system of claim 75, wherein the FIFO structure has a number of output signals, one of them for each the number of decoders. A decoding system according to claim 79, wherein the FIFO structure a pair of multiplexers and a control logic for selecting the Multiplexer pairs, to ensure that a codeword supplied to each decoder is. The decoding system of claim 80, wherein the Multiplexer pair through the control logic based on requirements selected which has been obtained from one of the number of decoders. Coding system according to claim 8, wherein coded Data in one of the parallel streams based on a set Criteria. allocated with a fixed size memory, the connected to the entropy coder to the parallel streams of coded Store data storing coded data of greater importance and coded data of lesser importance are thrown away, when the memory is full size is. The coding system of claim 82, wherein the memory has a number of storage areas, and coded data stored in stored in each of the number of memory areas encoded data having a different importance level. The coding system of claim 82, wherein the memory has a number of memory areas, and in which coded Data of importance level is stored in at least one of the number of storage areas are that store coded data of another importance level. A coding system according to claim 84, wherein the coded ones Data of the one importance level coded data of the other importance level in which at least one of the number of memory areas overwrite. Method for initializing a number of contexts in a method for coding according to one of the patent claims 1 to 7 or in a coding system according to one of the claims 8 to 60, with the following steps: Specifying an initial PEM state; Receive a PEM state of a current one Context, wherein the step of obtaining comprises the steps of: Access to a location for the current one Context to the present to receive assigned PEM state; Determine if the storage location valid is by a current one Context number for the current context with a counter value which is intremented when in any context is accessed, the currently assigned PEM state as valid is set when the counter value indicates that the memory location has already been initialized; Use of the initial PEM state for the current one Context and ignore a currently assigned PEM state for the gegewärtigen Context if PEM data of the accessed memory location is not valid, and Using the present assigned PEM state for the current one Context if the PEM data is valid are. The method of claim 86, further comprising the step having: Writing a new PEM state when the Changed PEM state Has. Decoder with a context model, to use context boxes or Create context bins; a memory associated with the contextual model is connected to create probability states based on the context bins; a logic associated with memory, to probability classes to generate on the basis of the probability states; one Decoder connected to the logic to generate a number of Release signals based on the probability classes produce; a number of bit generators connected to the decoder are connected and are provided to receive the encoded data, wherein each of the number of bit generators is for at least one different one or own code is determined and in response to a different or own the number of enable signals works, the Decoder one of the number of bit generators based on a current probability class releases to cause one of the number of bitstream generators the encoded data decodes that of the current probability class assigned. A decoder according to claim 88, wherein at least one of the number of bit generators decodes data using an R code, and at least one of the plurality of bit generators, data having a non-R code decoded. A decoder according to claim 88, wherein at least one of the number of bit generators handles short runlengths and as an R-code decoder is working. A decoder according to claim 88, wherein at least one of the number of bit generators handles long runlengths and a short one Running unit and a long running unit, wherein the short Run unit codes of a first predetermined length treated and the long run unit handles any remaining bits and determines which, if any, are to be output from the remaining bits. Method for decoding parallel entropy-coded-reordered Data comprising the steps: Providing a context tray; Provide a number of bit generators; Accessing a memory with the help of the context box, a probability state to obtain; Generating a probability class on the Base of the probability state; Releasing a specific one Bit generator of the number of bit generators depending on the determined probability classes, wherein each of the number of bit generators is different for at least one Code is determined so that only the one different code is used for decoding, and one of the number of bit generators decodes the encoded data. Coding system according to one of the claims 8 to 60, with: a context model to provide context fans; one memory associated with the context model to probability states the base of the context fans to accomplish; a logic associated with memory, to probability classes to generate on the basis of the probability states; and one encoder coupled to the logic to provide a number of enable signals to generate on the basis of the probability class; one Number of bit generators connected to the encoder to the Input data, each of the number of bit generators at least for a different code is determined, the encoder a the number of bit generators based on a current probability class releases so that the one of the number of bitstream generators input data encoded, the current one Probability class are assigned. An encoder according to claim 93, wherein at least one of the number of bit generators encodes data with an R code and at least one of the number of bit generators data using a Non-R codes coded. An encoder according to claim 93, wherein at least one of the number of bit generators handles short runlengths and as an R-code encoder is working. An encoder according to claim 93, wherein at least one of the number of bit generators handles long runlengths and a short one Running unit and a long running unit, wherein the short Run unit codes of a first predetermined length treated and the long run unit handles any remaining bits and determines which, if any, are to be output from the remaining bits. Method for coding a data stream after a of the claims 1 to 7, which has the steps: Providing a context tray; Access to a memory using the context box, to a probability state to obtain; Generating a probability class on the Base of the probability state; Releasing a one Number of bit generators used for at least one different or own code is determined, so that only one uses its own code for coding becomes; and one of the number of bit generators is the input data coded. The method of claim 92 entropy coded for decoding Data comprising the further steps: Provide a Run counter for entropy decoding; Loading a count into a counter that every run counter is assigned, wherein the count value the size of one used codeword memory during coding corresponds when a new pass is started, where the count is loaded when a new code word is retrieved for each pass counter; decrement the count, every time a codeword is called, and Delete one Bit generator state associated with the new codeword when the counter decremented to zero. The method of claim 98, wherein each pass counter is one Assigned PEM state is. The method of claim 98, wherein each pass counter is one Context box is assigned. The method of claim 92 entropy coded for decoding Data comprising the further steps: Provide a counter; incrementing of the counter value each time a codeword is requested, where the counter value a present one Has time display; Storing the counter value as a stored one Time display when a first code word is started; to compare the stored time display plus the size of an encoder memory with the current time display; and Clear a bit generator state for the first codeword and requesting a new codeword when the current Time display is larger as the stored time indication plus the size of the encoder memory. The method of claim 101, wherein the stored Time display has a timestamp. The method of claim 101, wherein the stored Time display for a subsequent one Codeword is used again. The method of claim 92 entropy coded for decoding Data comprising the further steps: Save a Index corresponding to a codeword, where the index is in a queue is stored when the codeword is requested; To mark the entry of the index in the queue is invalid; Save the code word in the entry and marking the entry as valid when the codeword is complete; and Output data from the queue, following these steps having: Outputting data from the queue entry and displaying, that the data to the decoder is invalid when the queue entry as invalid is marked and the codeword is prematurely completed, the decoder Deletes bit generator state information, in response thereto, that it receives data from the queue that marks invalid are. A decoder for decoding coded data, comprising: a context modeling mechanism for providing contexts, the context modeling mechanism having a number of integrated circuits; a memory coupled to the context modeling mechanism for storing state information, wherein the memory provides state information corresponding to each context provided by the context modeling mechanism and a number of decoders connected to the memory for supplying code words from the memory using the state information wherein the number of decoders decodes codewords using a number of R-codes, the number of R-codes being operable to encode at least one non-maximum round-trip of most probable symbols on which a least likely symbol does not follow. A decoder according to claim 105, wherein pass counts not maximum length a uniquely decodable prefix or have a clearly decodable intent. A coding system according to claim 17, wherein a Bit generator state of the bit generator is updated after carried out a biter production and in which also the bit generator before completion reusing the updating of the bit generation state, which is written to the memory. A coding system according to claim 107, wherein the Bit generator during the modifier stage of a read-modify-write cycle is used. A coding system according to claims 8 to 16, wherein the bit generator generates a pass count of non-minimal length, if he has to write an updated state on the Memory is reused. A coding system according to claim 16, wherein the Bit generator encodes data using R codes defined as such are that on any run length at least one uncoded bit follows, thereby preventing two codewords same run length be decoded one after the other. A decoding system according to claim 75, including one Context modeling mechanism for providing contexts; one memory associated with the context modeling mechanism for storage state information, wherein the memory is state information corresponding to each of the context modeling mechanism Context creates, and a number connected to the memory Decoder for decoding codewords by means of the state information from the memory, wherein at least one of the number of decoders has a delay-tolerant Decoder has. The system of claim 111, wherein at least one of the number of decoders has a variable-length shift performs the basis of decoded data available after a delay. The system of claim 111, wherein each of the Number of decoders receives variable length data. The system of claim 113, wherein the number Decoder decode parallel-input variable-length data. The system of claim 111, wherein an output signal the number of decoders is divided into nested fixed length words becomes.