DE19520962C1 - Two-dimensional discrete real-time cosine transformation circuit or cosine reverse transformation circuit - Google Patents

Abstract

A 2-D DCT/IDCT circuit comprises a rate buffer, a multiplexer, a one-dimensional DCT/IDCT processor, a transpose buffer and an inverse rate buffer. The data input rate of the rate buffer and the output rate of the inverse rate buffer are a first rate, while the transform process, which is carried out between the rate buffer and the inverse rate buffer by the 1-D DCT/IDCT processor, is at a second rate. Since the second rate is approximately two times the first rate, the 2-D DCT/IDCT circuit can satisfy the requirement of high speed operation. Moreover, since the 2-D DCT/IDCT circuit according the present invention provides a specific arrangement of the order of input/output data, the hardware structure is simplified, thereby making it easy to realize in a VLSI circuit. The circuit carries out a 2-D DCT/IDCT by passing the data through the 1-D DCT/IDCT twice, transposing it in between.

Description

The invention relates to a two-dimensional discrete real-time cosine transformation (DCT) or cosine reverse trans formation circuit (IDCT), which implements in particular in a highly integrated circuit (VLSI) can be.

Because of the ever larger amounts of data, data compresses have in image processing sion process attained great importance. In these procedures, the coding and the Data transformation is always the most difficult part. The complex code or Transfor Mation algorithm must namely be implemented in a circuit, which mostly only unsuccessful. For data coding in video systems is because of the orthogonal Transformation process often uses DCT / IDCT processing. There is therefore a great need for a fast, real-time capable, two-dimensional DCT / IDCT circuit, that meets the requirements of international video standards, for example the joint picture Expert Group (JPEG), the Motion Photography Expert Group (MPEG) and according to H.261.

There are two-dimensional DCT / IDCT scales for continuous input and output data in which two one-dimensional DCT / IDCT processors are connected in series. If you need a greater transformation performance, then a two-dimensional one could directly Transformation algorithm to be implemented in the circuit. Unfortunately, this is not feasible: the hardware design would be too complicated and the scope of the circuit too large. Therefore, almost all conventional two-dimensional DCT / IDCT circuits are based (see US-A-4, 791, 598 and US-A-5, 249, 146) on a structure in which two one-dimensional Processors are connected in series.

EP 0 566 184 A2 describes image processing in which one line alternates one Block and a column of the product elements of the previous block transformed will. The columns are broken down in parallel. The transformation is done by fixed Multiplier. DE 37 19 628 A1 teaches a method for two-dimensional discrete inverse Cosine transformation, in which the input values to be transformed into two on top of each other following transformers can be machined one-dimensionally. This procedure will preferably used for the recovery of magnetically stored spectral values.  

Fig. 1 is a two-dimensional DCT / IDCT circuit shows two-dimensional Prozesso ren. For a two-dimensional transformation, the DCT / IDCT circuit leads aufeinanderfol quietly two one-dimensional DCT / IDCT processings. The circuit comprises a one-dimensional DCT / IDCT processor 15 , a transpose buffer 16 , a further one-dimensional DCT / IDCT processor 17 and a further transpose buffer 18 . In the one-dimensional DCT / IDCT processors 15 and 17 , two one-dimensional DCT / IDCT processing of a matrix X and its transposed Z are carried out. In order to keep the output data in the correct order, two transpose buffers 16 and 18 are provided for swapping the row and column elements of the matrices. There are two similar processing stages in the circuit of FIG. 1. That is, the operation of the first stage, which consists of the one-dimensional DCT / IDCT processor 15 and the transpose buffer 16 , is similar to the operation of the second stage, which consists of the one-dimensional DCT / IDCT processor 17 and the transpose buffer 18 . The smallest possible circuit scope can therefore be achieved by establishing a feedback loop from the transpose buffer 16 to the one-dimensional DCT / IDCT processor 15 and by omitting the components of the second stage, namely the one-dimensional DCT / IDCT processor 17 and the transpose buffer 18 . Since the circuit mentioned has two processing stages, the processing time is too long for real-time processing. That is, despite the smaller circuit size, the circuit of FIG. 1 is not suitable for the high speed needs of video systems.

It is therefore an object of the invention to have a faster, real-time capable, two-dimensional To provide DCT / IDCT circuit, which is particularly for data-reducing Image processing in video systems is suitable.

This object is achieved by a two-dimensional DCT / IDCT circuit according to claim 1 solved. Preferred embodiments of the invention result from the subordinate sayings.

The two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to the invention comprises
a speed buffer suitable for inputting NxN data at a first speed and outputting the data at a second speed;
a multiplexer suitable for providing a data path for data transmission from a first data path and a second data path, the first data path being provided for the data from the speed buffer during a first period of time and the second data path being provided for transposed data during a second period of time;
a one-dimensional DCT / IDCT processor suitable for performing a one-dimensional DCT / IDCT on the data from the data paths of the multiplexer;
a transpose buffer suitable for transposing the data from the one-dimensional DCT / IDCT processor, the transpose buffer generating the transposed data and storing it for forwarding to the multiplexer; and
an inverse speed buffer, suitable for acquiring the data coming from the transpose buffer and transformed in the second dimension during the second period at the second speed, and for outputting the transformed NxN data at the first speed.

The invention thus provides a two-dimensional DCT / IDCT circuit that goes to high speed data transformation from components operating at different speeds stands to meet the real-time requirement. The data entry rate of the Speed buffer and the output rate of the inverse speed buffer one first speed. On the other hand, the transformation process that the one-dimensional nale DCT / IDCT processor between the speed buffer and the inverse Ge speed buffer takes place at a second speed. Because the second Speed is approximately twice the first speed, the two-dimensional DCT / IDCT circuit meet the requirements of high speed fulfill drive.

Since the two-dimensional DCT / IDCT circuit according to the invention also has a provides a special arrangement of the order of the input or output data, the hardware structure is simplified and it can be easily integrated into a VLSI circuit will. The invention therefore also provides a two-dimensional DCT / IDCT circuit smallest possible components ready to reduce the circuit dimensions and that Ease to implement in a VLSI circuit.

The invention will now be described with reference to the accompanying drawings. Same Reference numerals designate identical parts. It shows:  

Fig. 1 is a block diagram of a conventional two-dimensional DCT / IDCT circuit;

Fig. 2 is a block diagram of a two-dimensional DCT / IDCT circuit according to the invention;

Fig. 3 is a diagram of the temporal assignment of the input and output data of the rate buffer in Fig. 2;

FIG. 4 shows a diagram for the temporal assignment of the input and output data of the multiplexer in FIG. 2;

Fig. 5 is a diagram of the temporal assignment of all the components of the circuit in Fig. 2;

FIG. 6 shows a diagram for the temporal assignment of the input and output data of the inverse speed buffer in FIG. 2;

FIG. 7 shows a circuit diagram for explaining the speed buffer in FIG. 2.

Fig. 2 shows the two-dimensional DCT / IDCT circuit according to a preferred embodiment of the invention. The circuit comprises a speed buffer 10 , a multiplexer 11 , a one-dimensional DCT / IDCT processor 12 , a transpose buffer 13 and an inverse speed buffer 14 .

The circuit has an input data matrix X and an output data matrix Y. Is the matrix X is an NxN matrix with, for example, N = 8, the input data matrix can be represented as

Thus, the output matrix is also an NxN matrix, i.e. that is, the matrix Y can be represented as

Therefore, the input data of the speed buffer 10 can form a one-dimensional sequence from the matrix X, for example a row sequence X₀₀, X₀₁, X₀₂, X₀₃, X₀₄, X₀₅, X₀₆, X₀₇, X₁₀, X₁₁, X₁₂, X₁₃,. . ., X₂₀, X₂₁,. . ., X₇₀, X₇₁, X₇₂, X₇₃, X₇₄, X₇₅, X₇₆und X₇₇. The output data from the inverse speed buffer 14 can also be a one-dimensional sequence of Y₀₀, Y₀₁, Y₀₂, Y₀₃, Y₀₄, Y₀₅, Y₀₆, Y₀₇, Y₁₀, Y₁₁, Y₁₂, Y₁₃,. . ., Y₂₀, Y₂₁,. . ., Y₇₀, Y₇₁, Y₇₂, Y₇₃, Y₇₄, Y₇₅, Y₇₆ and Y₇₇ form.

All of the components of the two-dimensional DCT / IDCT circuit of the invention are as follows explained.

The speed buffer 10 in the invention provides a data input rate at a first speed and a data output rate at a second speed. That is, the input data sequence mentioned is the input into the speed buffer 10 via the port 10 a at the first speed. The speed buffer 10 then outputs a rearranged data sequence to the multiplexer 11 at a second speed. The second speed is preferably twice the first speed. The different data input and data output rates can be achieved by applying driver signals with different frequencies to the input end and the output end of the speed buffer 10 . A double-fast transformation process can therefore be achieved within the two-dimensional DCT / IDCT circuit according to the invention.

The multiplexer 11 provides two data paths for data transmission. A first data path 11 b is provided for the rearranged input data sequence from the speed buffer 10 . This data path is active for a first period. When a one-dimensional transformation of the input data matrix X has ended, a second time period begins. The multiplexer 11 provides a second data path 11 a instead of the first data path, suitable for transferring another data sequence from the transpose buffer 13 .

The one-dimensional DCT / IDCT processor 12 is a double-speed IxN processor, the processing time of which is not greater than 2N-1. For example, if N is 8, a maximum processing time of 15 clock cycles is required. Furthermore, the throughput rate of the one-dimensional DCT / IDCT processor 12 is approximately equal to the second speed. The data transmitted through the data paths of the multiplexer 11 are transformed in the one-dimensional DCT / IDCT processor 12 . The structure of the one-dimensional DCT / IDCT processor 12 has been disclosed in several articles and publications and is known to those skilled in the art so that it is not described here.

The transpose buffer 13 has the size NxN. The data transformed by the one-dimensional DCT / IDCT processor 12 are stored in the transpose buffer 13 during the first period. The stored data, which are referred to as matrix Z, are transposed into a further data matrix Z ^t . The matrices Z and Z ^t are in one-dimensional format like the sequence from matrix X, see above. During the second period, the matrix Z ^{t is sent} to the one-dimensional DCT / IDCT processor via the second data path 11 a of the multiplexer 11 .

As with speed buffer 10 , a data input rate at the second speed and a data output rate at the first speed must be consistent with the inverse speed buffer 14 . During the second time period, data from the one-dimensional DCT / IDCT processor 12 are stored in the inverse speed buffer 14 and then output as a data matrix Y at the first speed. The different data input and data output rates can be achieved by applying driver signals with different frequencies to the input end and the output end of the inverse speed buffer 14 .

Together with the representations of the temporal profiles of FIG. 3 to FIG. 6, the operation of the two-dimensional DCT / IDCT circuit according to the invention will now be described with reference to a case of the game, whose input data and output data have the size of 8 × 8.

Reference is first made to FIG. 3. The temporal relationships between the input data and the output data of the speed buffer 10 are explained together with a reference time coordinate whose time unit scale is 1 / f. The second line in Fig. 3 shows the time sequence of the input data sequence from the matrix X. In order to prevent Since tenkonflikte, the rate buffer 10 outputs via the first data path 11 b data only to the multiplexer 11 from after the first 56 elements of the input data sequence have been saved. This means, as can be seen in the second and third lines of FIG. 3, that the first element X₀₀ of the sequence is only sent from the speed buffer 10 when the element X₇₀ of the input data sequence is being stored in the speed buffer. Obviously, in the drawing, the data input rate f is half the output rate.

Reference is now made to FIG. 4. It explains the temporal relationships between the first data path 11 b and the second data path 11 a of the multiplexer 11 . During the first period of time, data from the rate buffer 10, ie, the sequence consisting of X₀₀ to X₇₇, b transmitted via the first data path 11, and outputted to the one-dimensional DCT / IDCT processor as the first and third lines in Fig. 4 show. After consisting of X₀₀ to X₇₇ sequence has been outputted to the one-dimensional DCT / IDCT processor 12, the first data path 11 b is closed, whereas the second data path 11 a is provided for the follow-up Z₀₀ Z₇₇. Comprising Z₀₀ to Z₇₇ sequence from the transpose buffer 13 is transmitted during the second time period via the second data path 11 to a one-dimensional DCT / IDCT processor 12, as the second and third lines in Fig. 4 show.

In the invention, the one-dimensional DCT / IDCT processor 12 receives input data at the input port 12 a in the arrangement X _0c , X _1c , X _2c , X _3c , X _4c , X _5c , X _6c and X _7c during the first period, c runs from 0 to 7. The input data are transformed and output to the transpose buffer 13 . In contrast, in the second time period is the data sequence Z _R0, Z _R1, Z _R2, Z _R3, Z _R4, Z _R5, Z ₆ and Z _R7 R from 0 to 7 from the transpose buffer 13 via the second data path 11 a in the one-dimensional DCT / IDCT processor 12 input to generate an output data string Y _R0 , Y _R1 , Y _R2 , Y _R3 , Y _R4 , Y _R5 , Y _R6 and Y _R7 , where R runs from 0 to 7.

FIG. 5 is a timing diagram illustrating the relationships of the X, Y and Z sequences between the output from the speed buffer 10 and the input to the inverse speed buffer 14 . The first line in FIG. 5 shows the temporal position of the data sequence from X₀₀ to X₇₇ from the speed buffer 10 . As the third line shows, the data sequence is sent by the multiplexer 11 to the one-dimensional DCT / IDCT processor 12 . After an execution time delay, the output data of the transformation in the first dimension are written from the one-dimensional DCT / IDCT processor 12 as a sequence from Z₀₀ to Z₇₇ in the transpose buffer 13 . At the beginning of the second period, the one-dimensional DCT / IDCT processor 12 reads the sequence from Z₀₀ to Z₇₇ for the transformation in the second dimension, as the second line in FIG. 5 shows. The inverse speed buffer 14 then takes over the last output sequence from Y₀₀ to Y₇₇ from the one-dimensional DCT / IDCT processor 12 , as the last line in FIG. 5 shows.

The inverse speed buffer 14 outputs the last data sequence of the two-dimensional DCT / IDCT circuit, ie the sequence from Y₀₀ to Y₇₇, at the first speed.

Reference is now made to FIG. 6. The first line represents a reference time coordinate. The temporal position of the input data and the output data of the inverse speed buffer 14 are also explained. The reference time coordinate has a time unit scale of 1 / f. The sequence consisting of Y₀₀ to Y₇₇ is obviously entered into the inverse speed buffer 14 at a frequency of 2f, ie at the second speed. In contrast, the data output from the inverse speed buffer 14 takes place at the frequency f, that is to say the first speed. Since the output rate of the inverse speed buffer 14 and the input rate of the speed buffer 10 are the same, see FIG. 3, the input-output timing of the two-dimensional DCT / IDCT circuit can be kept consistent.

In order to obtain the various data input and data output rates, the speed buffer 10 and the inverse speed buffer 14 in the invention can be dual-port devices. For example, a static dual-port memory with random access (SRAM, SRAM = Static Random Access Memory) can be used as the speed buffer 10 , see FIG. 7.

Reference is now made to FIG. 7. Two counters 101 and 103 are provided , each of which is connected to the input port and output port of the dual-port SRAM 102 . The counter 101 , which is controlled by a write enable signal Bwrite, is clocked by a clock signal ckf, which has the frequency f. However, the counter 103 is clocked instead of the signal ckf by a signal ck2f which has a frequency of 2f. The counter 103 is controlled by a read enable signal Bread. By controlling the address signals Wa and Ra from the counters 101 and 103 , the dual-port SRAM 102 can read the sequence X at a first speed and output the sequence X 'at a second speed. Since the wiring between the counters and the input-output ports of the dual-port SRAM 102 can be set up as desired, there can be various address modes. In other words, the output sequence and input sequence need not be in the same order. Inverse speed buffer 14 may also include a dual port SRAM and two counters. In contrast, the signals that clock the input and output counters have an inverse frequency ratio compared to the speed buffer 10 .

The double-speed operation of the two-dimensional DCT / IDCT circuit enables real-time transformation to be obtained. Compared to the conventional circuit of FIG. 1, the speed buffer 10 and multiplexer 11 are also provided in the invention to replace the function of the one-dimensional DCT / IDCT processor in the second stage. Because the circuitry of a one-dimensional DCT / IDCT processor is approximately ten times that of a speed buffer together with a multiplexer, the circuitry of the invention can be greatly reduced and the hardware design is much simpler. The invention is therefore more suitable for VLSI implementation.

Claims (14)

1. Two-dimensional, discrete, real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT), comprising:
a speed buffer ( 10 ) adapted to input NxN data at a first speed and output the data at a second speed;
a multiplexer ( 11 ), suitable for providing a data path for data transmission from a first data path ( 11 b) and a second data path ( 11 a), the first data path ( 11 b) for the data from the speed buffer ( 10 ) during a first Time period is provided, the second data path ( 11 a), however, is provided during a second time period for transposed data;
a one-dimensional DCT / IDCT processor ( 12 ), suitable for executing a one-dimensional DCT / IDCT on the data from the data paths ( 11 a, 11 b) of the multiplexer ( 11 );
a transpose buffer ( 13 ) adapted to transpose the data from the one-dimensional DCT / IDCT processor ( 12 ), the transpose buffer ( 13 ) generating the transposed data and storing it for forwarding to the multiplexer ( 11 ); and
an inverse speed buffer ( 14 ) suitable for acquiring the data coming from the transpose buffer ( 13 ) and transformed in the second dimension during the second period at the second speed, and for outputting the transformed NxN data at the first speed. 2. Two-dimensional discrete real-time cosine transformation circuit (DCT) or The cosine reverse transform circuit (IDCT) of claim 1, wherein the second Speed is twice the first speed. 3. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the one-dimensional DCT / IDCT processor ( 12 ) is a double-speed DCT / IDCT processor whose throughput rate is not less than the second Speed. 4. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the Ge speed buffer ( 10 ) is equipped with different address modes for the NxN data. 5. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the inverse speed buffer ( 14 ) is equipped with different address modes for the transformed NxN data. 6. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein two drive signals with different frequencies are provided for the input and output of the data of the speed buffer ( 10 ). 7. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein two drive signals are provided with different frequencies for the input and output of the data of the inverse speed buffer ( 14 ). 8. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein for the input and output of the data of the speed buffer ( 10 ) two counters ( 101 , 103 ) are provided with different processing speeds. 9. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein two counters with different processing speeds are provided for the input and output of the data of the inverse speed buffer ( 14 ). 10. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the Ge speed buffer ( 10 ) comprises a dual-port device. 11. Two-dimensional, discrete, real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the inverse speed buffer ( 14 ) comprises a dual-port device. 12. Two-dimensional discrete real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the speed buffer ( 10 ) contains a static dual-port memory ( 102 ) with random access (SRAM). 13. Two-dimensional, discrete, real-time cosine transformation circuit (DCT) or cosine reverse transformation circuit (IDCT) according to claim 1, wherein the inverse speed buffer ( 14 ) comprises a dual-port SRAM. 14. Two-dimensional discrete real-time cosine transformation circuit (DCT) or A cosine inverse transform circuit (IDCT) according to claim 1, which is a processor tion time of less than 2N-1 clock cycles of the second speed.