DE10300329A1 - Direct sequence spread spectrum collision detection multiple access transmission involves associating pseudorandom sequence code states to signal depending on counter, pseudorandom sequence modulation - Google Patents

Abstract

The method involves clock synchronization of a data signal with a pseudorandom sequence in the transmission branch by detecting an edge of a data signal, starting a counter on detecting an edge, associating individual code states of the sequence to the data signal depending on the counter state with subsequent modulation of the data signal using the pseudorandom sequence. AN Independent claim is also included for the following: (a) a programmable logic component, especially an ASIC or FPGA, for implementing the inventive method.

Description

The invention relates to a method for clock synchronization and clock recovery with direct sequence spread spectrum (DSSS) CDMA transmission method.

Spread spectrum or spreading method have in the past few years in digital communications increased Gained importance. They point to conventional transmission methods a number of advantages, including the possibility of multiple access by code division, an increased noise immunity and the possibility for message veiling.

Under the spread spectrum procedure is the direct sequence method (DS) the best known and most widely used; it is also under the term direct spread or pseudo-noise method known. Generally understands one under DS modulation the modulation of a digital data signal on a carrier a digital code sequence whose bitrate is much higher as that of the data signal. In other words, every single one Data bit sequential with one of zeros and ones so-called pseudorandom sequence (pseudorandom noise code or PN code) logically linked, their total length exactly the length must correspond to a data bit.

In CDMA methods, the signals that pass through a Radio channel run, not by time slots or frequency bands but exclusively separated by the choice of suitable PN codes. This offers the Advantage that the available Bandwidth can be better used and a larger number Participants can be granted access to the transmission medium. With this measure let yourself use a frequency band of 5 MHz simultaneously of several hundred channels.

An appropriate circuit will be for example, in "Erich Stadler, modulation method, 7.Auflage, 1993, Vogel, Würzburg "presented.

For a trouble-free data transfer Here is the synchronization of the pseudorandom sequence with the data signal an indispensable requirement; d. H. the respective starting times of pseudo-random sequences temporally with the edge changes of the data signals, ie with the Start times of the individual data bits, coincide.

In the case of fluctuations in the periodicity of the data signal and thus changing length single data bits, so-called jitter, this synchronicity is lost. As a result, the information on the receiver side no longer recover from the received signal.

So far, these become necessary Synchronization of the data signals with the pseudorandom sequence in the transmission branch of transmission systems so-called clock recovery blocks used. These lead the Clock of the incoming data and use it for synchronization the pseudorandom sequence with the data signal. This procedure works but from a certain intensity of the jitter in the data signal no longer reliable and impaired thus the robustness of the data transmission. About that In addition, the necessary circuitry is extremely expensive and needs one certain settling time.

It is the object of the invention robust, cost-effective DSSS-CDMA transmission method to disposal to deliver.

This task is performed by a transmission method with those in the independent Claim 1 described features or by a logic device solved with the features of claim 6. Advantageous embodiments The invention are the subject of the dependent claims.

The method according to the invention is based on that and falling edges of the data signal are detected and at each edge change a counter is started.

For each edge of the data signal is the start of the corresponding pseudorandom sequence intended. About that It is also desirable the synchronicity the pseudo-random sequences with the data signal via a Sequence of the same bit states to hold the data signal. For this purpose, the phase position of the data signal should constantly be known. The phase position of the data signal can be calculated from the count derived.

As in 1 For example, using an 8-bit pseudorandom sequence, the counter starts at zero and ends at seven. The individual elements of the pseudo-random sequence, the so-called chips, are set depending on the count. Each count represents the beginning of a chip. Each count also corresponds to the position of a chip within the pseudorandom sequence. In the event that the frequency of the data signal fluctuates or a bit is partially transmitted incorrectly by a fault, the synchronicity of the pseudorandom sequence with the data signal is only briefly lost. At the onset of the next edge of the data signal, the counter is restarted and the synchronization of the pseudorandom sequence with the data signal is reestablished.

For a better understanding are two cases distinguished:

• (a) The error-free case In error-free Case is the counter at each edge change of the data signal at an integer Multiples of the code length, ie the number of bits of the pseudorandom sequence used. Of the Restart of the counter falls at a flank change with the restart of the counter at Reaching the code length together and thus does not affect.
• (b) The faulty case Consider the case of a shortened data bits for a PN code length of 8 bits. For example, the end of the data bit and thus the edge change of the data signal already takes place at a count of 5 instead of at a level of 7. The edge detection triggers the counter immediately to a restart, and already at the next data bit is the synchronicity of the data signal with the PN code restored. Without this procedure, the synchronicity would be lost and the following data bits would be incorrectly coded.

This procedure according to the invention shows different advantages. For example, is unnecessary when using the inventive method the use of a clock recovery module, which starts at one certain intensity of the Phase noise no longer works reliably and the other requires a certain settling time.

Unlike conventional methods in the method according to the invention in the case of errors in the data signal, the synchronization is not regularly lost.

The method thus allows the Minimization of the influence of phase noise in the flanks of the Data signal and allows a robust data transmission with high phase noise.

In a further advantageous embodiment Use of a transmission system variable data rate becomes another advantage of the invention clear. Here, preferably, the code length is kept variable to the Bandwidth of the transmission channel fully exploit. The length of the individual bits of the pseudorandom sequence, the so-called chip length for all codes used are equal and correspond to the reciprocal of the available bandwidth.

With variable bit length the Data signals corresponds to the optimal code length the ratio of data bit length to chip length. Of the counter can now in conjunction with the edge detector in an advantageous manner be used to determine the current bit length and the associated code length.

Each time the counter is reset, the yes, at each edge change takes place, the associated meter reading given to a circuit for code selection. The meter reading here corresponds to the optimal code length to use. The code selection circuit includes a memory in which for each bit length of the matching code is deposited. Then the circuit takes one Selection of the appropriate code before, which from then on to the modulation with the Data signal is used. Thus, a circuit can be realized be opposite Code change is particularly robust.

The method described is based on the in 2 illustrated flowchart further clarified.

On the receiving side it is so desirable, recognize the code used on the transmitting side.

In an advantageous embodiment The invention is the recipient when the data rate changes, the new code that will be used soon e.g. about communicated the data channel directly. This allows the code selection on the receiver side without further analysis of the radio signal can be done quickly.

If this is not possible, preferably in the following described circuit can be used:

Located in a CDMA receiver There is already a correlator, which the correlation function between the received signal r (t) and a code c (t) present in the receiver generated. The correlation function yields correlation values which depend on the time shift z of the received signal r (t) with respect to c (t) are.

If the same code c (t) is used in the receiver, as it was already used in the transmitter, results for the time shift T of the received signal r (t) a high maximum at which the code c (t) and the code modulated on each data bit in the transmit branch is synchronized are.

Is the code c (t) different in the receiver from the code contained in the received signal, it follows a much lower correlation maximum.

At the receiving end, the code length (and thus also the code) are now varied so long, over one longer Data sequence detected a suitable value for the correlation maximum becomes.

In this way, the one to be used in the receiver Code c (t) can be determined.

For example, in a learning sequence in a counter the code length L from the smallest stored code of length L1 to the longest code the length L2 counted up become.

In a code selection, each code length is the Memory address of a code assigned to this length, whereupon this Code is used in the correlator. For each code length is now the correlation maximum over averaged several bits of the data sequence. The averaging increases the signal-to-noise ratio for the Detection of the correlation maximum. Is for a certain code length (namely the used in the transmitting branch) the highest Value of the correlation maximum reached, then this value and the one for that needed code length stored. The achieved correlation maximum can continue used to set a decision threshold, which serves to detect the data bits. The correlation maximum came for too an evaluation of the dynamics of the transmission path (e.g., for a level control) can be used.

After the learning sequence, which in the initialization phase (phase of the preparation of the data ver binding), the counter for the subsequent data traffic can be set to this stored optimal code length. The found code, which reached the maximum correlation value, will be used for further correlation in the receiver. If there is a change in the data rate and thus the code length in the transmitter, then the learning sequence described above is restarted on the transmitter side. Since the code c (t) now differs from the new code contained in the received signal, the value of the correlation maximum decreases dramatically. In the receiver, the beginning of a new learning sequence is detected and started a new counting process.

Because the learning sequence used for each Data rate performed only once must become, is the simplest and the poorest solution the counting up of the code length from the minimum value to the maximum value and the determination of the case reached maximum correlation value. Also an embodiment of Learning sequence in the form of a control loop is basically conceivable.

The method described is based on the in 3 illustrated flowchart further clarified.

In addition, it is advantageous for the transmission of zeros and ones to use different PN codes because thus the wiretapping security of the system leaves; however, it is then in the reception branch of the transmission system to provide a second, parallel correlator.

A particularly advantageous variant of the method is that the logic of the modulation the pseudorandom sequence in the transmission path in programmable logic devices such as Field Programmable Gate Arrays (FPGA's) can be realized. Thus, a flexible adaptation of the logic via software interfaces allows.

Also when using ASIC's (for a specific Application optimized semiconductor devices), the process is clear the code length and The data rate can be flexibly adapted at any time by exchanging the ASICs.

Claims (6)

CDMA-DSSS transmission method, wherein the clock synchronization of a data signal with a pseudorandom sequence contains the following steps in the send branch: Detection of a flank of the data signal - Begin a counter upon detection of a flank - Assignment of individual code states of the Pseudorandom sequence to the data signal as a function of the counter reading with following Modulation of the data signal with the pseudorandom sequence. transfer process according to claim 1, characterized in that it has a variable data rate and with the help of the counter the for the particular data rate to be used code length is determined. transfer process according to claim 2, characterized in that each time the data rate is changed the soon to be used to transfer new code becomes. transfer process according to claim 2, characterized in that varies in the reception branch, the code length , values of a correlation function are determined for each selected code length and due the values of the correlation function of the code used in the transmitter is determined. transfer process according to one of the preceding claims, characterized in that for the Encoding zeros and ones uses different codes become. Programmable logic device, in particular ASIC or FPGA with an embossed Program to carry out of the preceding claims described transmission method.