DE10248982B4 - Device and method for monitoring the current consumption of a circuit arrangement - Google Patents

Abstract

Device (10) for monitoring a current consumption (Iq) of a circuit arrangement (12) connected between a first and a second potential, wherein the circuit arrangement (12) has a first and a second voltage supply connection (12a, 12c), having the following features:
a capacitor (18) connected in parallel with the circuit (12) to be monitored;
a switch (16) for disconnecting the parallel circuit of circuit (12) to be monitored and capacitance (18) from the first potential, the switch (16) being controllable by a switching signal (S1) having a first and second switching state, the switch (16) is closed at the first switching state and is open at the second switching state; and
means (20; 20, 28, 30) for monitoring the potential on the side of the parallel circuit separate from the first potential, the means for monitoring comprising a comparator (20) for detecting a voltage difference between a voltage (U ' ₁ ) at the first power supply terminal (12a) and a reference voltage during the second ...

Description

The The present invention relates to circuit tests for examination and review of functionality of electronic circuits, and more particularly to a device and a method of monitoring the current consumption of an electronic circuit to a possible Determine errors of the electronic circuitry.

A increasingly important class of integrated circuits (ICs; IC = integrated circuit) is called "mixed signal circuits" (mixed signal circuits) designated. By this one understands integrated circuits, which itself from both analog and digital circuits for processing composed of analog and / or digital signals.

Under a digital circuit generally understands a circuit, the digital signals are processed, with digital signals in turn characterized in that they only certain discrete values can accept. In particular, the so-called. "Binary logic" is widespread, with two logical states or levels, d. H. with a so-called. Logically high ("HIGH") and a so-called. logic low ("LOW") level, comes from.

The vast majority of digital circuits are being implemented in CMOS (complementary metal oxide semiconductor) (CMOS) logic circuits today, since CMOS structures are particularly easy to miniaturize, and thus extremely complex systems are extremely versatile accommodate small chip area. In the case of the CMOS logic, the two logic states "HIGH" and "LOW" are represented, for example, by corresponding voltage values V _CC and V _SS , the voltage value V _{CC being,} for example, a supply voltage value of 5 V and the voltage value V _SS a reference voltage value of 0, for example V (ground potential) corresponds.

A specific feature of CMOS logic circuits is that they do not consume any appreciable power in the static case, since CMOS logic circuits show no significant power consumption in the static state when the clock signals do not change, ie when all signals and clock signals are "frozen". This is the case since in a transistor chain between the supply voltage V _CC and ground potential V _SS in each static, logic state, at least one CMOS transistor of the chain blocks.

by virtue of unavoidable leakage currents occurs in reality but a small static current consumption of CMOS circuits on. leakage currents arise due to currents, which flow across pn-semiconductor junctions, though a lower potential at the p-type semiconductor region than at the n-type semiconductor region and also due to unavoidable subthreshold currents, i. H. Streams over the channels of MOS transistors, though whose gate-source voltages are below the threshold voltage (sub-threshold) lie.

in the dynamic case, d. H. in the normal operating state of CMOS circuits, if the signals change over time, have to unavoidable stray capacities of lines against the substrate from a low logic level "LOW" to a high level logical level "HIGH" and conversely from "HIGH" to "LOW", so that for a short time relatively large Current pulses per switching operation of the digital CMOS circuits flow.

typical digital circuits implemented in CMOS technology For example, logic gates such as AND, invertor, NAND, NOR, OR, XOR gates, and devices built with these digital circuits such as multiplexers, decoders, as well as flip-flop elements, Counter.

in the In contrast, analogue circuits process analogue signals, which are not quantized and thus real-valued. Typical analog Circuits are, for example u. a. Operational amplifiers, power supplies, Power sources and analog multipliers.

typical Mixed signal circuits are now especially such circuits, the one conversion of an analog signal into a digital signal as well conversely, a conversion of a digital signal into an analogue one Accomplish signal. Such circuits will be accordingly as analog-to-digital converter (ADC = analog digital converter) or accordingly as a digital-to-analog converter (DAC).

In addition, many ASIC (Application Specific IC) devices are associated with this type of circuit. Often, while an analog input signal is digitized, digitally processed, z. B. by a digital filtering, and then fed to a microprocessor system. Occasionally, an analog input signal is also digitized for further processing only to be subsequently converted back to an analog output signal. Numerous sensor ASIC arrangements, for example, for a magnetic field, pressure or Temperature sensing used in industrial or automotive applications may be assigned to the range of "mixed signal circuits".

In purely digital switching systems, and in particular in very large scale integration (VLSI) digital circuits, a test procedure has been known for some time, referred to as the I _DDq test method, the abbreviation for the English term "direct drain quiescent current ".

The I _{DDq test} method has been used in recent years particularly to improve the quality of CMOS chip. Certain errors in the circuitry may exist in CMOS technology, but their presence does not alter the functionality of the circuit under test. However, a large part of these errors can be detected by a current test, the so-called I _DDq test. In such a current test, the leakage current of the power supply is measured in a CMOS circuit to determine if excessive cross-current is flowing, indicating a fault in the CMOS circuit.

However, there are certain difficulties in using the I _{DDq test} method because an I _{DDq current} threshold must be determined to distinguish a faultless from a faulty circuit, and it must be ensured that the I _DDq current is sufficient for a faultless circuit is low to distinguish it from an I _DDq current of a faulty circuit.

The I _{DDq current} threshold, ie, the cross current limit, for an I _{DDq test} operation is often determined experimentally by measuring the I _DDq current values of a large number of faultless and a large number of faulty circuits, whereupon a suitable I _DDq threshold _{current is} selected which would detect as many faulty circuits as possible without affecting (too many) healthy circuits.

In an I _{DDq test} method, the circuit _under test is operated in the static state, with its current consumption being measured. Now is the current consumption of the circuit under test in the static state too high, z. B. greater than a limit of 0.05 mA, this indicates a defect of a component, for. B. a transistor out, which should actually lock, but still passes due to a process error. With this I _{DDq test} method, a large number of faulty integrated circuits can already be detected and rejected during a wafer test.

In the so-called mixed-signal systems, an I _{DDq test} method has hitherto not been applicable, since even with a faultlessly functioning digital CMOS circuit part of the analog circuit part often has a considerable power consumption of mostly several milli-ampere. Therefore, a possibly present small leakage current of the digital circuit part can not be distinguished from this large supply current of the analog circuit part, so that a possible process error of the digital circuit part will remain undetected.

Further, since the analog circuit part includes numerous power supplies which are also provided to power the digital circuit part, in most cases, it is not possible to easily turn off the analog circuit part for the I _DDq test method. This is especially true for such integrated circuits, which are to be used for example in the automotive sector, since it is there that due to the high demands on the EMC strength (EMC = electromagnetic compatibility) and the overvoltage and Verpolfestigkeit the supply voltage of the digital circuit part must be stabilized and regulated by extensive analog circuit blocks.

For wafer test purposes, therefore, an additional test pad (test pad) is generally attached so that one can turn off and completely disconnect the analog circuit portion from the digital circuit portion, with the digital supply voltage applied across the test pad. The I _DDq current to be detected is then also detected via this test pad.

A disadvantage of this approach, however, is that it is only applicable to the wafer test, since the test pad is not bonded and thus is no longer available after housing the integrated circuit in a housing. Therefore, it is _impossible to perform an I _DDq test, in particular during operation of the integrated circuit. Moreover, the sensitivity of the I _{DDq test} systems previously used in the prior art is limited because conventional I _DDq test _systems respond only to relatively high I _DDq cross currents.

The patent (US-5,694,063) relates to a circuit for monitoring the quiescent current of a device under test. For this purpose, a reference current I _{REF is} first fed into a first node, wherein the power supply device is decoupled from the first node by means of a switch. The first supply terminal of the device under test is connected to the first Node connected, wherein the second supply terminal is connected to ground potential. After the power supply device has been decoupled from the first node, the voltage at the first node is now determined at a first time. The voltage at the first node is then determined a second time at a later time. If the voltage at the first node has increased between the first and second times, this is an indication that the power _{supply bias} current I _{DDQ of} the device under test is lower than the reference current. If the voltage at the node decreases between the first time and the second time, this is an indication that the power supply quiescent current of the device under test is greater than the reference current, and thus there is too much power supply quiescent current. The voltage at the first node 215 is evaluated by means of a comparator, the result of the comparator being passed to a tester to judge whether the device under test passed or failed the I _DDQ test.

The patent ( DE 19782246 T1 ) refers to an IC tester that measures the current flowing from a power source to an integrated semiconductor circuit element formed by a MOS-type circuit, to thereby determine whether the element has a defect or not.

outgoing from this prior art, the object of the present Invention therein, an improved, generally applicable concept for monitoring to provide the current consumption of a circuit arrangement, regardless of the type of circuitry during its operation steadily carry out an accurate recording and assessment of the current consumption can.

These The object is achieved by a device for monitoring a current consumption a circuit arrangement according to claim 1 or 3 and by a method for monitoring a current consumption a circuit arrangement according to claim 23 or 25 solved.

The inventive device for monitoring a current consumption of a between a first and a second potential switched circuitry includes a capacitor that is parallel to the one to be monitored Circuit arrangement is connected, a switch for disconnecting the Parallel connection from to be monitored Circuitry and capacity from the first or second potential, and means for monitoring of the potential at the one separated from the first or second potential Side of parallel connection.

The inventive method to monitor a current consumption of a between a first and a second potential switched circuitry comprises the steps of providing a capacity parallel to the one to be monitored Circuit arrangement is connected, the separation of the parallel circuit to be monitored Circuitry and capacity from the first or second potential, and monitoring the potential the side of the parallel circuit separate from the first or second potential.

Of the The present invention is based on the knowledge, the power consumption an electronic circuit arrangement, for. B. a digital circuit part, to monitor by the circuitry either at its positive or negative Supply voltage connection preferably during a static state the same by means of a switch of the positive and negative Supply voltage is disconnected, the instantaneous supply or operating voltage of the circuit arrangement stored on a capacitor which is parallel to the monitored Circuit arrangement is arranged, and wherein at the same time possibly changing Voltage over monitors the capacity which is on a possible Indicates fault current of the circuit arrangement.

at a first preferred embodiment the present invention, the current consumption of an electronic Monitored circuit arrangement, by the ones to be monitored Circuit arrangement by means of the switch from the supply voltage is disconnected to the currently applied supply voltage of the Circuit arrangement over to store a capacitor arranged parallel to the circuit arrangement and at the same time the possibly changing voltage curve over the capacity to monitor.

During the normal operating state of the circuit is the switch initially closed, whereupon the scarf ter who to interrupt or connect the Supply voltage to the circuit arrangement is provided during the Test interval open is to the circuitry of the supply voltage source to disconnect and to establish the test state of the circuit arrangement, So that the Circuit arrangement only of the stored on the capacity Charge is supplied.

there It should be noted that the monitoring the current consumption of the circuit in a so-called. Static Condition of the same performed should be. This means, if it is a digital circuit part, the current monitoring should only between two consecutive clock edges of the clock signal be executed if the current peaks caused by the clock edges sufficient have subsided, d. H. the digital circuit part after the respective clock edge is in the static state.

The Tension over the capacity but remains during of the test interval only at a substantially constant Value if the capacity is in essentially not discharged. More precisely, in the static Condition should be the current consumption of the circuit in error-free State smaller than a specific adjustable limit for example, about 0.05 mA, in which a corresponding dimensioned capacity only slightly unloaded. However, if the circuitry is faulty, a relative flows high cross-flow, the capacity, d. H. the charge stored on it, discharges relatively quickly, so that thereby the tension over the capacity breaks down, the supply voltage of the circuit arrangement in the test interval represents.

This increased drop in the supply voltage of the circuit is determined by a comparator, z. B. a comparator, detected as early as possible, the comparison means as a result of indicating an error, relatively high voltage drop across the capacitance an error signal, which is also referred to as so-called. I _DDq error signal outputs. This error signal can then be suitably further processed by a suitable evaluation device.

The earliest possible detection of an error state by the monitoring _device according to the invention is advantageous in order, for example, to be able to react quickly to such an I _{DDq error} state of a digital CMOS circuit by outputting a logic signal, for example a high logic level, at the output of the comparison device is to close the switch as quickly as possible, and thus to prevent the voltage that is above the capacity and thus represents the supply voltage of the circuit part, even further and thus possibly too strong breaks.

at a further preferred embodiment the device according to the invention for monitoring a current consumption of a circuit arrangement, the comparison device, further preferably an RS flip-flop element, that of the comparator circuit is followed, wherein stored in the RS flip-flop element, the error signal is reset by the error signal with a logic high level at the Set input (SET) of the RS flip-flop element is present. During the test condition of the Circuit arrangement is the reset input (RESET) of RS flip-flop element at a low logic level (LOW). The RS flip-flop element now gives a signal at its Q output with a high logic level when the comparison signal has a has a logic high level, which is also supplied to an OR gate. The Oder Gate now gives a switching signal for the switch off, which closes the switch as quickly as possible and thus prevents the voltage from over the capacity which represents the supply voltage of the circuit, too strong breaks.

It would be extremely unfavorable if the supply voltage of the circuit arrangement breaks down so much that, for example, a digital circuit part loses information stored in its flip-flop elements. Therefore, the combination of comparator circuit, RS flip-flop element, OR gate and switch must be as fast as possible, ie have a high bandwidth and a small response time. However, since the speed of the above-mentioned control loop is naturally limited, it is further advantageous to bridge the switch by two antiparallel diodes so that the potential across the capacitor can never deviate from the supply voltage of the circuit by more than one diode forward voltage. Thus, the supply voltage of the circuit arrangement is ensured even with very abrupt changes in the potential at the supply line of the circuit, wherein at the same time a (digital) error signal (I _DDq signal) is generated which indicates too high a cross-flow from the supply line of the circuit to ground and thus triggers an I _DDq alarm.

Corresponding a further preferred embodiment The present invention can be the concept of the invention for monitoring the current consumption of an electronic circuit arrangement to the effect be modified that the Circuit arrangement by means of a switch from the negative supply voltage, for. B. ground potential, is separated, again the currently applied Supply voltage of the circuit arrangement via a parallel to the circuit arrangement arranged capacitor monitored becomes. This fault current test is preferably also during a static state of the circuit to be examined performed.

In this further preferred Ausfüh For example, when the capacitor is discharged, the potential to be monitored at the circuit node formed by the first switch connection, the second supply voltage connection of the circuit arrangement and the second connection of the capacitance increases, since this circuit node is activated during the fault current test on the basis of FIG is disconnected from the negative supply voltage and the first terminal of the capacitor is kept at the potential of the positive voltage supply. This circuit node is to evaluate the monitoring potential with a comparator, z. B. a comparator connected.

The potential increase at this circuit node should also be detected as early as possible in this embodiment, wherein the comparison means an error signal, ie the I, as a consequence of a pointing to an error, relatively high voltage rise at this circuit node corresponding to the voltage drop across the capacitor due to the fault current _{DDq error} signal, outputs. This error signal can then be appropriately further processed by a suitable evaluation device.

By means of the device according to the invention or the method according to the invention for monitoring a current consumption of a circuit _arrangement , it is now possible to carry out an I _DDq test even during operation of the circuit _{arrangement in} order to be able to detect as early as possible all types of fault which are caused by a static cross-flow ( _FIG . Iq) between a high digital voltage level (V _CC , supply voltage) and a low digital voltage level (V _SS ; Due to the concept according to the invention, therefore, the continuous operation of the functionality of an integrated circuit can significantly increase the operational reliability of an electronic module.

The inventive concept can be, for example so that the user of one with the inventive concept equipped electronic system the need for a service the electronic system is displayed, in which one then, for example can replace the defective electronic module. It is further also possible, that the integrated circuit in case of error only one for one Service technician easily outputs measurable, unique error signal, so that the service technician can locate the error very quickly can and then, for example, a particular affected electronic component or exchange the entire electronic module targeted can.

Particularly advantageous is the inventive concept for monitoring a power consumption of a circuit arrangement on EEPROM circuits (EEPROM = electrically erasable programmable read-only memory = electrically erasable and programmable read-only memory) and in particular to CMOS EEPROM circuits applicable, as for example in the German patent application DE 102 14 898 A1 A key feature of such CMOS EEPROM circuits is that, in the case of critical failure modes thereof, ie, all failures in which charge is lost from the floating gate region of the corresponding transistor, which is to lock in the perfectly programmed state, an undesirable cross-flow of a high logic level V _CC sets to a low logic level VS _S. If this error mode, ie the discharge, detected in time, Thus, the charge loss can be detected in time before the EEPROM circuit loses the value of the stored bits, so that advantageously an undesirable loss of information can be prevented.

It should be noted that the inventive concept for monitoring a current consumption of a circuit arrangement, ie the inventive I _DDq system, of course, also applicable to other known EEPROM architectures, in which context, for example, to the European patent application " EP 0756328 A2 Motorola, INC., entitled "Non-volatile memory cell having a single polysilicon gate" and U.S. Patent No. "US-6,028,789" entitled "Zero-power CMOS non-volatile memory cell having an avalanche injection element" of Vantis Corporation.

The concept _{according to} the invention, ie the inventive I _DDq system, is furthermore advantageously usable not only during the wafer test of an integrated circuit but also during the final test of the integrated circuit. The final test is performed after the integrated circuit has been mounted in its housing. Therefore, the possibly provided for the wafer test, the above-mentioned test pads (test pads) are no longer accessible, whereby the inventive concept for monitoring the power consumption of a circuit _arrangement (I _DDq test) can be used extremely advantageous.

The concept _{according to} the invention, ie the I _DDq system _{according to} the invention, can also be used extremely advantageously during operation of the integrated circuit, wherein during the loading For example, in the automotive field, precautions must be taken to prevent EMC disturbances and short supply voltage drops, which are up to about 1 μs long and are referred to as micro-breaks, incorrectly outputting of the I _DDq alarm signal. Furthermore, it is extremely advantageous that the inventive I _DDq system in the case of EMC interference and brief dips in the supply voltage, the functioning of the entire integrated circuit is not additionally impaired, as is avoided by the inventive monitoring concept that the integrated circuit due to the invention I _{DDq -Systems} already shows at lower EMC interference or EMC influences impairment of functionality than would be the case without the inventive I _DDq system.

In summary, it can be stated that the I _DDq system according to the invention is extremely advantageous in that it can not only be used during the wafer test, but that the I _DDq system is available during the entire operation of the integrated circuit to be monitored. In addition, the sensitivity of the I _DDq system _{according to} the invention is greater than in conventional systems, ie it already responds to smaller I _DDq cross currents, since the I _DDq system _according to the invention can be _implemented completely integrated and thus smaller parasitic effects, ie leakage and leakage currents, stray capacitances, etc., as must be accepted in conventional I _DDq test systems.

The inventive concept for monitoring However, the power consumption of a circuit arrangement can also on the monitoring the current consumption of circuits other than digital CMOS circuits be applied. For example, a relatively high power consumption assumed a circuit arrangement, so you have only the Time duration while the switch is in an open state, sufficiently short choose and at the same time the capacity value of the capacitor sufficiently large, thus a current drain not too big Voltage drop at the over The capacitor voltage applied leads. The comparator threshold is also set insensitive, so that the comparator output For example, only then goes to a logic high level, if the potential at its inverting input a predetermined high value below that potential at the non-inverting input sinks. They are natural any scaling in practice limits.

preferred embodiments The present invention will be described below with reference to FIG the enclosed drawings closer explained. Show it:

1 a device for monitoring a current consumption of a circuit arrangement according to a first embodiment of the present invention;

2 a device for monitoring a current consumption of a circuit arrangement according to another preferred embodiment of the present invention;

3 various typical waveforms during the monitoring of the current consumption of a circuit arrangement to illustrate the operation of the monitoring device according to the invention; and

4 a device for monitoring a current consumption of a circuit arrangement according to another preferred embodiment of the present invention.

Before Referring now to the figures preferred embodiments of the present invention be discussed in more detail it is noted that same or functionally identical elements in the figures with the same or similar Reference numerals are provided, and that to avoid repetition a new detailed explanation of this Elements is avoided.

Referring to the 1 and 3 Now, a preferred embodiment of the present invention for monitoring a current consumption of a circuit arrangement will be discussed in detail.

As in 1 is shown, is the monitoring device according to the invention 10 between a circuit arrangement 12 , z. B. a digital circuit part, and a power supply device 14 , z. B. an analog circuit part, the voltage supply to the circuit 12 is provided switched.

The circuit arrangement 12 includes a first port 12a , a second connection 12b and a third connection 12c , The first connection 12a the circuit arrangement is preferably a supply voltage input for receiving a positive supply voltage, the second connection 12b is preferably a clock signal input of the circuit arrangement 12 , and the third connection 12c is preferably a second supply voltage input for receiving a negative supply voltage or for application to ground potential.

The monitoring device 10 includes a switch 16 , with a first switch connection 16a , a second switch terminal 16b and a control input 16c , a capacitor 18 with a first capacitor connection 18a and a second capacitor terminal 18b , a comparison device 20 with a first entrance 20a , a second entrance 20b and an exit 20c , and a logic element 22 with a first entrance 22a , a second entrance 22b and an exit 22c ,

The first switch connection 16a of the switch 16 is with the power supply 14 connected, wherein the second switch terminal 16b of the switch 16 with the supply voltage input 12a the circuit arrangement 12 connected is.

The first capacitor connection 18a of the capacitor 18 is with the second switch port 16b of the switch 16 connected, wherein the second capacitor terminal 18b of the capacitor 18 with a reference potential connection, z. B. a ground potential terminal connected.

The first entrance 20a the comparison device 20 is with the second switch port 16b of the switch 16 connected, the second input 20b the comparison device 20 with the first switch connection 16a of the switch 16 connected is. The exit 20c the comparison device 20 is with the first entrance 22a of the logic element 22 connected. At the second entrance 22b of the logic element 22 is applied a test signal φ1, which is exemplified as waveform II in 3 is shown. The exit 22c of the logic element 22 is with the control input 16c of the switch 16 connected. The clock signal input 12b the circuit arrangement 12 is connected to a clock signal φ2, which is exemplified as a waveform I in 3 is shown.

The following will now be based on 1 and 3 the functioning of in 1 illustrated device 10 for monitoring a current consumption Iq of the circuit arrangement 12 discussed in detail. To simplify the understanding of the operation of the monitoring device according to the invention 10 Reference is further made to various typical waveforms I-V, the during the monitoring of the current Iq a circuit arrangement 12 typically can occur.

How out 1 can be seen supplies the power supply device 14 the supply voltage U1 for the electronic circuit arrangement 12 which is, for example, a digital CMOS circuit.

During the normal operating state of the circuit 12 is the switch 16 closed, so that the power supply device 14 and thus the supply voltage U1 directly to the circuit arrangement 12 connected is. During the test state T _{IDDq of} the device 10 for monitoring the current consumption I _{q of} the circuit arrangement 12 , for example, by the test signal φ1 (see the waveform II of 3 ) is the switch 16 between his first switch connection 16a and its second switch port 16b open, leaving the circuitry 12 from the power source 14 is disconnected and thus the supply voltage U1 of the circuit arrangement 12 as the voltage curve U ' ₁ on the capacitor 18 is stored. The capacitor 18 However, the stored supply voltage U ' ₁ can hold only at a relatively constant voltage value when the capacitor 18 is not discharged by cross currents Iq. Because even in the faultless, static state of the circuit 12 a slight current consumption of, for example, less than or equal to 0.05 mA is present, the capacitor 18 slightly discharged, so that a "real", falling voltage curve U ' ₁ over the capacitor 18 results. The capacity 18 However, in the error-free state of the circuit 12 due to the very low current consumption I _q only relatively slightly discharged and thus the real voltage curve U ' ₁ only slightly decrease.

Should be a fault in the circuit 12 present, flows a relatively high cross-flow I _q , the capacity 18 relatively strong discharges. This breaks the supply voltage of the circuit arrangement 12 , ie the capacitor voltage U ' ₁ , a relatively strong. This voltage change is made by the comparator 20 , which is preferably carried out by a comparator circuit, detected as early as possible, wherein at the output 20c the comparison device 20 an I _DDq signal having a high logic level is output when the voltage difference ΔU between the supply voltage U1 and the voltage U ' ₁ across the capacitor 18 exceeds a predetermined threshold due to a fault in the circuitry 12 suggesting.

The earliest possible detection of a relatively high dip in the voltage U ' ₁ across the capacitor 18 is advantageous in that now can respond quickly to this voltage dip by responding to the output signal from the output 20c the comparison device 20 the desk 16 can be brought back to the closed state. As in 1 is shown, is the first input 22a of the logic element 22 with the exit 20c the comparison device 20 connected, the second input 22b of logic elements 22 is connected to the test signal φ1.

The logic element 22 puts at its exit 22c a switching signal S1 for the control input 16c of the switch 16 ready. The logic element 22 is preferably formed as an OR gate, of course, other correspondingly functional logic circuits are conceivable.

The desk 16 is thus controllable by the switching signal S1, wherein the switching signal S1 may have a first and a second switching state, and wherein the switch 16 is closed at the first switching state of the switching signal S1 and is open at the second switching state of the switching signal S1. Because the logic element 22 as already mentioned, preferably formed by an OR gate, the switching signal S1 of the switch 16 by an OR operation of the output signal (I _DDq signal) of the comparison _device 20 and the test signal φ1, therefore, the switching signal S1 has a logic high level HIGH when either the I _DDq signal or the test signal φ1 has a high logic level. The switching signal has a low logic level LOW only when both the output of the comparator circuit 20 , ie, the I _DDq signal, as well as the test signal φ1 simultaneously have a logic low level.

From the test waveform φ1, as he as waveform II of 3 is shown, and from the above functional description of the device for monitoring the current consumption of the circuit arrangement 12 it is clear that the switching signal S1 only has a low logic level, and thus the switch 16 in an open state when the test signal φ1 has a low logic level during the I _DDq test and also the comparator 20 no "excessive" voltage reduction of the voltage U ' ₁ across the capacitor 18 detected, which could affect or even impair the functionality of the circuit.

It would be extremely unfavorable if the supply voltage U ' _{1 of} the circuit arrangement 12 that _passed through the capacitor during the I _DDq test 18 is provided so far breaks that this voltage dip may be in logic elements of the circuit 12 could cause a loss of information. Therefore, the inventive combination of the switch 16 which is designed, for example, as a simple transistor switch, the comparison device 20 , which is designed for example as a comparator circuit, and the logic element 22 , which is designed as an OR gate, for example, be as fast as possible, ie have a high bandwidth and a small response time.

The signal III of 3 For example, _{FIG. 12} shows the resulting history of an I _DDq signal during a test cycle T _{IDDq of} the present invention as determined by the _{method of FIG} 1 shown inventive arrangement for monitoring a power consumption of a circuit arrangement can result. In the following it will now be explained in detail how the waveform IV in 3 represented I _DDq signal comes about.

In 3 is shown as waveform I an exemplary clock signal φ2, for example, the clock signal input 12b the circuit arrangement 12 is supplied, wherein the circuit arrangement 12 for example, is designed as an integrated, digital CMOS circuit part. In the case of the logic transitions from "0" to "1" (from LOW to HIGH) and the logic transitions from "1" to "0" (from HIGH to LOW) of the clock signal φ2, large cross-currents I _q flow for a short time Signal curve III of 3 are shown in principle, which inevitably to the breakdown of the voltage U ' ₁ to the capacitor 18 The switch should lead 16 remain open, and thus to a high level of the I _DDq signal at the output 20c the comparison device 20 That would lead to an I _DDq error alarm.

Is the circuit arrangement 12 For example, as a clocked logic circuit executed, as will be the case in the vast majority of (digital) circuitry, it is necessary that the test signal φ1 and the clock signal φ2 are synchronous to each other, the test signal φ1 only a low logic level 0 "(LOW) may be assumed if all charging currents or cross-currents I _{q of} the circuit arrangement (eg CMOS logic) have decayed sufficiently from the preceding clock edge of the clock signal φ 2 the test signal φ1 has a low logic level "0" (LOW). If the circuit arrangement to be monitored, ie, for example, a digital CMOS circuit part, contains only synchronous logic at a low or medium clock frequency, the above-mentioned requirements are comparatively easy to observe in practice.

In the case of an asynchronous logic or at very high clock frequencies, ie when half the period lasts approximately as long as the charging currents generated per clock edge, the above-mentioned requirements may possibly not be achievable in practice. In this case, for example, for the duration of the observation period, ie during the I _{DDq test} window T _IDDq at which the test signal φ1 has a low logic level (LOW), it is possible to slow down or even stop the clock signal φ2.

Now it is assumed that the circuit arrangement 12 , which is formed in the present embodiment, for example, as a digital circuit part properly functioning, there is in static operation, ie between two clock edges of the clock signal φ2 no significant cross-current I _q from the high potential V _CC to the low potential V _SS . During normal operation of the circuitry 12 becomes the switch 16 usually remain closed for the most part and only be opened sporadically during the test window T _IDDq to perform an I _DDq test. For this purpose, the duty cycle or the relative switch-on time duration of the test signal φ1 is set such that the test signal φ1 has a high logic level "1" (HIGH) for about 90% of the time and only a low logic level "0" for about 10% of the time. (LOW), so that the duty cycle is thus about 90% (= 0.9).

It should be noted, however, that these duty cycle values are to be considered as exemplary only, with in practice, depending on the application, values for the duty cycle of the test signal which are greater than 0.5 and preferably in a range around 0.9, suitable could be. It is merely to be noted that on the one hand, the operation of the circuit to be monitored by the I _DDq tests essentially not affected and on the other hand, the I _DDq test should not be affected by the inevitable cross-currents of the circuit under investigation substantially.

As long as the test signal φ1 has a logic high level "1" (HIGH), the switch 16 closed, since the switching signal S1, which is generated by the logical combination of the test signal φ1 and the I _DDq signal, the closed state of the switch 16 causes. This will be the circuit arrangement 12 from the power supply 14 low-resistance supplied with the supply voltage U1. The term "low impedance" in this context means that the internal resistance of the power supply 14 is low impedance. Also, the relatively low resistance of the switch 16 in the on state, which is often designed as a p-type MOS transistor, for example, increases the internal resistance of the power supply device 14 , ie the voltage source, not worth mentioning. The capacity 18 serves in this operating state in general as the usual stabilizing capacity of the supply voltage U1. At the condenser 18 Therefore, the supply voltage U1 is applied. If the test signal φ1 changes from a logic high level "1" (HIGH) to a logic low level "0" (LOW), then the switching signal S1 changes with the switching state of the switch 16 is controllable, the switch 16 now open for the I _DDq test. On the condenser 18 Now stay over the capacitor 18 applied voltage U ' _{1 is} initially "frozen" (stored) by switching the switch 16 will this voltage U ' ₁ as a result of a voltage division occurring in practice between the capacitance 18 and a plurality of parasitic stray capacitances (not shown) of the switch constructed as a switching transistor 16 change a little bit, but these inaccuracies of tension can be kept negligible.

Thus, the comparison means executed as a comparator circuit 20 For example, equipped with a so-called hysteresis, which should be greater than these inaccuracies anyway. In addition, the comparator circuit is preferably designed so that at the output 20c the I _DDq signal has a low logic level, provided there is no significant voltage difference ΔU between the first 20a and the second 20b Input of the comparator 20 , ie the comparator circuit, is present. Thus, the switch remains 16 open.

If in the further consequence the capacity 18 is not significantly discharged, the conditions change, ie the logical states of the individual components of the monitoring device 10 until the test signal φ1 returns to a high logic level "1" (HIGH) and ends the I _DDq test 16 about the logic element 22 , ie via the switching signal, brought into the closed state.

Next, it is now assumed that the circuit arrangement 12 during a static state of the clock signal pulls an excessively high cross- _current I _q (I _DDq ), causing the capacitance 18 is discharged as soon as the switch 18 is open. So goes the test signal φ1 to a low logic level "0" (LOW), and thus opens the switch 18 , so diminishes at a constant cross-current I _q in the circuit arrangement 12 hence the voltage U ' ₁ across the capacitor 18 according to the following relationship: U ' 1 = U1 - Iq × t / C1, such that: ΔU = U1 - U ' 1 = Iq × t / C1, where U ' _{1 is} the voltage across the capacitor 18 with the switch open 16 is, the voltage U1 is the initial value of the voltage across the capacitor 18 at the time of opening the switch 16 is, the current Iq the cross-current of the circuit 14 and time t is the time since the time the switch was opened 16 is.

Now drops the voltage U ' ₁ at the capacitor 18 sufficiently strong, this is done by the comparator 20 detected in the form of a comparator circuit, whereby the output 20c the comparison device 20 has a high logic level "1" (HIGH) for a short time This duration is defined as the time duration ΔT _{1 of} the signal curve IV of FIG 3 shown in principle. Because the output 20c the comparison device 20 with the first entrance 22a of the logic element 22 is connected, which is preferably formed as an OR gate, is also the switch 16 immediately (very quickly) by the switching signal S1 of the logic element 22 closed. This loads the power supply 14 the capacity 18 again quickly to the supply voltage U1, so that the circuitry 12 in turn is operated with its regular supply voltage U1.

From the in 3 illustrated exemplary waveform IV of the I _DDq signal at the output 20c the comparison device 20 For example, the logical state of the I _DDq signal can now be evaluated with an evaluation _device in order to obtain information about the current consumption Iq of the circuit arrangement 12 hold true.

As with the waveform IV of 3 is shown, for example, during the test window T _IDDq also from the time t _{0 of} the occurrence of a signal _{edge of} the I _DDq signal and the duration .DELTA.T _{1 of} the I _DDq signal qualitative statements about the discharging and recharging the capacitor 18 and thus be taken over the cross-current Iq, since for example from the time t _0, the time duration .DELTA.T ₀ between the beginning of the I _DDq test window and the occurrence of the signal _{edge of} the I _DDq signal can be determined, and thus with knowledge of the capacitance _{value of} the capacitor 18 and the supply voltage U1 of the voltage supply device 14 can be determined using the above formulas, the faulty cross-current Iq.

From the above in connection with 1 It will be appreciated that in a preferred embodiment of the present invention, the second input 20b the comparator circuit 20 representing the non-inverting input thereof with the supply voltage U1 of the power supply 14 connected is. It should be noted, however, that this input of the comparator circuit 20 can also be associated with a differently obtained reference voltage. It is important only that the comparator circuit 20 receives a reference voltage, when falling below, ie when the at the first input 20a the comparator circuit 20 applied voltage U ' ₁ at the second input 20b applied reference voltage falls below, at the output 20c an output signal I _DDq having a defined logic level (HIGH) is output. The reference voltage is advantageously in a context with the circuit to be examined 12 , so that it is ensured that at the latest when the real supply voltage U1 'is so small that the proper operation of all elements of the circuit 12 is at risk, the comparator circuit 20 switches and thus closing the switch 16 initiates.

It should also be noted that in 1 a monitoring _device is shown, which only as an output signal I _{DDq of} the comparator _circuit 20 provides a signal with a logic high level when the real supply voltage U ' ₁ falls below a predetermined limit in the form of the reference voltage. It is also possible to use the monitoring device 10 to modify that output 20c the comparator circuit provides a logic high level as soon as the real supply voltage U ' ₁ exceeds a predetermined limit. This can be achieved, for example, by the first (inverting) input 20a and the second (non-inverting) input 20b the comparator circuit 20 be reversed. This makes it possible, for example, to detect EMC interference.

Thus, for example, a development of the invention in 1 shown monitoring device 10 consist in using two comparator circuits simultaneously, which respond to both a lower and to exceed a predetermined limit by a reference voltage, these signals can then be fed to a suitable logic Auswertelogik, then better EMI interference from fault or Leakage currents of the circuit arrangement 12 to be able to distinguish.

Based on 2 Now be further optional developments of the device according to the invention 10 for monitoring a current consumption of a circuit arrangement 12 shown. It should be noted that elements that match those of 1 match, again have the same reference numerals and will not be explained again in detail.

Furthermore, it should be noted that the respective optional developments, as they are based on 2 in the following, each individually or in any combined manner based on 1 shown, the first preferred embodiment may be applied to further this according to the present invention.

As in 2 is illustrated, the Vor direction 10 for monitoring the current consumption Iq of the circuit arrangement 12 now in addition a first diode 24 with a first connection 24a (Cathode) and a second connection 24b (Anode) and a second diode 26 with a first diode connection 26a (Cathode) and a second diode terminal 26b (Anode), wherein the second diode terminal 24b the first diode 24 and the first diode terminal 26a the second diode 26 with the first connection 16a of the switch 16 are connected, and wherein the first diode terminal 24a the first diode 24 and the second diode terminal 26b the second diode 26 with the second switch terminal 16b of the switch 16 are connected, so the switch 16 through the antiparallel diode pair 24 . 26 is bridged. The antiparallel diode pair 24 . 26 thus forms a limiting device for the maximum occurring voltage difference across the open switch 16 ,

The comparison device 20 further comprises a logic memory element 28 with a first entrance 28a , a second entrance 28b and an exit 28c on. The first entrance 28a of the logic memory element is connected to the output 20c the comparator circuit 20 connected. The second entrance 28b of the logic memory element 28 is connected to the test signal φ1. The exit 28c of the logic memory element 28 is with the first entrance 22a of the logic element 22 connected. The device 10 further comprises an evaluation device 30 , with a first entrance 30a , a second entrance 30b , a third entrance 30c and an exit 30d , being at the exit 30d the evaluation device 30 now the output signal I _{DDq of} the device 10 provided.

The first entrance 30a the evaluation device 30 is with the exit 28c of the logic memory element 28 and with the first entrance 22a of the logic element 22 connected. The second entrance 30b the evaluation device 30 is connected to the test signal φ1. The third entrance 30c the evaluation device 30 is connected, for example, to a reset signal φ3.

The following will now be based on the 2 in conjunction with the in 3 illustrated signal waveforms I-V, the operation of the individual optional developments of the device according to the invention 10 for monitoring the current consumption Iq of the circuit arrangement 12 shown.

As already detailed by means of 1 is discussed, is on the capacitor 18 the supply voltage U1 of the circuit arrangement 12 , z. B. a digital circuit part, in the form of a real voltage waveform U ' ₁ stored by the switch 16 , which is closed during the normal operating state, is opened to perform the I _DDq test. The capacitor 18 keeps the supply voltage U ' ₁ constant only when the capacitor 18 is essentially not discharged, since in the static state, the power consumption of the circuit 12 in the error-free state, for example, should be less than or equal to a value of about 0.05 mA. If there is a fault in the circuit 12 is present, however, flows in general, a relatively high cross-current Iq, the capacity 18 would unload relatively quickly. As a result, the supply voltage U ' ₁ breaks the circuit arrangement 12 with the switch open 16 through the capacitor 18 is provided. This voltage dip across the capacitor 18 is through the comparator circuit 20 detected as early as possible and in the logic memory element 28 , ie, preferably an RS flip-flop element, stored at the set input 28a (SET) of the logic memory element 28 a logic high level "1" (HIGH) is applied.

It is now extremely advantageous that a potential voltage dip across the capacitor 18 is detected very early in the present invention in order to respond to such a voltage dip as quickly as possible by the logic memory element 28 at its exit 28c , that is, the Q output of the RS flip-flop element, outputs a logic high level "1" representing the switch 16 closes again as quickly as possible and thus prevents the voltage U ' ₁ across the capacitor 18 and thus the supply voltage of the circuit arrangement 12 with the switch open 16 breaks down too much. It would be extremely unfavorable if the supply voltage of the circuit arrangement 12 so far breaks that the voltage dip leads, for example, that in logic elements of the circuit 12 lost information is lost. Therefore, the combination of switch 16 , Capacitor 18 , Comparator circuit 20 , Logic element 22 and logic memory element 28 be as fast as possible, ie have a high bandwidth and a low response time.

However, since the speed of this control loop is limited in practice, it is also advantageous to intervene between the circuitry 12 and the power supply device 14 to provide the limiting device of the voltage difference in order to limit the voltage difference between the reference voltage and the voltage at the second switch terminal to a maximum value in order to prevent the real supply voltage U ' ₁ not unduly heavily from the supply voltage U1 of the voltage supply device 14 neither deviates downwards nor upwards. In this context, "an impermissibly high voltage dip" can mean that elements of the circuit arrangement 12 no longer work properly, in particular, causing data loss in registers and flip-flops of the circuitry 14 as a result of overvoltage or undervoltage.

In the simplest case, the limiting device has a diode circuit comprising at least one diode, wherein the maximum value of the voltage difference is the diffusion voltage U _D in the direction of flow of the diode. Thus, the maximum value of the voltage difference is limited to a value corresponding to the value of the supply voltage above or below the diffusion voltage U _{D of} the diode corresponding to the connection of the diode.

This limiting circuit can, for example, two diodes connected in parallel parallel to the switch 16 exist, ie the switch 16 is optional through the two antiparallel connected diodes 24 . 26 bridged, so that the potential U ' ₁ on the capacitor 18 never more than a diode forward voltage, which is about 0.7 V for Si diodes, from the supply voltage U1, which is the power supply 14 provides, may differ. Thus, the provision of the supply voltage U1 is also at very abrupt changes in the potential at the supply line for the circuit arrangement 12 ensured, while a digital signal is generated, which is an excessive cross-current Iq from the supply line of the circuit 12 indicating mass and thus triggering an I _DDq alarm.

Assuming now that the circuitry 12 , z. B. a digital circuit part, works properly, there is no significant cross-current Iq to ground in static mode, ie in the range between two consecutive opposite clock signal edges of the clock signal φ2. As a rule, the switch 16 remain closed most of the time and only be opened sporadically to the I _DDq test, ie monitoring the current Iq of the circuit 12 to perform. For this purpose, for example, a test signal φ1 is provided which has a high logic level "1" (HIGH) 90% of the period and a low logic level "0" (LOW) for only 10% of the signal period, so that the so-called duty cycle , ie the duty cycle or the relative switch-on duration, of the test signal φ1 has a value of, for example, 90% (= 0.9). However, the duty cycle of the test signal φ1 can according to the application, ie the circuit to be monitored 12 essentially assume an arbitrary value, which is preferably greater than or equal to 0.5 and less than 1. In practice, the I _DDq test, if run in real time, is likely to be used only sporadically, for example, only about 0.1% of the time, which corresponds to a duty cycle of 0.999.

As long as the test signal φ1 has a high logic level, the switch is 16 closed, and the circuitry 12 is from the power supply device 14 low-resistance supplied with the supply voltage U1. The term "low impedance" in this embodiment also means that the internal resistance of the voltage supply device 14 (Voltage source) is low impedance. Also, the relatively small (negligible) resistance of the switch 16 in the on state, the switch 16 is preferably designed as a p-type MOS transistor, increases the internal resistance of the voltage supply device 14 essentially not worth mentioning.

The capacity 18 is at a closed switch 16 in general again as a conventional stabilizing capacity of the supply voltage U1 effective. At the capacity 18 Therefore, the supply voltage U1 is applied. Now goes the test signal φ1 from a high logic level to a low logic level, so the switch 16 by the switching signal S1 of the logic element 22 open, being on the capacitor 18 the supply voltage U1 remains "frozen" at first due to the switching process of the switch 16 is the voltage applied to the capacitor real supply voltage U ' ₁ due, for example, a voltage division between the capacitance 18 and a plurality of parasitic stray capacitances (not shown) of the switch implemented by a switching transistor 16 change a little, and this inaccuracy in the supply voltage can be kept negligible by appropriate measures.

The comparator circuit is equipped for this purpose, for example, with a "hysteresis", so that the switching threshold of the comparator circuit 20 in any case greater than the above-mentioned inaccuracies in the supply voltage U1 when switching the switch 16 ,

In addition, the comparator circuit 20 preferably designed so that at the exit 20c the comparator circuit 20 a signal is provided with a low logic level, provided no significant voltage difference .DELTA.U between the two inputs 20a . 20b the comparator circuit 20 is present. This is due to the setting input 28a of the logic memory element 28 (RS flip-flop element) to a low logic level, so that at the output 28c of the logic memory element 28 (Q output) continues to output a signal with a low logic level. Thus, the switch remains 16 open.

If now in the following the capacitor 18 is not significantly further discharged, the logical relationships change at the individual elements of the device 10 until the test signal φ1 returns to a high logic level. This gives the evaluation 30 for example, which is implemented as a counter, a positive clock edge, wherein at the first input 30a the evaluation device 30 a low logic level is applied.

Is the evaluation device 30 now, for example, as a bidirectional counter executed, and causes a high logic level at its input 30a the counter to increase its count, and a low logic level at this input 30a causes the counter to reduce its count, so reduces the understood as a binary count of the evaluation 30 for example, the count 1 , If the counter reading of the evaluation device was previously identical to 0, it should preferably not change, ie the evaluation device designed as a bidirectional counter 30 should preferably be overflow protected. Since the counter reading is reduced by 1 or is identical to 0, the counter reading is at the same time not identical to the maximum value which _indicates the output of the I _DDq signal at the output 30d the evaluation device 30 would cause, so that the output signal I _DDq the evaluation 30 remains at a logic low level, so that it can be seen from the outside that no I _DDq error was detected.

If, on the other hand, it is assumed that the circuit arrangement 12 in the static state draws a significant cross current Iq, the capacitor 18 over-discharge as soon as the switch 16 is open. So now goes the test signal φ1 to a logic low level and thus opens the switch 18 due to the switching signal S1 of the logic element 22 , so diminishes at a constant cross-current Iq in the circuit arrangement 12 the on the capacitor 18 applied voltage U ' ₁ according to the relationship: U ' 1 = U1 - Iq × t / C1, such that for the voltage difference ΔU: ΔU = U1 - U ' 1 = Iq × t / C1; wherein the voltage U1 is the initial value of the supply voltage across the capacitor 18 at the time of opening the switch 16 is, the current Iq the cross-current of the circuit 12 is, and the time t is the time since the time t ₀ of opening the switch 16 has passed.

Now drops the voltage U ' ₁ above the capacitor 18 strong enough, this is done by the comparator circuit 20 by an increased voltage difference ΔU between its first and second inputs 20a . 20b detected, being at the output 20c the comparator circuit 20 the signal level transitions to a high logic level when a comparator threshold, which may, for example, have hysteresis, for the voltage difference is exceeded, whereby the first input 28a of the logic memory element 28 is also occupied by a high logic level. Since at the in 2 illustrated embodiment, the logic memory element 28 is designed as an RS flip-flop element, represents the first input 28a the set input, whereby the RS flip-flop element is set, so that at the output 28c (Q output) thereof also a logic high level is applied, as indicated by the waveform V of 3 becomes clear.

Thus, however, the switching signal S1 also goes to the output of the logic element 22 that at the in 2 is executed as an OR gate, to a logic high level, so that the switch 16 immediately closed again. With the switch closed 16 charges the power supply 14 the capacitor 18 again quickly to the supply voltage U1, so that the circuitry 12 is again supplied with the intended, regular supply voltage.

Up to the next transition from a low logic level to a high logic level of the test signal φ1 changes in the logic states of the individual components of the monitoring device 10 essentially nothing.

If a bidirectional counter than the comparator 30 is used, counts the bidirectional counter at the rising edge of the test signal φ1 at the above transition from LOW to HIGH, for example, by a count of "1" up, because at the rising edge of the test signal φ1 at its input, ie the input 30a the evaluation device 30 , a logical high level is applied. If it is only a one-time count-up, in which the counter reading has not yet reached its maximum value, the output signal I _{DDq remains} at the output 30d the evaluation device 30 (the bidirectional counter) at a low logic level, so that no I _DDq alarm is output yet. However, if there is enough error in the circuitry during a sufficient number of previous clock cycles of the test signal φ1 12 indicative, excessive leakage current Iq has been detected or the error has been detected sufficiently frequently, reaches the designed as a bidirectional counter evaluation 30 ih ren maximum value, so that the output signal I _DDq at the output 30d the evaluation device 30 goes to a logical high level and thus an I _DDq alarm is output.

However, if the executed as bidirectional counter evaluation 30 is already at its maximum count, so should another count pulse with a logic high level at the first input 30a the evaluation device 30 whose counter reading does not increase any further, ie the counter should be overflow protected even after high values. Simultaneously with a counting up of executed as a bidirectional counter evaluation 30 becomes the logic memory element 28 reset, ie the RS flip-flop element is reset so that at its Q output 28c a logic low level is set, whereby the logic memory element 28 is prepared for the next I _DDq control _cycle .

Regarding the above with reference to the 1 - 2 and with reference to the waveforms I-V of 3 discussed embodiments of the device according to the invention 10 for monitoring the current consumption Iq of the circuit arrangement 12 It should be noted that also EMV pulses (EMC = electromagnetic compatibility) are connected to the capacitor 18 voltage applied U ' _{1 can} change when the switch 18 is in its open state. However, due to the small amount of time during which the switch 16 is in its open state, ie, for example, about 10% or less of the time duration corresponding to the duty ratio of the test signal φ1, and the need that only a larger number of I _DDq -single alarms designed as a bidirectional counter evaluation 30 to a maximum value, with a single _alarm by a logic high level I ^* _DDq at the output 28c (Q output) of the logic memory element 28 (RS flip-flop element) is defined, and thus can trigger an I _DDq alarm, EMC interference and influences can not easily trigger a false alarm. Only when these EMC disturbances continue for a correspondingly long time and, moreover, are interrupted only by correspondingly brief pauses without EMC disturbances does the device according to the invention release 10 for monitoring the current consumption Iq of the circuit arrangement 12 an I _DDq false alarm.

Furthermore, it should be noted that the use of a bidirectional counter for the evaluation device shown above 30 only to be considered as an example. It is also possible to imagine significantly more complex EMC suppression algorithms and to implement them in a circuit block which is used instead of the evaluation device designed as a bidirectional counter.

So you can, for example, the output signal Q at the output 28c of the RS flip-flop element 28 use as input signal in such a circuit _block , wherein at the output of such a circuit block, an I _DDq -Alarmsignal is provided, wherein in the circuit block then a longer sequence as a history of I _DDq -single alarms stored and an optimized evaluation is supplied, which recognize if possible should be whether the I _{DDq single} alarms are more likely to be the result of prolonged EMC and EMI interference.

Another possibility is the EMC interference immunity of the device according to the invention 10 for monitoring the current consumption Iq of the circuit arrangement 12 It also consists of, as an evaluation device 30 to use a (unidirectional) up counter, which can count only upwards and moreover has a reset input, at which one also applies the output signal Q of the RS flip-flop element. As a result, an I _DDq signal is only generated for N directly consecutive I _DDq single alarms.

With respect to the executed as RS flip-flop element logic memory element 28 should be noted that it is advantageous to use an RS flip-flop type, where it is also allowed to both the set input 28a as well as the reset input 28b to occupy simultaneously with a logic high level, in which case the reset input, ie the reset, of the element should win.

It should also be noted that it is particularly advantageous when used as a comparator circuit 20 a self-calibrating comparator type is used. Because the comparator circuit 20 on the one hand already small potential differences of about 10 mV between the two inputs 20a . 20b to recognize as I _DDQ -Fehlerfall, on the other hand offset error is also affected by errors of about 10 mV by unavoidable, it is recommended a self-calibrating Comparator.

As long as the switch 16 is closed, needs the comparator circuit 20 not to work, because both inputs are at the same potential, ie on the supply voltage U1. This phase, which preferably corresponds to about 90% of the time duration, can be used to generate an error signal. Ideally, the comparator circuit should be 20 at its exit 20c can not decide between a low and a high logic level, because with the switch closed 16 both entrances 20a . 20b of the comparator circuit 20 at the same potential, ie the supply voltage U1, are. Through a control circuit can be during this phase of operation in an inner network node of the comparator circuit 20 memorizing a correction current that leads to the desired result "undecided" between a low and a high logic level.

This correction current can still be impressed unchanged when the switch 16 is open. It then serves in this operating state to compensate for the unwanted zero error of the comparator circuit 20 ,

In the following it will be discussed briefly with which sensitivity a cross-current Iq to be monitored can be detected, whereby the estimation of the sensitivity can be based on the following calculation, in which the following assumptions are made by way of example: (1) the capacitance value of the capacitor 18 is 1 pf, which is a common value, on the one hand sufficiently large, and on the other hand, the capacitor does not require too much area on an electronic integrated circuit chip; (2) the duration of the I _{DDq test} window, ie the time duration during which the test signal φ1 has a low logic level is about 10 μs, so that the switch 16 a maximum of 10 μs is open; (3) The comparator is self-calibrating and can therefore reliably evaluate a differential voltage of 10 mV as "different." It follows from: Q = C × U, and Q = Iq × T (LOW) Iq = C × U / T (LOW) = 10 -12 × 10 -2 / 10 -5 = 10 -9 = 1 nA

The charge Q is at the capacitor 18 stored charge amount, wherein the current Iq represents the minimum detectable cross-flow. This current value of 1 nA (10 ^-9 A) is already so small that it already corresponds to the usual leakage current, especially at higher operating temperatures. Therefore, it is recommended, depending on the temperature, the duty cycle of the test signal φ1, the capacitance value of the capacitor 18 and possibly the comparator threshold to change or adapt.

As already on the basis of the inventive construction of 1 is discussed, shows the waveform I of 3 the clock signal φ2 of the circuit arrangement 12 that the circuit to be monitored, for. B. a digital CMOS circuit part controls. In the transitions from a low logic level to a high logic level as well as from a high logic level to a low logic level of the clock signal φ2, relatively large cross currents Iq flow for a short time, which inevitably lead to the onset of the capacitor 18 applied voltage U ' ₁ and thus trigger an I _DDq error alarm. Therefore, with clocked logic, as is the case with the vast majority of circuits, it is necessary for the test signal φ1 and the clock signal φ2 to be synchronous with each other, and for the test signal φ1 to be allowed to go to a logic low only when all Charging currents of the circuit to be monitored, for. As the CMOS logic, have decayed sufficiently from the previous clock edge of the clock signal φ2. In addition, the clock signal φ2 must not have a clock edge as long as the test signal φ1 is in a logic low state.

If the circuit to be monitored 12 contains only synchronous logic arrangements with low or medium clock frequency, these specifications are comparatively easy to follow and implement in practice. With asynchronous logic or even with high clock frequencies, if half the period of the clock signal φ2 lasts approximately as long as the charge currents Iq generated per clock edge, these specifications may no longer be applicable in practice. In this case, for example, for the observation period during which the test signal φ1 has a low logic level, for example, it may be possible to slow down or even stop the clock signal φ2.

The following will now be based on 4 a further preferred embodiment of the device according to the invention for monitoring a power consumption of a circuit arrangement shown.

It should be noted that the circuit elements with those of 1 and 2 match, again have the same reference numerals and will not be explained again in detail.

As in 4 is shown, the monitoring device 10 according to the further preferred embodiment of the present invention, a switch 16 with a first switch connection 16a , a second switch terminal 16d and a third switch terminal 16c on. The first switch connection 16a is connected to a circuit node K, wherein the circuit node K is further connected to the second power supply terminal 12c the circuit arrangement 12 , the second port 18b the capacity 18 and the non-inverting input 20b the comparator circuit 20 connected is. Furthermore, the node K is optionally connected to a limiting circuit, which preferably consists of the two antiparallel-connected diodes 24 . 26 is formed.

The second switch connection 16b is connected to a reference potential, preferably ground potential. The inverting input 20a the comparison device 20 is connected to a reference signal U _ref . At the in 4 shown monitoring device 10 is the power supply 14 representing the operating voltage U1 of the circuit arrangement 12 provides directly to the first port 18a the capacity 18 and further to the first port 12a , ie the power supply input, the circuit arrangement 12 connected.

The following will now be based on 4 combined with 3 the operation of the device 10 for monitoring a current consumption Iq of the circuit arrangement 12 explained in detail.

How out 4 becomes apparent, is now the switch 16 between the circuit to be monitored 12 , For example, a digital CMOS circuit, and a reference potential, which is preferably ground potential. In addition, the (positive) supply voltage connection 12a the circuit to be monitored 12 directly to the power supply 14 connected to the supply voltage U1 for the electronic circuitry 12 provides. How out 4 becomes clear, is the capacity 18 parallel to the circuit to be monitored 12 as in the case of 1 illustrated embodiment of the monitoring device 10 the case is.

During the normal operating state of the circuit 12 is the switch 16 closed, so that the second supply voltage terminal 12c the circuit arrangement 12 directly connected to the reference potential. During the test state T _{IDDq of} the device 10 for monitoring the current consumption I _{q of} the circuit arrangement 12 , for example, by the test signal Φ1 (see the waveform II of 3 ) is the switch 16 between his first switch connection 16a and its second switch port 16b opened, so that the circuit arrangement 12 ie the second supply voltage connection 12c , from the reference potential (ground potential), is separated, and thus the supply voltage U1 of the circuit arrangement 12 as the real voltage curve U ' ₁ on the capacitor 18 is stored. Should now have an error in the circuit 12 present, flows a relatively high cross-flow I _q , the capacity 18 during the test state T _IDDq relatively strong discharges. The test state T _{IDDq of} the monitoring _device 10 is again defined, for example, if the test signal .phi.1 (compare signal curve II of FIG 3 ) has a low logic level. As a result, the potential at the node K, which increases with the second supply voltage connection, increases 12c (negative terminal) of the circuit arrangement 12 connected is. This node K is also located at the non-inverting input of the comparator 20 , z. B. a comparator circuit.

It thus becomes clear that the potential at the node K drifts relatively strongly in the direction of more positive values in the event of a fault, since the discharge of the capacitor causes it to drift away 18 due to a fault current I _{q of} the circuit arrangement 12 the potential at the second terminal 18b of the capacitor 18 and to raise the potential at the node K, the potential at the first capacitor terminal 18a to the potential U1 of the voltage supply device 14 is fixed.

Therefore, it is necessary to have the node K with the non-inverting input 20b the comparator circuit 20 to connect (in contrast to that on the basis of 1 described first preferred embodiment), wherein the inverting input 20a the comparator circuit 20 is connected to the reference potential U _ref , so that between the first and second input 20a . 20b the comparator circuit 10 the voltage difference .DELTA.U results.

At the exit 20c the comparison device 20 In turn, an I _DDq signal having a high logic level is output when the voltage difference .DELTA.U exceeds a predetermined threshold due to an error in the circuitry 12 suggesting.

It should be obvious that the other elements of the 4 shown monitoring device 10 with the in 1 respectively. 2 represented (optional) elements, and have substantially the same function, as already with reference to the 1 and 2 was explained.

Another specific advantage of in 4 shown monitoring device 10 is now, for example, that the switch 16 can be performed as an n-type MOS transistor, wherein n-type MOS transistors in the on state generally conduct better than p-type MOS transistors, whereby by the in 4 illustrated arrangement can result in savings in the area consumption of the entire integrated circuit.

It should also be noted that the inventive concept for monitoring the current consumption of a circuit arrangement can also be applied to the current consumption of circuits other than digital CMOS circuits. For example, assume that the Current consumption of a circuit is about 1 mA, so you have to "only" the period of time during which the switch 16 in an open state, select sufficiently short and at the same time the capacitance value of the capacitor 18 sufficiently large, so that a current drain does not lead to an excessive voltage drop across the capacitor 18 applied voltage leads. The comparator threshold is also set less sensitive so that the comparator output 20c For example, only then goes to a logic high level when the potential at its inverting input, ie at the first input 20a , a value of, for example, about 1 V below that potential at the second (non-inverting) input 20b decreases, ie, for example, about 1 V instead of about 10 mV, as explained above in a digital circuit part.

It It should be noted that any scaling course in The practice limits are set, which further use as no longer make sense.

In summary, it can thus be stated that the I _DDq system according to the invention is extremely advantageous, since the same can be used not only during the wafer test, but because the I _DDq monitoring system _{according to} the invention is _available during the entire operation of the circuit _arrangement to be monitored. In addition, the sensitivity of the I _DDq system _{according to} the invention is greater than in conventional systems, since it responds even at very small I _DDq cross currents and you can run the integrated I _{DDq -Überwachungssystem} completely integrated, causing minor parasitic effects, such as leakage and Leakage currents, stray capacitances, etc., as in conventional I _DDq test systems occur.

At the same time, it is extremely advantageous that the inventive I _DDq system does not additionally impair the functionality of the entire integrated circuit, since the monitoring _{concept according to} the invention _avoids the additional burden on the integrated circuit _arrangement to be investigated.

to Clarification of the present invention will be the underlying Concept for monitoring the current consumption of a circuit arrangement summarized again shown.

The current consumption of a circuit block is tested by storing its supply voltage on a capacitor, and then for a certain time only this capacitance supplies the circuit block with electrical voltage. The capacitance is sufficiently large and the observation time sufficiently small, so that within the observation time, the voltage at the capacity remains at a fault-free circuit block in a window that is sufficient for the functioning of the circuit block. If the voltage on the capacitor is significantly removed from the voltage stored at the beginning of the measurement, this is detected by means of a comparator circuit and the capacitor is recharged by the voltage source by the switch 16 is closed, even before the voltage at the capacity has left the predetermined window. Since the comparison circuit and the switch may be too slow during rapid voltage drops during the test, it is advantageous to additionally provide a limiting circuit parallel to the switch, which prevents an unacceptably large change in the voltage across the capacitor in any case, while still leaving enough leeway so that the comparison circuit can detect small and medium changes, if the circuit to be examined 12 inadmissibly draws a lot of electricity.

10

monitoring device

12

circuitry

12a

Power Entry

12b

Clock signal input

14

Power supply means

16

switch

16a

first switch connection

L6B

second switch connection

16c

third switch connection

18

capacitor

18a

first capacitor terminal

18b

second capacitor terminal

20

comparator

20a

first entrance

20b

second entrance

20c

output

22

logic element

22a

first entrance

22b

second entrance

22c

output

24

first diode

24a

first connection

24b

second connection

26

second diode

26a

first connection

26b

second connection

28

Logic memory element

28a

first entrance

28b

second entrance

28c

output

30

evaluation

30a

first entrance

30b

second entrance

30c

third entrance

30d

output

Claims (35)

Contraption ( 10 ) for monitoring a current consumption (Iq) of a circuit arrangement connected between a first and a second potential ( 12 ), wherein the circuit arrangement ( 12 ) a first and a second power supply terminal ( 12a . 12c ), having the following characteristics: a capacity ( 18 ) parallel to the circuit to be monitored ( 12 ) is switched; a switch ( 16 ) for disconnecting the parallel connection from the circuit arrangement to be monitored ( 12 ) and capacity ( 18 ) from the first potential, the switch ( 16 ) is controllable by a switching signal (S1) having a first and second switching state, wherein the switch ( 16 ) is closed at the first switching state and is open at the second switching state; and a facility ( 20 ; 20 . 28 . 30 ) for monitoring the potential on the side of the parallel circuit which is separate from the first potential, the device for monitoring a comparator device ( 20 ) for detecting a voltage difference between a voltage (U ' ₁ ) at the first power supply terminal ( 12a ) and a reference voltage during the second switch state and for outputting a comparison signal in response to the detected voltage difference; wherein the switching signal (S1) is a logical combination of a test signal (φ1) and the comparison signal, wherein the test signal (φ1) has a first logic state, if no monitoring of the current consumption (Iq) of the circuit arrangement ( 12 ), and the test signal (φ1) has a second logic state when monitoring the current consumption (Iq) of the circuit arrangement ( 12 ). Contraption ( 10 ) according to claim 1, wherein the switch ( 16 ) a first and a second switch terminal ( 16a . 16b ), wherein the first switch terminal ( 16a ) with a voltage supply device ( 14 ) for providing the first potential of the circuit arrangement ( 12 ), and the second switch terminal ( 16b ) with the first power supply connection ( 12a ) of the circuit arrangement ( 12 ) and the capacity ( 18 ) between the first power supply terminal ( 12a ) and a reference potential terminal for providing the second potential, and wherein the comparison signal of the comparison device ( 20 ) has a first logic state when the voltage difference is greater than a predetermined threshold and a second logic state when the voltage difference is less than or equal to the predetermined threshold. Contraption ( 10 ) for monitoring a current consumption (Iq) of a circuit arrangement connected between a first and a second potential ( 12 ), wherein the circuit arrangement ( 12 ) a first and a second power supply terminal ( 12a . 12c ), having the following characteristics: a capacity ( 18 ) parallel to the circuit to be monitored ( 12 ) is switched; a switch ( 16 ) for disconnecting the parallel connection from the circuit arrangement to be monitored ( 12 ) and capacity ( 18 ) from the second potential, the switch ( 16 ) is controllable by a switching signal (S1) having a first and second switching state, wherein the switch ( 16 ) is closed at the first switching state and is open at the second switching state; and a facility ( 20 ; 20 . 28 . 30 ) for monitoring the potential on the side of the parallel circuit which is separate from the second potential, the device for monitoring a comparator device ( 20 ) for detecting a voltage difference between a voltage at the second power supply terminal ( 12c ) and a reference voltage during the second switch state and for outputting a comparison signal in response to the voltage difference; wherein the switching signal (S1) is a logical combination of a test signal (φ1) and the comparison signal, wherein the test signal (φ1) has a first logic state, if no monitoring of the current consumption (Iq) of the circuit arrangement ( 12 ), and the test signal (φ1) has a second logic state when monitoring the current consumption (Iq) of the circuit arrangement ( 12 ). Contraption ( 10 ) according to claim 3, wherein the switch ( 16 ) a first and a second switch terminal ( 16a . 16b ), wherein the first switch terminal ( 16a ) to the second power supply terminal ( 12c ) of the circuit arrangement ( 12 ), and the second switch terminal ( 16b ) is connected to a reference potential terminal for providing the second potential, and wherein the capacitance ( 18 ) between the first power supply terminal ( 12a ) and the second power supply terminal ( 12c ), wherein the comparison signal of the comparison device ( 20 ) has a first logic state when the voltage difference is greater than a predetermined threshold and a second logic state when the voltage difference is less than or equal to the predetermined threshold. Device according to one of the preceding claims, wherein the first potential, the positive supply voltage (U1) and the second potential, the negative supply voltage or Massepo potential for the circuit arrangement to be monitored ( 12 ). Device according to one of the preceding claims, in which parallel to the switch ( 16 ) a limiting device ( 24 . 26 ) is provided to measure the voltage difference between the voltage at the first switch terminal ( 16a ) and the voltage at the second switch terminal ( 16b ) to limit to a maximum value of the voltage difference. Device according to Claim 6, in which the limiting device comprises a diode circuit with a diode ( 24 ; 26 ), wherein the maximum value of the voltage difference is the diffusion voltage of the diode. Device according to Claim 6 or 7, in which the diode circuit ( 24 . 26 ) has two anti-parallel connected diodes, and the maximum value of the voltage difference is around the value of the diffusion voltage of the diodes above and below the reference voltage. Device according to one of the preceding claims, in the logical link an OR link is. Device according to one of the preceding claims, further comprising an evaluation device ( 30 ), wherein the evaluation device ( 30 ) evaluates the logic state of the comparison signal in order to obtain information about the current consumption (Iq) of the circuit arrangement (FIG. 12 ) and outputs an error signal (I _DDq ) when the current consumption (Iq) of the circuit arrangement ( 12 ) exceeds a predetermined limit. Device according to Claim 10, in which the evaluation device ( 30 ) evaluates a sequence of logic states of the comparison signal. Device according to Claim 10 or 11, in which the evaluation device ( 30 ) is a unidirectional or bidirectional counter. Apparatus according to any one of the preceding claims, wherein the means for monitoring further comprises a logic memory element (12). 28 ) with a first and a second logical input ( 28a . 28b ) and a logical output ( 28c ), wherein at the first logical input ( 28a ) the comparison signal can be applied, and at the second logical input ( 28b ) the test signal (φ1) can be applied, the logical output ( 28c ) provides a logical output signal having a first logic state when the comparison signal has a high logic level and the test signal has a low logic level and which otherwise has a second logic state. Device according to Claim 13, in which the logic memory element ( 28 ) is a flip-flop element and preferably an RS flip-flop element, wherein the first logical input ( 28a ) the set input, the second logical input ( 28b ) the reset input and the logical output ( 28c ) is the Q output of the RS flip-flop element. Device according to one of claims 1 to 14, in which the comparison device ( 20 ) is a comparator circuit or a comparator circuit with a hysteresis. Apparatus according to claim 15, wherein the comparator circuit is a self-calibrating comparator circuit. Device according to one of the preceding claims, wherein above the capacity ( 18 ) a test voltage waveform (U ' ₁ ) is applied during the second state of the switch ( 16 ) a measure of the current consumption (Iq) of the circuit arrangement ( 12 ). Device according to one of the preceding claims, in which the circuit arrangement ( 12 ) comprises a switching clock signal (φ2), wherein the test signal (φ1) has a duty cycle greater than or equal to 0.5 and preferably in a range around 0.9, and two consecutive switching edges of the test signal (φ1) for performing a single current consumption monitoring operation ( Iq) occur within one half cycle of the circuit clock signal (φ2). Apparatus according to claim 18, wherein the switching edges of the test signal (φ1) during the steady state of the circuit arrangement ( 12 ) occur. Apparatus according to claim 18 or 19, wherein the Switching clock (φ2) during two consecutive switching edges of a monitoring process slows down or stopped. Device according to one of Claims 1 to 20, in which the circuit arrangement ( 12 ) is a digital circuit arrangement. Apparatus according to claim 21, wherein the digital Circuit arrangement, a CMOS circuit arrangement or a CMOS EEPROM circuit arrangement is. Method for monitoring a current consumption (Iq) of a circuit arrangement connected between a first and a second potential ( 12 ), wherein the circuit arrangement ( 12 ) a first and a second power supply terminal ( 12a . 12c ), comprising the following steps: providing a capacity ( 18 ) parallel to the circuit to be monitored ( 12 ) is switched; Disconnecting the parallel circuit of monitored circuit arrangement ( 12 ) and capacity ( 18 ) from the first potential by means of a switch ( 16 ), the switch ( 16 ) is controlled by a switching signal (S1) having a first and second switching state, wherein the switch ( 16 ) is closed at the first switching state and is open at the second switching state; and monitoring the potential on the side of the parallel circuit that is separate from the first potential, wherein the step of monitoring further comprises the following substeps: detecting a voltage difference between a voltage (U ' ₁ ) at the first voltage supply terminal ( 12a ) and a reference voltage during the second switch state; and outputting a comparison signal in dependence on the voltage difference; wherein the switching signal is obtained by a logical combination of a test signal (φ1) and the comparison signal, wherein the test signal (φ1) has a first logic state, if no monitoring of the current consumption (Iq) of the circuit arrangement ( 12 ), and the test signal (φ1) has a second logic state when monitoring the current consumption (Iq) of the circuit arrangement ( 12 ). The method of claim 23, further comprising the steps of: switching a switch ( 16 ) with a first and a second switch connection ( 16a . 16b ), wherein the first scarf teranschluss ( 16a ) with a voltage supply device ( 14 ) for providing the first potential of the circuit arrangement ( 12 ), and the second switch terminal ( 16b ) with the first power supply connection ( 12a ) of the circuit arrangement ( 12 ), and wherein a capacitance between the first power supply terminal ( 12a ) and a reference potential terminal for providing the second potential is connected; and wherein the comparison signal of the comparison device ( 20 ) has a first logic state when the voltage difference is greater than a predetermined threshold and a second logic state when the voltage difference is less than or equal to the predetermined threshold. Method for monitoring a current consumption (Iq) of a circuit arrangement connected between a first and a second potential ( 12 ), wherein the circuit arrangement ( 12 ) a first and a second power supply terminal ( 12a . 12c ), comprising the following steps: providing a capacity ( 18 ) parallel to the circuit to be monitored ( 12 ) is switched; Disconnecting the parallel circuit of monitored circuit arrangement ( 12 ) and capacity ( 18 ) from the second potential by means of a switch ( 16 ), the switch ( 16 ) is controlled by a switching signal (S1) having a first and second switching state, wherein the switch ( 16 ) is closed at the first switching state and is open at the second switching state; and monitoring the potential on the side of the parallel circuit that is separate from the second potential, wherein the step of monitoring further comprises the following substeps: detecting a voltage difference between a voltage at the second voltage supply terminal ( 12c ) and a reference voltage during the second switch state; and outputting a comparison signal in dependence on the voltage difference; wherein the switching signal is obtained by a logical combination of a test signal (φ1) and the comparison signal, wherein the test signal (φ1) has a first logic state, if no monitoring of the current consumption (Iq) of the circuit arrangement ( 12 ), and the test signal (φ1) has a second logic state when monitoring the current consumption (Iq) of the circuit arrangement ( 12 ). The method of claim 25, further comprising the steps of: switching a switch ( 16 ) with a first and a second switch connection ( 16a . 16b ), wherein the first switch terminal ( 16a ) to the second power supply terminal ( 12c ) of the circuit arrangement ( 12 ), and the second switch terminal ( 16b ) is connected to a reference potential terminal for providing the second potential, and wherein a capacitance between a first voltage supply terminal ( 12a ) of the circuit arrangement ( 12 ) and the second power supply terminal ( 12c ) is switched; and wherein the comparison signal has a first logic state when the voltage difference is greater than a predetermined threshold and a second logic state when the voltage difference is less than or equal to the predetermined threshold. The method of any one of claims 23 to 26, further comprising the step of limiting the voltage difference between the voltage at the first switch terminal (16). 16a ) and the voltage at the second switch terminal ( 16b ) to a maximum value of the voltage difference. A method according to any one of claims 23 to 27, wherein the logical link one Or link is. Method according to one of Claims 23 to 28, further comprising the steps of evaluating the logic state of the comparison signal in order to obtain information about the current consumption (Iq) of the circuit arrangement ( 12 ) and outputting an error signal (I _DDq ) when the current consumption (Iq) of the circuit arrangement ( 12 ) exceeds a predetermined limit. The method of claim 29, wherein at step evaluating a sequence of logic states of the comparison signal Is evaluated. A method according to claim 29 or 30, wherein the Step of rating with a unidirectional or bidirectional one Counter is performed. A method according to any one of claims 23 to 31, further comprising the step of storing the output comparison signal in a logic memory element (12). 28 ) with a first and a second logical input ( 28a . 28b ) and a logical output ( 28c ), wherein at the first logical input ( 28a ) the comparison signal is applied, and at the second logical input ( 28b ) the test signal (φ1) is applied, and the step of providing a logical output signal at the logical output ( 28c ) having a first logic state when the comparison signal has a high logic level and the test signal has a low logic level, and which otherwise has a second logic state. Method according to one of Claims 23 to 32, in which the circuit arrangement ( 12 ) comprises a switching clock signal (φ2), wherein the test signal (φ1) has a duty cycle greater than or equal to 0.5 and preferably in a range around 0.9, and two consecutive switching edges of the test signal (φ1) for performing a single current consumption monitoring operation ( Iq) occur within one cycle of the circuit clock signal (φ2). Method according to Claim 33, in which the switching edges of the test signal (φ1) during the steady state of the circuit arrangement ( 12 ) occur. A method according to claim 33 or 34, wherein the Switching clock (φ2) during two consecutive switching edges of a monitoring process slowed down or stopped.