DE102014014677A1 - Method for generating PDM-modulated signals for the supply of LEDs for illumination in motor vehicles - Google Patents

Abstract

The invention relates to a method for generating a PDM spread-code modulated PDM output signal (PDMout) for use in a DC power supply and / or a DC / DC converter for supplying LEDs with electrical energy in motor vehicles. The generation of the PDM output signal (PDMout) is based on n PDM spreading codes (PDM1 to PDMn), with n as a positive integer and n> 1. The spreading codes are written in a spreading code sequence of m successive PDM spreading codes of these n PDM spreading codes with a spreading code length equal to the PDM period (TPDM), with m as a positive integer and m ≥ 1 and a spreading Code period (Tselect) strung together. The generation of an optimized PDM spectrum of the PDM output signal (PDMout) comprises the steps of generating a first PDM signal (PDM1) having a PDM period and a PDM period (TPDM) and a duty cycle (fcycle), generating from one, in particular n-1, further PDM signals (PDM2, second PDM signal to PDMn, n-th PDM signal) by respective delay of the first PDM signal (PDM1) and / or generation of a respective delayed first PDM signal (PDM1), each i-th PDM signal (PDMi) thus generated, with 1 <i ≤ n, being delayed by an i-th time offset (Toff_i) from the first PDM signal (PDM1), and wherein each of the n PDM signals (PDM1 to PDMn) represents one of the n PDM spreading codes. Finally, selecting a kth PDM signal (PDMk) as the current PDM spreading code signal from the n PDM signals (PDM1 to PDMn) in response to a select signal (PDMselect) is selected and converted to the PDM output signal.

Description

introduction

The present application makes reference to German reservation 10 2013 016 386.2 dated 30 September 2013, the contents of which are hereby made the subject of the present application.

In the said German reservation DE 10 2013 016 386.2 Among other things, it is described that a modulation of the driving of consumers by means of spreading codes can be done, which are predefined and successively a switching element (M) by means of a PWM output signal (PWM _out ) or a PDM output signal (PDM _out ). That in the reservation DE 10 2013 016 386.2 The described method has the advantage that the spectrums of the PWM output signal (PWM _out ) or the PDM output signal (PDM _out ) can be controlled well. The disadvantage of the method is the immense storage space that the spreading codes require in order to be able to hold for all filling factors defined there, if the PWM or PDMA resolution should be more than 4 bits. As can be easily understood, the memory requirement increases with the 1 th power of 2 if the resolution is to be 1 bit.

Object of the invention

It is therefore the object of the invention described here, a simplified method for generating two or more PWM spread code or PWM spread-code signals for the PWM modulation or of two or more PDM spreading codes or To specify PDM spreading code signals for PDM modulation that produce as flat a spectrum as possible and give few peaks in the spectrum, so keeping your code table (CTAB) as in the disclosure DE 10 2013 016 386.2 can be omitted.

This object is achieved by means of methods according to claims 1 and 3.

Description of the invention

In the investigation of suitable PWM spreading codes for an application of the in the German patent application DE 10 2013 016 386.2 The technique described in PWM has shown that some PWM spreading codes are better suited than others to optimize the spectrum. The same applies to the application of the German patent application DE 10 2013 016 386.2 described the technique for pulse density modulation (PDM).

The disclosure content and technical content of the application DE 10 2013 016 386.2 is a full-featured part of this application and is provided herein as part of the description of this disclosure. For the claimed scope, the claims are relevant. The description is for explanation only.

The description initially deals with the generation of optimal PWM spread codes for pulse width modulation (PWM modulation), since this is easier to understand for the reader.

In a second part, the description deals with the generation of PDM spreading codes for pulse-density modulation (PDM modulation) and their use.

However, the statements of both parts refer to the PDM and PWM modulation simultaneously and can be applied by analogous transmission.

Part one: Generation of PWM spreading codes and their application

The invention is based on the recognition that good PWM spreading codes, which are those PWM spreading codes which produce a very flat spectrum with few spikes, have certain symmetries.

It has been shown that in the simplest case, two PWM spread code signals (PWM ₁ , PWM ₂ ) are generated, each of which is a normal PWM signal with the common predetermined PWM period T _PWM . These two PWM signals, the first PWM signal (PWM ₁ ) and the second PWM signal (PWM ₂ ), preferably have the same fill factor, which means their duty cycle (f _cycle ), typically expressed in% , is equal to. Typically, the first PWM signal (PWM ₁ ) is generated by a first PWM signal generator (PWMG ₁ ) and the second PWM signal (PWM ₂ ) by a second PWM signal. Signal generator (PWMG ₂ ) generated. The two PWM signals (PWM ₁ , PWM ₂ ) preferably have a fixed phase shift relative to each other. The period of the second PWM signal (PWM ₂ ) is shifted by one time, a second offset (T _{off_2} ) with respect to the first PWM signal (PWM ₁ ). Preferably, the two PWM signals (PWM ₁ , PWM ₂ ) are otherwise selected the same. By a time shift by the said second offset (T _{off_2} ), the first PWM signal (PWM ₁ ) can thus be mapped onto the second PWM signal (PWM ₂ ). By switching between these two PWM signals (PWM ₁ and PWM ₂ ), for example by means of a multiplexer (MUX) as a selection device then the PWM output signal (PWM _out ) can be formed. In this case, the selection device (MUX) is controlled by a selection signal (PWM _select ), whose nature will be discussed in more detail later. First, let's assume for simplicity that the selection is random.

It has been shown in the investigations that led to the invention, that a delay of the second PWM signal (PWM ₂ ) compared to the first PWM signal (PWM ₁ ) by half the PWM period (T _PWM ) to a particularly favorable spectrum of the PWM output signal (PWM _out ) leads.

• (1) Erzeugen eines ersten PWM-Signals (PWM₁) mit einer PWM-Periodendauer (T_PWM) und dem PWM-Duty-Cycle (f_cycle) und
• (2) Erzeugen eines zweiten PWM-Signals (PWM₂) durch Verzögerung des ersten PWM-Signals (PWM₁) beispielsweise in einer Verzögerungsstrecke (ΔT, ΔT₂) um vorzugsweise die Hälfte der PWM-Periode (T_PWM) wobei jedes der beiden erzeugten PWM-Signale (PWM₁, PWM₂) je einen der beiden erzeugten PWM-Spreiz-Codes als erstes bzw. zweites PWM-Spreiz-Code-Signal repräsentiert.

The invention of the underlying method for generating two, PWM spread codes, the PWM signals (PWM ₁ , PWM ₂ ) for generating a PWM output signal (PWM _out ) with an optimized PWM spectrum and with a predetermined PWM duty Cycle (f _cycle ), thus includes the steps

• (1) generating a first PWM signal (PWM ₁ ) with a PWM period (T _PWM ) and the PWM duty cycle (f _cycle ) and
• (2) generating a second PWM signal (PWM ₂ ) by delaying the first PWM signal (PWM ₁ ) in, for example, a delay line (ΔT, ΔT ₂ ) by preferably half the PWM period (T _PWM ), each of the two generated PWM signals (PWM ₁ , PWM ₂ ) each represents one of the two generated PWM spreading codes as the first and second PWM spread code signal.

Of course, the method can be generalized to n PWM spreading codes, where n is a positive integer greater than one.

It has been shown that in this more general case n PWM spread code signals (PWM ₁ to PWM _n ) are generated, each of which is itself a normal PWM signal with the common predetermined PWM period T _{PWM again} . These n PWM signals, the first PWM signal (PWM ₁ ) to the n th PWM signal (PWM _n ), preferably again have the same fill factor, which means that their duty cycle (f _cycle ), typically in%, is the same. Typically, the first PWM signal (PWM ₁ ) is generated by a first PWM signal generator (PWMG ₁ ) and the n-1 further PWM signals (PWM ₂ to PWM _n ) by further PWM signal generators (PWMG ₂ to PWMG _n ) , The n PWM signals again preferably have a fixed phase shift with respect to one another. The period of an i-th PWM signal (PWM _i ) with 2 ≦ i ≦ n, which is in each case one of the n-1 further PWM signals (PWM ₂ to PWM _n ), is at one time, i ten offset (T _{off_i} ), compared to the first PWM signal (PWM ₁ ) shifted. Preferably, all n PWM signals (PWM ₁ to PWM _n ) are otherwise selected the same. By means of a time shift about the said i-th offset (T _{off_i} ), it is thus possible to _{image an} i-th PWM signal (PWM _i ) onto the first PWM signal (PWM ₁ ). The PWM output signal (PWM _out) can then now, by switching between these n PWM signals (PWM ₁ to PWM _n) for example by means of an N to 1 multiplexer (MUX) as a selection device again be formed. In this case, the selection device (MUX) is again controlled by the selection signal (PWM _select ), whose nature will be discussed in more detail later. First of all, it should also be assumed here for simplicity that the selection is random.

It has been found in the investigations leading to the invention that a delay of an i-th PWM signal (PWM ₁ ) with respect to the first PWM signal (PWM ₁ ) by a time, the (i-1) / n the PWM period (T _PWM ), leads to a particularly favorable spectrum of the PWM output signal (PWM _out ).

• (1) Erzeugen eines ersten PWM-Signals (PWM₁) mit einer PWM-Periodendauer (T_PWM) und dem PWM-Duty-Cycle (f_cycle) und
• (2) Erzeugen von n – 1 weiteren PWM-Signalen (PWM₂, zweites PWM-Signal bis PWM_n, n-tes-PWM-Signal), mit n als ganzer positiver Zahl und n > 1, vorzugsweise durch Verzögerung in n – 1 Verzögerungsstrecken (ΔT₂ bis ΔT_n) um vorzugsweise jeweils (i – 1)/n der PWM-Periode (T_PWM), wobei i die Nummer des i-ten PWM-Signals (PWM_i) repräsentiert, aus diesen n – 1 PWM-Signalen (PWM₂ bis PWM_n) wobei jedes der beiden erzeugten n PWM-Signale (PWM₁ bis PWM_n) je einen der n erzeugten PWM-Spreiz-Codes als erstes bis n-tes PWM-Spreiz-Code-Signal repräsentiert.

The inventive method is then a method for generating n PWM spreading codes, with n as a positive integer and n> 1, for generating a PWM output signal (PWM _out ) with an optimized PWM spectrum and with a predetermined PWM Duty cycle (f _cycle ). It then includes the steps

• (1) generating a first PWM signal (PWM ₁ ) with a PWM period (T _PWM ) and the PWM duty cycle (f _cycle ) and
• (2) generating n - 1 further PWM signals (PWM ₂ , second PWM signal to PWM _n , n-th PWM signal), with n as a whole positive number and n> 1, preferably by delaying in n - 1 Delay lines (.DELTA.T ₂ to .DELTA.T _n) to each preferably (i - 1) / n of the PWM period (T _PWM), where i represents the number of the i-th PWM signal (PWM _i), of these n - 1 PWM Signals (PWM ₂ to PWM _n ) wherein each of the two generated n PWM signals (PWM ₁ to PWM _n ) each represents one of the n PWM spread codes generated as first to nth PWM spread code signals.

This generation can again take place firstly, for example by delaying the first PWM signal (PWM ₁ ) in n-1 delay devices (ΔT ₂ to ΔT _n ). In this case, each of the n-1 PWM signals is typically delayed differently. In the following, we refer to the i-th PWM signal (PWM _i ) when we mean one of the other PWM signals (PWM ₂ to PWM _n ). Thus, each i-th PWM signal (PWM _i ) with 1 <i ≤ n, if generated, is compared with the first PWM signal (PWM ₁ ) by an i-th time offset (T _{off_i} ) specific to the respective one i-th PWM signal (PWM _i ) is delayed from the first PWM signal (PWM ₁ ). Here, each of the generated n PWM signals (PWM ₁ to PWM _n ) represents one of the generated n PWM spreading codes and in the form of n PWM spread code signals.

In order to generate a PWM output signal (PWM _out ) from the PWM spread-code signals so defined, the n PWM signals (PWM ₁ to PWM _n ), a selection device, typically an n-to-1 multiplexer (MUX), is selected. , one of the n PWM signals (PWM ₁ to PWM _n ) is outputted as a k-th PWM signal (PWM _k ), which is then converted to the PWM output signal (PWM _out ) through an output stage (PA). In this case, this output stage (PA) adjusts the level and possibly the signal form such that the resulting PWM output signal (PWM _out ) is suitable for a subsequent switching device (M). at. Typically, it is a switching device (M), which is switched by means of the k-th PWM signal (PWM _k ), for example, "on" and "off".

Preferably, the selection of the k-th PWM signal (PWM _k ) from the n PWM signals (PWM ₁ to PWM _n ) takes place as the current PWM spread-code signal at the beginning of a PWM period of the first PWM signal (PWM ₁ ). Also preferably, the PWM spread code is not changed during a PWM period with a PWM period T _PWM . This means that the next change occurs at the earliest after a PWM period (T _PWM ) or an integer positive multiple thereof. The factor is designated below by m.

The second, next selection of a second selection of a PWM signal (PWM ₁ to PWM _n ) as PWM spreading code in the form of the current spreading code signal, the k th PWM signal (PWM _k ) PWM spreading codes are thus preferably carried out at the beginning of a PWM period of the first PWM signal (PWM ₁ ) after m PWM periods (T _PWM ), with m as a whole positive number.

The first selection of the spreading code signal from the PWM signals (PWM ₁ to PWM _n ) takes place at a first spreading code selection time (T _SCS1 ), which is typically a time at the beginning of a PWM period of the first PWM signal is (PWM _1). The next next selection of a PWM spreading code is then made at an immediately following second spreading code selection _timing (T _SCS2 ) at the beginning of a PWM period of the first PWM signal (PWM1), which occurs after m PWM periods (T _PWM ) follows the first selection time (T _SCS1 ).

The selection by the selection device (MUX) is controlled as a function of the selection signal (PWM _select ). Typically, this is an analog and preferably a digital single or bus signal that controls the selection device (MUX). This selection signal (PWM _select ) may be, for example, a random signal or a pseudo-random signal or a signal generated analogously and / or digitally by a finite state machine.

The following two paragraphs do not apply to pulse-density modulation while the previous statements were transmittable.

Typically, in PWM modulation, the PWM signals (PWM ₁ to PWM _n ) are based on PWM pulses having a predetermined pulse width (T _puls ), typically: f _cycle = T _pulse / T _PWM .

In this case, the pulse width (T _pulse ) of the PWM signals (PWM ₁ to PWM _n ) is typically modulated on one side and / or two sides depending on the duty cycle (f _cycle ). A one-sided modulation means that the position of an edge of the pulse of a PWM signal (PWM ₁ to PWM _n ) changes depending on the given duty cycle (f _cycle ) while the other edge of PWM period to PWM period always the same distance T _PWM has. In a two-sided PWM modulation both edges are changed and only one point within the pulse of the PWM signal always has the constant distance of the PWM period (T _PWM ).

The one described in the previous section is not relevant to pulse density modulation. The following can also be analogously applied to the pulse-density modulation again.

It is obvious that it is favorable if each of the PWM signals (PWM ₁ to PWM _n ) is generated by a respective PWM generator (PWMG ₁ to PWMG _n ). In many cases, all of these PWM generators (PWMG ₁ to PWMG _n ) can be formed by a single PWM generator. Also, a processor may execute a program that generates these PWM signals (PWM ₁ to PWM _n ) using the hardware.

The further PWM signals (PWM ₂ to PWM _n ) can be generated by n delay lines (ΔT ₂ to ΔT _n ) from a first PWM signal (PWM ₁ ). Typically, n - 1 similar delay lines (ΔT) can be connected in series, whereby the required n - 1 further PWM signals (PWM ₂ to PWM _n ) are generated at their n - 1 outputs.

Of course, it is also conceivable to generate one or more or all of the further PWM signals (PWM ₂ to PWM _n ) autonomously by means of one or more further PWM signal generators (PWMG ₂ to PWMG _n ), wherein the further PWM signal generators ( PWMG ₂ to PWMG _n ) are synchronized with the first PWM signal generator (PWMG ₁ ).

As a result, one obtains again the n-1 further PWM signals (PWM ₂ to PWM _n ), which are compared with the first PWM signal (PWM ₁ ) by a respective time- _related ith offset (T _{off_i} ) compared to the first PWM signal. signal (PWM1) are delayed, where i is here for the respective number of the other PWM signal (PWM ₂ to PWM _n) is available whose delay is being viewed.

As already discussed, it is particularly favorable if: _{Toff_i} = T _PWM * (i-1) / n

All these n PWM signals (PWM ₁ to PWM _n ) always represent each one of the n, PWM spreading codes.

It has been found that in some cases it makes sense first to allow several spreading code periods (T _PWM ) to elapse before the selection signal (PWM _select ) _transmits another PWM spreading code in the form of another current spreading code Signal (PWM _k ) by means of the selector (MUX) selects. It is therefore particularly preferred if the spreading code selection signal (PWM _select ) has a periodicity with a spreading code period (T _select ) in such a way that its value only occurs at times that are multiples, for example, m times the PWM period, can change. So for this spreading code period (T _select) typically applies: T _select = m * T _PWM

Where m is a whole positive number greater than or equal to 1.

The selection device (MUX) thus selects a k-th PWM signal (PWM _k ) as the current spread-code signal from the generated n PWM signals (PWM ₁ to PWM _n ) as a function of a selection signal (PWM _select ) as PWM Output signal (PWM _out ) typically at a time interval of m times the PWM period duration (T _PWM .) And generates therefrom for the next selection period of a duration of m times the PWM period (T _PWM ) said PWM Output signal (PWM _out ).

This temporal process is preferably realized by a controller (CTR), which is synchronized with typically one of the PWM signal generators (PWMG ₁ to PWMG _n ), in particular the first PWM signal generator (PWMG1), and which selects the k th PWM Signal (PWM _k ) as the current PWM spreading code by the selection signal (PWM _select ) at least for a period of time only at the beginning of a PWM period of the first PWM signal (PWM ₁ ) permits and during a PWM period (T _PWM ) _inhibits a change of the current spreading code signal (PWM _k ) from the beginning of the PWM period to the end thereof and during the spreading code period (T _select ). Thus, as already explained, a spreading code change is suppressed for m times a PWM period (T _PWM ), namely, the spreading code period (T _select ).

Of course, the selection signal (PWM _select ) can be impressed not only from the outside, but can also be generated by a selection signal generator (SG), which is then part of the device according to the invention. If the selection signal (PWM _select ) is to be a pseudo-random signal, it is for example it is conceivable to use a shift register fed back with a simple primitive polynomial as a selection signal generator (SG) or other devices which also generate a pseudo-random signal. However, the selection signal generator can also use other true random processes, for example noise, etc., to generate the selection signal (PWM _select ). Finally, the selection signal generator may be a finite state machine which generates in a predetermined manner a selection sequence of the selection signal (PWM _select ).

Finally, some special cases for the generation of the spreading code signal, in particular with regard to the pulse density modulation (PDM) are discussed.

Second part: Generation of PDM spreading codes and their application

Most of what has been described so far can be applied to pulse density modulation (PDM).

If the terms PWM are replaced by PDM in the terminology, the analogous terms for the pulse density modulation (PDM) are obtained.

Thus, the n PWM signals (PWM ₁ to PWM _n ) become the n PDM signals (PDM ₁ to PDM _n ) from the n PWM signals. From the duty cycle (f _cycle ), the fill factor, also referred to here as f _cycle , which actually specifies how many ones within a PDM period (T _PDM ) is set in relation to how many possible ones within a PDM period (T _PDM ) become.

The selected PWM signal (PWM _k ) becomes the selected PDM signal (PDM _k ). From the i-th PWM signal (PWM _i ) becomes the i-th PDM signal (PDM _i ). This can now be done more or less analogously to all quantities and terms.

With regard to modulation, however, there are minor differences in a specific form.

Preferably, all of the n PDM generators (PDMG ₁ to PDMG _n ) each generate one of the n PDM signals (PDM ₁ to PDM _n ). (N - 1) / n of the PDM-period duration (T _PDM) - The n PDM generators (PDMG ₁ to PDMG _n) produce their respective PWM signals (PDM ₁ to PDM _n) in n 1 partial regions with a total length of with a constant value. This constant value in these n - 1 sections corresponds to a 1-value or a 0-value. These PDM generators (PDMG ₁ to PDMG _n ) generate their PDM signals (PDM ₁ to PDM _n ) in a subregion of length 1 / n of the PDM period (T _PDM ) with a pulse density which is the n-fold modulo of the _PDM Fill factor (f _cycle ) times n.

In the case of n = 2, it is conceivable to generate the first PDM signal (PDM ₁ ) in such a way that, provided the duty cycle is less than 50%, it consists of a first half filled with a pulse-density-modulated pulse density signal whose pulse density is twice the fill factor (f _cycle ). As a result, the first half of the PDM signal (PDM ₁ ) thus defined has to be filled at a filling factor (f _cycle ) of 50% to 100%.

The other half is then set to zero.

If the desired filling factor (f _cycle ) of the PDM signal is greater than 50%, then the second half is completely filled and the first half only with a pulse density which is twice the difference between the duty cycle and 50%.

Shifting by half a PDM period (T _PDM / 2) again results in the second PDM signal (PDM ₂ ).

This can also be extended to n PDM signals (PDM ₁ to PDM _n ).

First, the case of a filling factor (f _cycle ) less than 100% / n is dealt with.

In this case, it is conceivable to generate the first PWM signal (PWM ₁ ) in such a way that, provided the fill factor (f _cycle ) is less than 100% / n, it consists of a first 1 / n part of the PWM period which is filled with a pulse density modulated pulse density signal (PDM) whose pulse density is n times the filling factor (f _cycle ). It follows that the first 1 / n part of the thus defined PDM signal (PDM ₁ ) must be filled to 100% at a filling factor (f _cycle ) of 1 / n.

The other following n - 1 parts of a partial signal length of each T _PWM / n are then set to zero.

Next, the case of a filling factor (f _cycle ) larger than 100% / n but less than 200% / n will be dealt with.

If the desired fill factor (f _cycle ) is greater than 100% / n but less than 200% / n, then the first part is completely filled and the second part only with a pulse density which is n times the difference between duty cycle and 100% / n equals, filled and the third to the nth part set to zero.

This can be continued such that, in the event that the desired fill factor (f _cycle ) is greater than f × 100% / n, with n-1 ≥ f ≥ 1, the first part is complete up to the f-th part filled to 100% and the f + 1-th part is filled only with a pulse density which is equal to n times the jaw clasp of n times the filling factor (f _cycle ) and the f + 2-th to n part is set to zero. The Gauss bracket denotes the largest integer that is less than or equal to the number in the Gauss bracket. This is written as f = ⌊f _cycle · n⌋.

Analogously, the number of sub-areas to be filled with zero can be as well n - f - 1 = n - ⌊f _cycle · n⌋ - 1 be specified.

How the values 0 and 1 are defined in this sense with respect to the effect on the switching device (M) depends on the application. In this disclosure, it is assumed by way of example that the switching element is closed at 1 and opened at 0. This can be reversed.

By shifting by one PDM period part (i · T _PDM / n), one obtains again the ith PDM signal (PDM _i ) from the first PDM signal (PDM ₁ ).

The advantage of this method is that it is a mixture of PWM and PDM.

In the following the invention will be further explained with reference to the attached drawings.

1a shows a first PWM signal (PWM ₁ ) with a duty cycle of f _cycle = 25% and a PWM period of T _PWM . In this case, only two spreading code signals (PWM ₁ and PWM ₂ ) are generated. The second spreading code signal, the second PWM signal (PWM ₂ ) is formed from the first PWM signal (PWM ₁ ) by shifting by one PEM period (T _PWM ) divided by the number of spreading code signals n Since n is two here, the shift T is _PWM / 2.

1b shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle = 37.5% in one-sided PWM modulation.

2a shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle = 75% in one-sided PWM modulation.

2 B shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle = 62.5% in one-sided PWM modulation.

3 now shows the resulting PWM output signals (PWM _out ) for the signals of 1a . 1b . 2a and 2 B ,

3a shows the PWM output (PWM _out ) for the PWM signals (PWM ₁ and PWM ₂ ) of the 1a , The hatched areas show the time ranges in which the selection signal (PWM _select ) modulates the output signal (PWM _out ). If the selection signal (PWM _select ) is a random signal, the range of blocks within a PWM selection period of m * T _{PWM is} either common to all of these areas within the spreading code period (T _select ), for example, 1 or 0. Which value for all these areas within a spreading code period (T _select ) is assumed to be random at a random signal as a selection signal (PWM _select ). Thus, these time ranges "rush" from spreading code period (T _select ) to PWM spreading code period (T _select ) as a whole. Between these "noisy areas of the PWM output signal (PWM _out) is zero. It is thus the PWM of a random signal, which is band-limited by the spreading code period (T _select ).

3b shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of the 1b , Otherwise the conditions are similar to those of 3a

3c shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of the 2 B with a duty cycle (f _cycle ) of more than 50%, namely 62.5%. The difference to 3b is that between the "noisy" areas marked as hatched, the PWM output (PWM _out ) in this example is one instead of zero as before. This is because the duty cycle (f _cycle ) of more than 50% is used.

3d shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of the 2a with a duty cycle (f _cycle ) of 75%. Otherwise the conditions are similar to those of 3c

4 shows an exemplary schematic example of an apparatus for generating an optimized PWM output signal. In this case, in contrast to the preceding figures not n = 2 but n = 4 selected by way of example. The four PWM signals (PWM ₁ to PWM ₄ ) are generated by four signal generators (PWMG ₁ to PWMG ₄ ). In this case, the second PWM signal (PWM ₂ ) is equal to the first PWM signal (PWM ₁ ) delayed by one quarter of the PWM period (T _PWM ). In this case, the third PWM signal (PWM ₃ ) is equal to the first PWM signal (PWM ₁ ) delayed by two quarters of the PWM period (T _PWM ) and the fourth PWM signal (PWM ₃ ) is equal to the first PWM signal ( PWM ₁₎ delayed by three quarters of the PWM period (T _PWM). For these conditions to remain, the PWM generators (PWMG ₁ to PWMG ₄ ) are synchronized by a synchronization signal (Sync). This is provided in this example by a control unit (CTR), which typically also provides the system clock and / or uses the system clock itself. The control unit (CTR) ensures by means of a likewise drawn control line that the selection signal generator (SG) only a different PWM signal (PWM ₁ to PWM ₄ ) as a selected PWM signal (PWM _k ) by means of the multiplexer (MUX) selects if m PWM periods are over, that is, the spreading code period (T _select ) is over. The thus selected PWM signal (PWM _k ) is adjusted by a matching device (PA) to the requirements of the element to be controlled, here a switching device (M) in the form of a MOS transistor, as a PWM output signal (PWM _out ). As a result, the load, here an LED (D), is supplied with a current which is smoothed by the choke coil L. Freewheeling diodes, etc. are not shown for simplicity.

5 Figure 14 shows exemplary four PWM signals (PWM ₁ through PWM ₄ ) for an exemplary 12.5% duty cycle (f _cycle ) appropriate to the device 4 ,

6 shows the division of a PWM period in n, here for example 4, time slots (SL1 to SL4). Otherwise, the figure corresponds to the 5 ,

7 shows the first PWM signal (PWM ₁ ) for a different number m of PWM periods between two spreading code selection times (TSCS1, TSCS2) for the duration of the spreading code period (T _select ) for a first selection of a PWM Signal (PWM ₁ to PWM _n ) as a PWM spreading code in the form of the current PWM spread code signal (PWM _k ). For m = 1, the spreading code period (T _select ) is identical to the PWM period (T _PWM ).

8th now shows a scrambler (SCR), the time slots of the n PWM signals, for example, four PWM signals (PWM ₁ to PWM ₄ ), n scrambled PWM signals, here four exemplary scrambled PWM signals (PWM ₁ 'to PWM ₄ ') assigns. Only then does the selection device (MUX) form as in 4 the selected PWM signal (PWM _k ). The scrambling is based on 9 explained.

9 The exemplary result of scrambling from here exemplarily shows 4 PWM signals by the scrambler (SCR) accordingly 8th represents.

The first scrambled PWM signal (PWM ₁ ') corresponds to the first time slot (SL ₁₎ the first time slot (SL ₁₎ of the first PWM signal (PWM _1). The first scrambled PWM signal (PWM ₁ ') corresponds to the second time slot (SL ₂₎ the second time slot (SL ₂₎ of the second PWM signal (PWM _2). The first scrambled PWM signal (PWM ₁ ') corresponds to the third time slot (SL ₃₎ to the third time slot (SL ₃₎ of the third PWM signal (PWM _3). The first scrambled PWM signal (PWM ₁ ') corresponds to the fourth time slot (SL ₄₎ the fourth time slot (SL ₄₎ of the fourth PWM signal (PWM _4).

The second The scrambled PWM signal (PWM ₂ ') in the first time slot (SL ₁ ) corresponds to the first time slot (SL ₁ ) of the second PWM signal (PWM ₂ ). The second scrambled PWM signal (PWM ₂ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the third PWM signal (PWM ₃ ). The second scrambled PWM signal (PWM ₂ ') corresponds to the third time slot (SL ₃₎ to the third time slot (SL ₃₎ of the fourth PWM signal (PWM _4). The second scrambled PWM signal (PWM ₂ ') corresponds in the fourth time slot (SL ₄ ) to the fourth time slot (SL ₄ ) of the first PWM signal (PWM ₁ ).

The third scrambled PWM signal (PWM ₃ ') corresponds in the first time slot (SL ₁ ) to the first time slot (SL ₁ ) of the third PWM signal (PWM ₃ ). The third scrambled PWM signal (PWM ₃ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the fourth PWM signal (PWM ₄ ). The third scrambled PWM signal (PWM ₂ ') corresponds to the third time slot (SL ₃₎ to the third time slot (SL ₃₎ of the first PWM signal (PWM _1). The third scrambled PWM signal (PWM ₃ ') in the fourth time slot (SL ₄ ) corresponds to the fourth time slot (SL ₄ ) of the second PWM signal (PWM ₂ ).

The fourth scrambled PWM signal (PWM ₄ ') corresponds to the first time slot (SL ₁₎ the first time slot (SL ₁₎ of the fourth PWM signal (PWM _4). The fourth scrambled PWM signal (PWM ₄ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the first PWM signal (PWM ₁ ). The fourth scrambled PWM signal (PWM ₄ ') corresponds to the third time slot (SL ₃₎ to the third time slot (SL ₃₎ of the second PWM signal (PWM _2). The fourth scrambled PWM signal (PWM ₄ ') in the fourth time slot (SL ₄ ) corresponds to the fourth time slot (SL ₄ ) of the third PWM signal (PWM ₃ ).

In this way, by cyclically swapping the time slots, new scrambled PWM signals (PWM ₁ 'to PWM _n ') are formed from the PWM signals (PWM ₁ to PWM _n ) which typically result in lower frequency spectra

10 shows the scrambled PWM signals (PWM ₁ 'to PWM ₄ ') for a duty cycle (f _cycle ) of 37.5%. The first scrambled PWM signal (PWM ₁ ') is here permanently exemplary 1.

11 shows the scrambled PWM signals (PWM ₁ 'to PWM ₄ ') for a duty cycle (f _cycle ) of 62.5%. The first scrambled PWM signal (PWM ₁ ') and the second scrambled PWM signal (PWM ₂ ') are here permanently exemplified 1.

12 shows the scrambled PWM signals (PWM ₁ 'to PWM ₄ ') for a duty cycle (f _cycle ) of 87.5%. The first scrambled PWM signal (PWM ₁ ') and the second scrambled PWM signal (PWM ₂ ') and the third scrambled PWM signal (PWM ₃ ') are permanently exemplified herein.

13a shows an alternative possibility for generating two optimal PWM spreading codes. Again, instead of n = 2, another integer number of n is possible. In this case, the first PWM signal (PWM ₁ ) is modulated during a period of T _PWM / n, ie here T _PWM / 2, with a pulse density modulation (PDM) with a pulse density of 2 × f _cycle . Here f _{cycle has} the function of the filling factor (f _cycle ), which is the set of ones in relation to the set of possible ones. 13a shows the conditions at f _cycle <1 / n here so f _cycle <50%. The second PWM signal (PWM ₂ ) is again obtained by delaying T _PWM / n, in this case T _PWM / 2.

13b corresponds to 13a with the difference that the fill factor X is now over 50%. In the 13a Modulated signal ranges are now constant to Example 1, while the previously lying on example 0 parts are now modulated with a pulse density modulation (PDM). The number f of the subregions that are constantly set to exemplary 1 results as the rounded value f of f _cycle · n. This is typically written with a Gaussian bracket ⌊f _Cycle · n⌋. Only f subareas of the first PWM signal (PWM ₁ ) are then always set to exemplary 1 and then an f + 1-th region is provided with the said pulse density modulation. The density of this pulse density modulation is n · (f _cycle - f / n). Since n = 2 here, the density of this modulation is 2 · (f _cycle - 1/2).

15 shows the Fourier transform of a random-modulated signal according to the US8129924 , The transform contains relatively many relatively high spikes.

16 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) with a duty cycle (f _cycle ) of 25% and m = 1 without scrambling.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,111,000,000,000,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,000,000,011,110,000th

17 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) with a duty cycle (f _cycle ) of 25% and m = 2 without scrambling.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,100,000,011,000,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,000,110,000,001,100th

18 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) with a duty cycle (f _cycle ) of 25% and m = 2 without scrambling.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,000,100,010,001,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,010,001,000,100,010th

19 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m = 1.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,111,000,000,000,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,000,000,011,110,000th
The first scrambled PWM spreading code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence
1,111,000,011,110,000th
The second scrambled PWM spreading code, the second scrambled PWM signal (PWM ₂ '), corresponds to a bit sequence
0,000,000,000,000,000th

20 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m = 2.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,100,000,011,000,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,000,110,000,001,100th
The first scrambled PWM spreading code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence
1,100,110,011,001,100th
The second scrambled PWM spreading code, the second scrambled PWM signal (PWM ₂ '), corresponds to a bit sequence 0000000000000000.

21 shows the Fourier transform of a PWM signal according to the invention (PWM _out ) after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m = 4.
The first PWM spreading code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence
1,000,100,010,001,000th
The second PWM spreading code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence
0,010,001,000,100,010th
The first scrambled PWM spreading code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence
1,010,101,010,101,010th
The second scrambled PWM spreading code, the second scrambled PWM signal (PWM ₂ '), corresponds to a bit sequence
0,000,000,000,000,000th

Like that 16 to 21 can be seen, in contrast to US8129924 by choosing the parameters n and m, the spectrum can be influenced in wide ranges. LIST OF REFERENCE NUMBERS CTR Control. The controller is preferably with at least one of PWM signal generators (PWMG ₁ to PWMG _n ), in particular the first PWM signal generator (PWMG1), or with at least one of the PDM signal generators (PDMG ₁ to PDMG _n ), in particular the first PDM Signal Generator (PDMG1), synchronized and leaves the Selection of the kth PWM signal (PWM _k ) or the kth PDM signal (PDM _k ) as the current spreading code signal by the selection signal (PWM _select , PDM _select ) for at least one Period only at the beginning of a PWM period of the first PWM signal (PWM ₁ ) or only at the beginning of a PDM Period of the first PDM signal (PDM ₁ ). In another According to the invention, the controller leaves a next one Reselect the first selection to one first spreading code selection _timing (T _SCS1 ) at the time at the beginning of a PWM period of the first PWM signal (PWM ₁ ) or at the beginning of a PDM period of the first PDM signal (PDM ₁ ) follows. This approval of a new selection of a new spreading code signal takes place first to an immediately following second spreading code Selection time (T _SCS2 ) at the beginning of a PWM period of first PWM signal (PWM ₁ ) or at the beginning of a PDM Period of the first PDM signal (PDM ₁ ) after m PWM Periods (T _PWM ) or after m PDM periods (T _PDM ) again. Thus, the control suppresses a change in the spreading Code signal for the duration of a spreading code period (T _select ). .DELTA.T Delay. The delay element delays Signal preferably by the PWM period (T _PWM ) divided by the number n of the PWM signals or the PDM period (T _PDM ) divided by the number n of PWM signals. ΔT ₂ Delay element that the first PWM signal (PWM ₁ ) order the first offset (T _{off_1} ) to the second PWM signal (PWM ₂ ) delayed or that the first PDM signal (PDM ₁ ) to the first offset (T _{off_1} ) to the second PDM signal (PDM ₂ ) delayed. ΔT ₃ Delay element that the first PWM signal (PWM ₁ ) order the third offset (T _{off_3} ) to the third PWM signal (PWM ₃ ) delayed or that the first PDM signal (PDM ₁ ) to the third offset (T _{off_3} ) to the third PDM signal (PDM ₃ ) delayed. ΔT ₄ Delay element that the first PWM signal (PWM ₁ ) order the fourth offset (T _{off_4} ) to the fourth PWM signal (PWM ₄ ) delayed or that the first PDM signal (PDM ₁ ) to the fourth offset (T _{off_4} ) to the fourth PDM signal (PDM ₄ ) delayed. ΔT _n Delay element that the first PWM signal (PWM ₁ ) order the nth offset (T _{off_n} ) to the nth PWM signal (PWM _n ) delayed or that the first PDM signal (PDM ₁ ) to the n- _delayed offset (T _{off_n} ) to the nth PDM signal (PDM _n ). D LED or load f _cycle PWM duty cycle with PWM modulation in% or Fill factor for PDM modulation in% L inductor M Switching device, in particular a transistor MUX Selector. The selector selects the kth PWM signal (PWM _k ) or the kth PDM signal (PDM _k ) as current spreading code signal from the generated n PWM Signals (PWM ₁ to PWM _n ) or from the n PDM generated Signals (PDM ₁ to PDM _n ) depending on a Selection signal (PWM _select , PDM _select ) as PWM Output signal (PWM _out ) or as PDM output signal (PDM _out ) off. n Number of PWM spreading codes with PWM modulation or Number of PDM spreading codes in PDM modulation m PWM modulation: number of PWM periods between two spreading code selection _times (T _SCS1 , T _SCS2 ) for one first selection of a PWM signal (PWM ₁ to PWM _n ) as PWM spreading code in the form of the current PWM spreading Code signal (PWM _k ). PDM modulation: number of PDM periods between two Spread code selection _times (T _SCS1 , T _SCS2 ) for a first one Selection of a PDM signal (PDM ₁ to PDM _n ) as PDM Spreading code in the form of the current PWDM spreading code Signal (PDM _k ). PA Adaptation device for adapting the result to the Useful element (here the switching device (M)); PWM modulation: that through the selector (MUX) selected PWM signal (PWM _k ) is determined by the Matching device (PA) to the requirements of controlling element, here a switching device (M) in Shape of a MOS transistor, adapted. PDM modulation: that through the selector (MUX) selected PDM signal (PDM _k ) is determined by the Matching device (PA) to the requirements of controlling element, here a switching device (M) in Shape of a MOS transistor, adapted. PDM Pulse density modulation PDM ₁ first PDM signal of the first PDM generator (PDMG ₁ ) PDM ₂ second PDM signal of the second PDM generator (PDMG ₂ ) PDM ₃ third PDM signal of the third PDM generator (PDMG ₃ ) PDM ₄ fourth PDM signal of the fourth PDM generator (PDMG ₄ ) PDM ₁ ' first scrambled PDM signal PDM ₂ ' second scrambled PDM signal PDM ₃ ' third scrambled PDM signal PDM ₄ ' fourth scrambled PDM signal PDM _i ith PDM signal of the ith PDM generator (PDMG _i ), with 1 <i <n PDM _k current PDM spread code signal or kth PDM signal of the ith PDM generator (PDMG _i ), with 1 ≤ k ≤ n. The kth PDM signal is the signal that depends on current status of the selection signal (PDM _select ) currently is selected and thus for the duration of this selection with the PDM output signal (PDM _out ) essentially, typically down to level and some delay, matches. PDM _n nth PDM signal of the nth PDM generator (PDMG _n ) PDM _out PDM output signal of the device according to the invention PDM _select select signal PDMG ₁ first PDM signal generator for generating the first PDM Signal (PDM ₁ ) PDMG ₂ second PDM signal generator for generating the second PDM signal (PDM ₂ ). The second signal generator generates the second PDM signal (PDM ₂ ) is typically one second offset (T _{off_2} ) offset in time to the first PDM Signal (PDM ₁ ). Preferably, it is about this second offset (T _{off_2} ) delayed first PDM signal (PDM ₁ ). PDMG _i i-th PDM signal generator (1≤i≤n) for generating the ith PDM signal (PDM _i ). The ith signal generator generates the i-th signal generator PDM signal (PDM _i ) typically by an ith offset (T _{off_i} ) offset in time to the first PDM signal (PDM _i ). Preferably, this is an i-th offset (T _{off_i} ) delayed first PDM signal (PDM ₁ ). The i-th Signal generator is one, namely the ith, the n Signal generators (PDMG ₁ to PDMG _n ). PDMG _k kth PDM signal generator (1 ≤ k ≤ n) for generating the k th PDM signal (PDM _k ), which contains the currently selected spreading Code signal is. The kth signal generator generates the kth PDM signal (PDM _k ) typically by a k-th offset (T _{off_k} ) offset in time to the first PDM signal (PDM ₁ ). Preferably, this is about this k th offset (T _{off_k} ) delayed first PDM signal (PDM ₁ ). The kth Signal generator is one, namely the kth, the n Signal generators (PDMG ₁ to PDMG _n ). PDMG _n nth PDM signal generator n for generating the nth PDM Signal (PDM _n ). The nth signal generator generates the nth PDM signal (PDM _n ) typically by an nth offset (T _{off_n} ) offset in time to the first PDM signal (PDM ₁ ). It is preferably about this n-th offset (T _{off_i} ) delayed first PDM signal (PDM ₁ ). PWM pulse-width modualtion PWM ₁ first PWM signal of the first PWM generator (PWMG ₁ ) PWM ₂ second PWM signal of the second PWM generator (PWMG ₂ ) PWM ₃ third PWM signal of the third PWM generator (PWMG ₃ ) PWM ₄ fourth PWM signal of the fourth PWM generator (PWMG ₄ ) PWM ₁ ' first scrambled PWM signal PWM ₂ ' second scrambled PWM signal PWM ₃ ' third scrambled PWM signal PWM ₄ ' fourth scrambled PWM signal PWM _i i-th PWM signal of the i-th PWM generator (PWMG _i ), with 1 <i <n PWM _k current PWM spread code signal or k-th PWM signal of the i-th PWM generator (PWMG _i ), with 1 ≤ k ≤ n. The k-th PWM signal is the signal that depends on current status of the selection signal (PWM _select ) currently is selected and thus for the duration of this selection with the PWM output (PWM _out ) essentially, typically down to level and some delay, matches. PWM _n nth PWM signal of the nth PWM generator (PWMG _n ) PWM _out PWM output signal of the device according to the invention PWM _select select signal PWMG ₁ first PWM signal generator for generating the first PWM signal (PWM ₁ ) PWMG ₂ second PWM signal generator for generating the second PWM signal (PWM ₂ ). The second signal generator generates the second PWM signal (PWM ₂ ) is typically one second offset (T _{off_2} ) offset in time from the first PWM Signal (PWM ₁ ). Preferably, it is about this second offset (T _{off_2} ) delayed first PWM signal (PWM ₁ ). PWMG _i i-th PWM signal generator (1≤i≤n) for generating the ith PWM signal (PWM _i ). The i-th signal generator generates the i-th PWM signal (PWM _i ) typically by an i-th Offset (T _{off_i} ) offset in time to the first PWM signal (PWM _i ). It is preferably an order of this ith Offset (T _{off_i} ) delayed first PWM signal (PWM ₁ ). The i- te signal generator is one, namely the ith, the n Signal generators (PWMG ₁ to PWMG _n ). PWMG _k k-th PWM signal generator (1 ≤ k ≤ n) for generating the k-th PWM signal (PWM _k ), which contains the currently selected spreading Code signal is. The kth signal generator generates the kth PWM signal (PWM _k ) typically by a k-th offset (T _{off_k} ) offset in time to the first PWM signal (PWM ₁ ). Preferably, this is about this k th offset (T _{off_k} ) delayed first PWM signal (PWM ₁ ). The kth Signal generator is one, namely the kth, the n Signal generators (PWMG ₁ to PWMG _n ). PWMG _n nth PWM signal generator n for generating the nth PWM signal (PWM _n ). The nth signal generator generates the nth PWM signal (PWM _n ) typically by an nth Offset (T _{off_n} ) offset in time to the first PWM signal (PWM ₁ ). Preferably, it is about this nth Offset (T _{off_i} ) delayed first PWM signal (PWM ₁ ). SCR scrambler SG Selection signal generator. PWM modulation: The selection signal generator generates the Selection signal (PWM _select ) based on which Selector (MUX) the current spreading code signal (PWM _k ) representing the current PWM spreading code n PWM signals (PWM ₁ to PWM _n ). PDM modulation: The selection signal generator generates the Selection signal (PDM _select ) based on which Selector (MUX) the current spreading code signal (PDM _k ) representing the current PDM spreading code selects the n PDM signals (PDM ₁ to PDM _n ). T _{off_2} Delay of the second PWM signal (PWM ₂ ) opposite the first PWM signal (PWM ₁ ) or delay of second PDM signal (PDM ₂ ) compared to the first PDM Signal (PDM ₁ ) T _{off_3} Delay of the third PWM signal (PWM ₃ ) the first PWM signal (PWM ₁ ) or delay of third PDM signal (PDM ₃ ) compared to the first PDM Signal (PDM ₁ ) T _{off_4} Delay of the fourth PWM signal (PWM ₄ ) the first PWM signal (PWM ₁ ) or delay of fourth PDM signal (PDM ₄ ) compared to the first PDM Signal (PDM ₁ ) T _{off_i} Delay of the i-th PWM signal (PWM _i ) from the first PWM signal (PWM ₁ ) or delay of the i-th PDM signal (PDM _i ) against the first PDM signal (PDM ₁ ) T _{off_k} Delay of the kth PWM signal (PWM _k ), the current one selected PWM spreading code signal, compared to first PWM signal (PWM ₁ ) or delay of the kth PDM signal (PDM _k ), of the currently selected PDM spreading Code signal, compared to the first PDM signal (PDM ₁ ) T _{off_n} Delay of the nth PWM signal (PWM _n ) the first PWM signal (PWM ₁ ) or delay of the n- PDM signal (PDM _n ) against the first PDM signal (PDM ₁ ) T _pulse PWM pulse width T _PDM PDM period T _PWM PWM period T _select Spreading code period. The spreading code period is a m Fold period of the PWM period (T _PWM ) or a m Fold period of the PDM period (T _PDM ). T _SCS1 PWM modulation: First spread code selection time for a first selection of a PWM signal (PWM ₁ to PWM _n ) as PWM spreading code in the form of the current PWM Spreading code signal (PWM _k ); PDM modulation: First spreading code selection time for a first selection of a PDM signal (PDM ₁ to PDM _n ) as PDM spreading code in the form of the current PDM spreading code Signal (PDM _k ). T _SCS2 PWM modulation: second spread code selection time for a direct selection on the first selection of a PWM Signal (PWM ₁ to PWM _n ) as PWM spread code in the form the current PWM spread code signal (PWM _k ) following second selection of the same; PDM modulation: second spread code selection time for an immediate on the first selection of a PDM Signal (PDM ₁ to PDM _n ) as PDM spreading code in the form of current PDM spreading code signal (PDM _k ) following second Selection of the same. V _asked exemplary supply voltage

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102013016386 [0001, 0002, 0002, 0003, 0005, 0005, 0006]
• US 8129924 [0087, 0094]

Claims (10)

Method for generating two, in particular n, PDM spreading codes, in particular for use in a DC voltage supply and / or a DC / DC converter, in particular for the supply of LEDs with electrical energy, in particular in motor vehicles, with n being a positive, whole Number and n> 1, for generating a PDM output signal (PDM _out ) with an optimized PDM spectrum and with a predetermined PDM filling factor (f _cycle ), comprising the steps a. Generating a first PDM signal (PDM ₁ ) with a PDM period (T _PDM ) and the PDM filling factor (f _cycle ) and b. Generating at least one, in particular n-1, further PDM signals (PDM ₂ , second PDM signal to PDM _n , n-tes PDM signal), with n as a whole positive number and n> 1, in particular by delaying the first PDM signal (PDM ₁ ), and i. wherein each i-th PWM signal (PDM _i) with 1 <i ≤ n, if generated, compared to the first signal (PDM ₁₎ to a time i-th offset (T _{off_i)} compared to the first PWM signal (PWM ₁ ) is delayed and ii. wherein each of the generated, in particular n, PDM signals (PDM ₁ to PDM _n ) represents one of the generated, in particular n PDM spreading codes. A method according to claim 1 characterized by, a. in that the offset (T _{off_i} ) of one, in particular all, of the ith PDM signals (PDM _i ) multiplies as PDM period duration (T _PDM ) with the number (i-1) divided by two, in particular multiplied by the number (i - 1) divided by the number n of PDM spreading codes, let calculate. Method for generating a PDM spread code modulated PDM output signal (PDM _out ), in particular for use in a DC voltage supply and / or a DC / DC converter, in particular for the supply of LEDs with electrical energy, especially in a car based on two, in particular n, PDM spreading codes, with n as a positive integer and n> 1, and a spreading code sequence of m consecutive PDM spreading codes of these n PDM spreading codes, with m as a positive , integer and m ≥ 1 and a spreading code period (T _select ), for generating an optimized PDM spectrum of the PDM output signal (PDM _out ), comprising the steps a. Generating a first PDM signal (PDM ₁ ) having a PDM period and a PDM period (T _PDM ) and a filling factor (f _cycle ) and a. Generating one, in particular n-1, further PDM signals (PDM ₂ , second PDM signal to PDM _n , n-th PDM signal) by respective delay of the first PDM signal (PDM ₁ ) and / or generation each delayed first PDM signal (PDM ₁ ) and i. each so generated i-th PWM signal (PDM _i) with 1 <i ≤ n a with respect to the first signal (PDM ₁₎ to a time i-th offset (T _{off_i)} compared to the first PWM signal (PWM ₁₎ is delayed and ii. wherein each of the n PDM signals (PDM ₁ to PDM _n ) represents one of the n PDM spreading codes. b. Selecting a kth PDM signal (PDM _k ) as the current PDM spreading code signal from the n PDM signals (PDM ₁ to PDM _n ) in response to a selection signal (PDM _select ). A method according to claim 3 characterized by, a. in that the offset (T _{off_i} ) of one, in particular all, of the ith PDM signals (PDM _i ) multiplies as PDM period duration (T _PDM ) with the number (i-1) divided by two, in particular divided by the number n the PDM spreading codes. A method according to claim 3 or 4 characterized by, a. in that the selection of the kth PDM signal (PDM _k ) takes place as the current PDM spread code signal at the beginning of a PDM period of the first PDM signal (PDM ₁ ). Method according to one or more of claims 3 to 5 characterized by, a. that in response to a first selection of a PDM signal (PDM ₁ to PDM _n ) as PDM spreading code in the form of the current PDM spreading code signal (PDM _k ) at a first spreading code selection time (T _SCS1 ) at the beginning of a PDM period of the first PDM signal (PDM ₁ ), the next next selection of a PDM spreading code at an immediately following second spreading code selection time (T _SCS2 ) at the beginning of a PDM period of the first PDM Signal (PDM ₁ ) after m PDM periods (T _PDM ), which corresponds to the spreading code period (T _select ), takes place. A method according to claim 6 characterized by, a. that the selection signal (PDM _select ) is a random signal. Method according to one or more of the preceding claims characterized by, a. the PDM signals (PDM ₁ to PDM _n ) assume a constant value in n-1 subsections with a total length of (n-1) / n of the PDM period duration (T _PDM ), which in ⌊ _fcycle ·n⌋ subareas 1 value and in n - ⌊f _cycle · n⌋ - 1 partial ranges corresponds to a 0 value and b. the PDM signals (PDM ₁ to PDM _n ) are modulated in a sub-region of length 1 / n of the PDM period (T _PDM ) with a pulse density which corresponds to the n-fold modulo of the filling factor (f _cycle ) times n. Method according to one or more of claims 3 to 8, characterized by the steps a. Division of a PDM period of the PDM period length (T _PDM ) into time slots (SL ₁ to SL _n ), in particular by a scrambler (SCR) and a. Formation of n scrambled PDM signals (PDM ₁ 'to PDM _n '), by interchanging (scrambling) signal sections of the PDM signals (PDM ₁ to PDM _n ) in each case one time slot of the time slots (SL ₁ to SL _n ) with each other in particular by a scrambler (SCR). A method according to claim 9 characterized by, a. in that the scheme of permutation is changed cyclically from time slot to time slot, in particular by a scrambler (SCR) during the spread code period (T _select ).

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