DE102007008683A1 - Apparatus and method for setting a sampling clock for broadband analog video signals - Google Patents

Abstract

contraption for setting a sampling clock (ta) for broadband analog video signals (Vin) having a pixel clock (tp) of a pixel frequency (fp), with means (A) for analyzing the pixel clock (tp) and means (V) for changing the sampling clock (ta) to sample clock frequency (fa) and phase (phia), where the means (A) are suitable for analysis in the analog video signal (Vin) image line-related gradient (G), caused by interference between the pixel clock frequency (fp) and the Sampling clock frequency (fa) arise when the analog video signal (Vin) is sampled at a wrong frequency, and the location (O) to detect the gradient and the means (V) to change such that the sampling clock (ta) is in the presence of gradients (G) is changed until no more gradients (G) be recorded.

Description

The The invention relates to an apparatus and method for adjusting a sampling clock for broadband analog video signals according to the preamble features of the claims 1 or 7.

at the processing of video signals, the z. B. generated by graphics cards you are confronted with the situation, with many to work on different image formats. An image format is among other things, characterized in that it has a certain resolution, d. H. an exact number of pixels in horizontal and vertical direction, has. It is between a total A distinction is made between the number of pixels and an active number of pixels. The total Number of pixels also includes the areas of horizontal and vertical exchange gaps, in which among others Synchronization information is transmitted. The active one Number of pixels refers to the number of pixels, which is the pure image content represents.

Graphics cards as they are common in personal computers, for example, work time discretely, d. H. they send synchronously to an internal one Working clock one pixel at a time. For example, corresponds one XGA standard 1024 pixel active horizontal and 768 pixels Pixels in the vertical direction. The total number of pixels is doing 1344 pixels in the horizontal direction and 806 pixels in vertical Direction. A complete XGA standard image consists of 1083264 pixels, so the graphics card needs 1083264 clocks, to send a whole analogue XGA image. In a presentation with a frequency of 60 frames per second that means that 1083264 × 60 = 64995840 cycles per second needed for transmission become. This frequency is called the pixel clock frequency. Becomes such an analog video signal back into a digital system fed into video signal processing, it must be in this with a frequency corresponding to the pixel clock frequency. If a sampling is performed at a frequency that deviates from the pixel clock frequency, so arise in the scanned Image so-called artifacts that correspond to a moiree pattern, the by the interference between the pixel clock frequency and the sampling clock frequency arises, d. H. the image will be blurred at the appropriate places.

In order to be able to set the correct sampling clock with the appropriate correct sampling frequency during sampling, it has begun to standardize the image transmission. In such a standard, for. B. VESA standard, in addition to the active and the total image resolution other parameters such. B. the line frequency and the frame rate defined. According to the prior art, such as. B. the US 6 522 365 , of the US 709996 or the US 6922188 , Various methods are known to measure the line and / or frame rate and / or the number of lines and to close on the basis of this information on the transmitted format and thus the resolution on the associated pixel clock or sampling frequency.

This However, known practice has several vulnerabilities in practice on. For one thing, there are several different ones in the VESA standard, for example Timing definitions that make up different pixel clock frequencies and therefore give different sampling frequencies to be set. For an XGA standard 1024 × 768 image Pixel at 60 Hz he gives it pixel clock frequencies, the between 63.50 MHz and 64.99 MHz vary. On the other hand, that graphics card manufacturers do not always adhere to the exact format definitions, as prescribed by the VESA standard, and therefore the pixel clock deviates from the given frequency. Another The weak point is that image formats that do not comply with a VESA standard can not be processed, d. h. that it is not possible is an unknown format that does not match any standard exactly adjust. Another disadvantage of the previously known methods is that in the measurements made for the format detection whoever, the picture content as far as possible unchanged should remain, which in strongly moving images to considerable problems leads.

The The object of the invention is a device and a method for setting the sampling clock for broadband analogue Provide video signals that make it possible to the sampling clock frequency for an unknown format, the moreover, it does not have to correspond to a standard, exactly adjust.

These Task is solved by a device with the features of patent claim 1 and a method having the features of the claim 7th

advantageous Further developments of the invention are the subject of the dependent claims.

The basic idea of the invention is a moiree pattern, that when sampling at a wrong frequency due to interference between the pixel clock frequency and the sampling clock frequency, for adjusting the sampling clock frequency and the phase of the sampling clock to use.

If an analog video signal z. B. oversampled, then in addition to the plateaus of the pixels and the pixel transitions are sampled. In these transitions the picture is out of focus and gives a moi ree-stripe pattern. In order to detect these transitions, signal gradients are determined in the analog video signal, it merely being necessary to determine whether a gradient exists or not. If the sampling clock deviates from the pixel clock by one clock period, a fuzzy column appears in the picture. If you z. B. 12 cycles over or undersampled, so you can see 12 blurred stripes.

It is therefore a device for setting a sampling clock for broadband analog video signals with a pixel clock a pixel clock frequency, the means for analyzing the Pixel clocks and means for changing the sampling clock in frequency and phase, the means being suitable for analysis, image-line interference that occurs when the analogue Video signal is sampled at a wrong frequency and to control the means for varying such that the Sample clock changed in the presence of interference for so long until no interference is detected.

Prefers the means of analysis are designed so that the interference detected by a gradient in the analog video signal at the sampling point become.

Prefers are the means of analysis and the means of change designed such that in the presence of gradients a first Location of the gradient is recorded, then the phase the sampling clock is changed and then a second location the gradient is detected. Based on the recorded locations of the gradients Subsequently, a direction of movement is determined and the sampling clock is changed based on the determined direction of movement.

It is advantageous that, based on the determined direction of movement of the gradient and with the information about which direction the phase has been shifted, it can be determined whether an overscan or a subscan takes place. With a shift of the phase to the right and a present oversampling, the detected gradients also travel to the right, ie the detected second location of the gradients after the phase shift lies further to the right in the image line. If, on the other hand, there is an undersampling, the gradients travel to the left and the detected second location accordingly lies further to the left in the image line. In the case of a phase shift to the left (reduction of the phase angle), the same applies inversely, ie in the case of over-sampling, the gradients travel to the left, and in the case of undersampling, to the right. To determine the gradient, for example, the method of the German Patent Application No. 10 2005 025 453.5 "Device for determining a measure of signal change and phase control method" can be used.

In a preferred embodiment of the invention is provided that means of analysis means for changing such control that in the presence of gradients and identical first Place and second place of the gradient, the frequency remains constant and only the phase of the sampling clock is changed until no more gradients are detected.

Advantageous in this embodiment, it is recognized that when the pixel clock frequency and the sampling frequency coincide, and thus faster convergence of the algorithm is ensured.

In A preferred embodiment is when no gradients detected be checked if the analog video signal is applied.

in this connection the advantage lies in the fact that it is wrongly excluded a correct sampling clock is suspected, although no image information are available, and only for that reason no gradients be detected in the sampled signal.

In In a further preferred embodiment, the means for Analysis designed such that a picture line in several equal size Sections is divided and the line-related determined gradient over a whole picture in a histogram summed up according to their sections become.

in the Ideally, there are the same number of sections as sampling cycles, for hardware reasons, however, this is not always favorable, so that this embodiment also brings benefits. Especially it is possible to measure the beginning and the end of the Adjust the overall section of a picture line, so that individual sections of the picture can be displayed enlarged. Thereby, that the line-related determined gradients over a whole picture summed and evaluated by a histogram Furthermore, clear information about the gradient distribution and thus the shape of the interference pattern obtained.

In A preferred embodiment of the invention are the means for Analysis partially or completely implemented as software.

A Embodiment of this form has the advantage that z. B. for histogram analysis or to determine the direction of movement of the gradients easily various methods and algorithms can be used. It is Z. B. conceivable, the movement of the gradient by means of correlation Fourier transformation or through a cluster analysis. Also, a determination of the position of the gradient by means of threshold or other methods is conceivable.

In a preferred embodiment of the invention are the means for Changing the sampling clock as a phase-locked-loop (PLL) for setting the frequency and as a delay-locked-loop (DLL) for Setting the phase formed.

A Such implementation has the advantage that the frequency and the phase of the sampling clock with PLL and DLL circuits very accurate can be adjusted.

According to the independent claim 8 is a method for adjusting a sampling clock in frequency and phase for broadband analogue Video signals that occupy one pixel clock of one pixel frequency exhibit. According to the inventive method If the analog video signal is sampled at the sample clock, it will be image-based in the sampling signal gradient and their Determined location in the analog video signal and the sampling clock in his Sampling frequency and its phase changed until, until no more gradients are detected.

To In a preferred procedure, the analysis becomes a first Location of the gradient recorded, then the phase of Changed sampling clock, and then a second location of the Gra served detected. On the basis of the detected places is a direction of movement of the Gradients by which the sampling clock is changed is determined.

This Method has the advantage already described above, that based the direction of movement of the gradient with information about the Direction of the phase shift can be determined whether an over- or subsampling. That has the advantage that so a targeted change in the sampling frequency possible is.

According to one more preferred method is the sampling clock frequency of the sampling clock in the presence of gradients and identical first and second Location of the gradients kept constant and only the phase of the sampling clock changed until no more gradients are detected.

Advantageous At this procedure is that is recognized, if the correct Sampling frequency is present and the phase matching of optimal sampling point can be adjusted.

According to one preferred development of the method is a picture line in divided into several equal sections and the line related determined gradients are over an entire picture in one Histogram summed up according to their sections.

Advantageous At this procedure is that by the summation over an entire picture a clear statement about the distribution the gradient is obtained.

The Invention will be described below with reference to an embodiment with the help of the attached figures closer explained. Show it:

1 a first block diagram of a circuit according to the invention,

2 a second, more detailed block diagram of a circuit according to the invention,

3 exemplary signal waveforms for the analog input signal, the sampled signal and the detected gradients and

4 an exemplary flowchart for a method according to the invention.

This in 1 illustrated block diagram of an embodiment of the invention shows an analog video signal Vin with a pixel clock tp, a scanning device 1 having. The scanning device 1 performs a sampling with a sampling clock ta having a sampling clock frequency fa and a phase phia and providing a sampled signal Va. The sampled signal Va can be supplied, for example, to a computer monitor which, for reasons of clarity, is not shown. Furthermore, in the sampling of the analog video signal Vin by an analysis device A, which determines whether in the analog video signal Vin Gradienten G are present at the sampling point, and image-line-determined, at which location O, these gradients G are. The analysis device A, in turn, controls a changing device V which is suitable for changing the sampling clock ta in its sampling clock frequency fa and its phase phia in accordance with the analysis.

This in 2 shown block diagram shows a further refinement of the block diagram 1 , The analog video signal Vin is supplied to an analog-to-digital converter (ADC) by simultaneously implementing a function for determining the gradient G. The analyzer A is according to 2 divided into a hardware and a software part. The hardware part is a pixel-clock-recovery-sensor PCR, to which the analog-to-digital converter ADC information about the gradient G, a vertical synchronous signal Vsync and a horizontal synchronizing signal Hsync are supplied. The horizontal sync signal Hsync indicates the end of each image line, the vertical sync signal Vsync the end of an entire image. By means of the two synchronizing signals Vsync, Hsync, it is possible for the pixel-clock-recovery-sensor PCR, the line-determined information via the gradient G into a histogram, in which the line-by-line information is summed over an entire image. The histogram determined by the pixel clock recovery sensor PCR is made available to an analysis software which evaluates the histogram and accordingly controls the modifying means V.

The changing means V is according to 2 from a phase-locked loop, a so-called phase-locked-loop PLL and a delay-coupled control loop, a so-called delay-locked-loop DLL. In this case, the phase-locked loop PLL can be fed with the vertical synchronizing signal Vsync, which marks the end of an entire picture. The phase locked loop PLL is further controlled by the analysis software and serves to generate the sample clock frequency fa. The sampling clock frequency can be supplied to the delay-locked-loop DLL, which, controlled by the analysis software, sets the phase angle phia between the sampling clock ta and the pixel clock tp.

By recursive looping through this loop will be optimal Setting the sampling clock ta reached.

In 3 For example, exemplary waveforms for the analog video signal Vin, the sampled video signal Va, and the detected gradients G are shown. In the case of the analog video signal Vin, a line with 640 pixels is shown, from which a sampled clock of 642 clocks per line produces a sampled signal Va. As can be seen in the representation of the sampled signal Va, amplitude drops occur at two points, which can vary depending on the phase position. This in 3 represented signal G shows the gradient G, which can be determined from the analog video signal Vin. If the phase of the sampling clock is changed at the pixel clock, then the amplitude drops and correspondingly the detected gradients G change their position in the line being examined, and it can be concluded from this movement whether an overscan or a subscan is present.

This in 4 Flowchart shown shows a possible implementation of the method according to the invention.

In a first step will be the phase-locked-loop PLL, the delay-locked-loop DLL and the pixel clock recovery sensor PCR initialized. Subsequently the sampling clock ta is set and in a following step the histogram by the pixel clock recovery sensor PCR off the line-related determined data of the gradient G created was read in. If a new format is detected, then the next step to the initialization process jumped back. If there is no new format, then the read in histogram examined on gradient heaps. If no gradient clusters are detected, then Checks whether image data exists, and if so, jump to the end of the process. Do not lie Image data before, so the previous procedure from the reading of the Go through the histogram again. In the event that gradient heap be determined, in a next step, the position the gradient heap determined. Subsequently, the position the gradient heap from the currently read histogram with the position of the gradient clusters from the histogram of the previous one Measurement compared and determined a partial direction of movement. Becomes in the following step determines a phase shift, the smaller is a clock period, so in the next step, the sampling clock ta changed by a fraction of the sample clock period and the procedure is repeated from the time the histogram is read. is the determined phase shift is greater than one Clock period, then in the following step, the resulting direction of movement the gradient heap determined. If a movement is detected, then In a following step, the sampling frequency fa becomes dependent adapted to the direction of movement and the search algorithm used and the sampling clock ta is set again. Is used in the determination the movement direction detected no movement, so the phase phia of the sampling clock ta is changed as long as until no more gradients are detected. Do not become gradients detected more, the process is completed.

1

scanning

A

medium for analysis, analysis device

G

gradient

V

medium for changing, changing device

Vin

analog video signal

Va

sampled video signal

ta

sampling

fa

sampling clock

øa

phase

tp

pixel clock

fp

pixel clock frequency

O

place

ADC

Analog to digital converter

PLL

Phase-locked-loop

DLL

delay-locked-loop

Vsync

Vertical sync

Hsync

Horizontal synchronization signal

PCR

pixel clock recovery sensor

R

movement direction

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• US 6522365 [0004]
• US 709996 [0004]
• - US 6922188 [0004]
• - DE 102005025453 [0014]

Claims (12)

Apparatus for setting a sampling clock (ta) for broadband analog video signals (Vin) having a pixel clock (tp) of a pixel frequency (fp), means (A) for analyzing the pixel clock (tp) and means (V) for changing the sampling clock (ta ) in sampling clock frequency (fa) and phase (phia) characterized in that the means (A) for analyzing, when sampling the analog video signal Vin, to detect image line related interference between the pixel clock frequency (fp) and the sampling clock frequency (fa) arise when the analog video signal (Vin) is sampled at a wrong frequency, and the means (V) for changing control so that the sampling clock (ta) is changed in the presence of interference until no interference is detected. Device according to claim 1, characterized in that that the interference due to a gradient in the analog video signal (Vin) are recognized. Device according to claim 2, characterized, that the means (A) for analysis and the means (V) for changing are designed in such a way - that in the presence of gradients (G), a first location (O1) of the gradients (G) is detected Then, the phase (phia) of the sampling clock (ta) is changed and then a second location (O2) of the gradients (G) is detected becomes, - that on the basis of the recorded places (O1, O2) a Movement direction (R) of the gradient (G) is determined, and - that the sampling clock (ta) based on the determined direction of movement (R) is changed. Device according to one of the preceding claims, characterized in that the means (A) for analysis are the means (V) to modify such that in the presence of gradient (G) and identical first location (O1) and second location (O2) of the gradient (G), the sampling frequency (fa) remains constant and only the phase (phia) of the sampling clock (ta) changes until no more gradients (G) are detected. Device according to one of the preceding claims, characterized in that the means (A) are designed for analysis are checked that if no gradients (G) are detected is whether an analog video signal (Vin) is present. Device according to one of the preceding claims, characterized in that the means (A) are designed for analysis are that a picture line in several equal sections is divided and the line-related determined gradient (G) via a whole picture in a histogram summed up according to their sections become. Device according to one of the preceding claims, characterized in that the means (A) for analysis partially or completely implemented as software. Device according to one of the preceding claims, characterized in that the means for changing the Sampling clock (ta) a phase-locked-loop (PLL) to set the Sampling frequency (fa) and a delay-locked-loop (DLL) for setting the phase (phia). Method for setting a sampling clock (ta) with a sampling frequency (fa) and a phase (phia) for broadband analog video signals (Vin) with one pixel clock (tp) a pixel clock frequency (fp), characterized by the steps - scanning of the analog video signal (Vin) with the sampling clock (ta) with the Frequency (fa) and phase (phia), - image-based Determination of gradients (G) and their location (O) in the analog video signal (Vin), and - changing the sampling clock (ta) in sampling frequency (fa) and phase (phia) to no gradients (G) more are recorded. Method according to claim 9, characterized, - that in the analysis, a first location (O1) of the gradients (G) is detected, then the phase (phia) of the sampling clock (ta) changed and then a second location (O2) of the gradients (G) is detected becomes, - that on the basis of the recorded places (O1, O2) a Movement direction (R) of the gradient (G) is determined, and - that the sampling clock (ta) based on the determined direction of movement (R) is changed. Method according to claim 9 or 10, characterized in the presence of gradients (G) and identical first Location (O1) and second location (O2) of the gradient (G), the sampling frequency (fa) remains constant and only the phase (phia) of the sampling clock (ta) changes until no more gradients (G) are detected. Method according to one of claims 9 to 11, characterized in that a picture line in several equal size Sections is divided and the line-related determined gradients (G) over an entire image in a histogram after their sections are summed up.