DE102004063702B4 - A method of manufacturing a semiconductor device having an HfNx layer on a Hf-containing layer - Google Patents
A method of manufacturing a semiconductor device having an HfNx layer on a Hf-containing layer Download PDFInfo
- Publication number
- DE102004063702B4 DE102004063702B4 DE102004063702A DE102004063702A DE102004063702B4 DE 102004063702 B4 DE102004063702 B4 DE 102004063702B4 DE 102004063702 A DE102004063702 A DE 102004063702A DE 102004063702 A DE102004063702 A DE 102004063702A DE 102004063702 B4 DE102004063702 B4 DE 102004063702B4
- Authority
- DE
- Germany
- Prior art keywords
- layer
- forming
- contact hole
- line
- containing layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
- Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
- Y10T428/264—Up to 3 mils
- Y10T428/265—1 mil or less
Abstract
Verfahren
für die
Herstellung eines Halbleiter-Bauelements,
das folgende Schritte umfasst:
Ausbilden mindestens einer Schutzisolierschicht
(23, 24) auf einer Cu-Leitung (22) in einem Substrat (21),
Ausbilden
eines Kontaktloches in der mindestens einen Schutzisolierschicht
(23, 24), um einen Abschnitt der Cu-Leitung (22) freizulegen,
Ausbilden
einer Hf-haltigen Schicht (26) in dem Kontaktloch, um den freigelegten
Abschnitt der Cu-Leitung
(22) abzudecken, und
Ausbilden einer leitenden Schicht (28,
31) über
dem Substrat einschließlich
der Hf-haltigen Schicht (26), wobei der Schritt des Ausbildens einer
leitenden Schicht (28, 31) das Ausbilden einer HfNx-Schicht (30) auf
der Hf-haltigen Schicht (26) durch Glühen der Hf-haltigen Schicht
(26) umfasst.Method for the production of a semiconductor device, comprising the following steps:
Forming at least one protective insulating layer (23, 24) on a Cu line (22) in a substrate (21),
Forming a contact hole in the at least one protective insulating layer (23, 24) to expose a portion of the Cu line (22),
Forming an Hf-containing layer (26) in the contact hole to cover the exposed portion of the Cu line (22), and
Forming a conductive layer (28, 31) over the substrate including the Hf-containing layer (26), the step of forming a conductive layer (28, 31) forming an HfN x layer (30) on the Hf-containing one Layer (26) by annealing the Hf-containing layer (26).
Description
ALLGEMEINER STAND DER TECHNIKGENERAL PRIOR ART
ErfindungsgebietTHE iNVENTION field
Die vorliegende Erfindung betrifft ein Verfahren für die Herstellung eines Halbleiter-Bauelements, durch das eine Cu-Leitung mit einer Cu/Hf-Grenzfläche und hervorragenden Eigenschaften ausgebildet werden kann, indem man Hf (Hafnium), einen leistungsfähigen Sauerstofffänger, dazu benutzt, an der Cu-Leitung anhaftenden Sauerstoff (in Form einer Cu-Oxidschicht) zu entfernen.The The present invention relates to a method for the production of a semiconductor device, by a Cu line with a Cu / Hf interface and excellent properties can be formed by adding Hf (hafnium), a powerful oxygen scavenger, to it used, on the Cu-line adhering oxygen (in the form of a Cu-oxide layer) to remove.
Erläuterung der verwandten TechnikExplanation of the related art
Cu ist allgemein ein beliebtes Material beim Verbinden von Metallleitungen. Eine obere Schicht (d.h. ein Verdrahtungsabschnitt zwischen einem Verbindungs-Pad und einem Gehäuse bei der Kapselung) setzt dennoch unverändert Al ein. Da eine Cu-Oberfläche stark oxidiert, kann Sauerstoff durch die oxidierte Cu-Oberfläche in eine tiefer liegende Metallschicht diffundieren und eine Korrosion des in der tiefer liegenden Schicht enthaltenen Cu auslösen. Darüber hinaus ist allgemein bekannt, dass ein Al-Pad für die Verdrahtung bei der Kapselung vorteilhaft ist.Cu is generally a popular material when joining metal lines. An upper layer (i.e., a wiring portion between a Connection pad and a housing in encapsulation) Al still sets in unchanged. Because a Cu surface is strong oxidized, oxygen can pass through the oxidized Cu surface into a deeper metal layer diffuse and corrosion of the in the deeper layer Cu cause. Furthermore It is well known that an Al pad is used for wiring during encapsulation is advantageous.
Auf
der ersten Isolierschicht
Der konventionelle Metallverdrahtungsprozess entfernt jedoch manchmal das Oxid auf der Cu-Oberfläche nicht oder überätzt manchmal die Cu-Leitung und verursacht eine Beschädigung der Cu-Leitung in der tiefer, liegenden Schicht.Of the However, conventional metal wiring process sometimes removes the oxide on the Cu surface not or sometimes over-etched the Cu line and causes damage to the Cu line in the deep, lying layer.
Aus
der
Die
Die
Die
KURZFASSUNG DER ERFINDUNGSUMMARY OF THE INVENTION
Dementsprechend betrifft die vorliegende Erfindung ein Verfahren für die Herstellung eines Halbleiter-Bauelements, das im Wesentlichen ein oder mehrere auf Einschränkungen und Nachteile der verwandten Technik zurückzuführende Probleme vermeidet.Accordingly The present invention relates to a process for the preparation a semiconductor device that is essentially one or more on restrictions and disadvantages of the related art avoids problems.
Es ist eine Aufgabe der vorliegenden Erfindung, ein Verfahren für die Herstellung eines Halbleiter-Bauelements bereitzustellen, durch das Oxid auf einer Cu-Oberfläche nach dem Kontaktloch-Ätzen unter Verwendung von Hf (Hafnium) als Barrierematerial thermodynamisch entfernt (z.B. gefangen) werden kann.It It is an object of the present invention to provide a process for the preparation a semiconductor device to be provided by the oxide on a Cu surface after contact hole etching Use of Hf (hafnium) as a barrier material thermodynamically can be removed (e.g., caught).
Zusätzliche Vorteile, Ziele und Merkmale der Erfindung werden teilweise in der nachfolgenden Beschreibung dargelegt, und teilweise werden sie sich Fachleuten bei Betrachtung des nachfolgenden Textes oder durch das Praktizieren der Erfindung erschließen. Die Ziele und andere Vorteile der Erfindung lassen sich durch den Aufbau umsetzen und erreichen, der in der schriftlichen Beschreibung und den Ansprüchen davon sowie in den beigefügten Zeichnungen speziell dargelegt wird.additional Advantages, objects and features of the invention are set forth in part in the The following description will set out and in part will become apparent to those skilled in the art looking at the following text or practicing to open the invention. The objectives and other advantages of the invention can be achieved by the Implement and achieve the structure in the written description and the claims and in the attached drawings specifically set out.
Um diese Ziele und andere Vorteile zu erreichen, und gemäß dem hier zum Ausdruck gebrachten und allgemein beschriebenen Zweck der Erfindung enthält ein Verfahren für die Herstellung eines Halbleiter-Bauelements gemäß der vorliegenden Erfindung folgende Schritte: Ausbilden mindestens einer Schutzisolierschicht auf einer Cu-Leitung in einem Substrat, Ausbilden eines Kontaktloches in der mindestens einen Schutzisolierschicht, um einen Abschnitt der Cu-Leitung freizulegen, Ausbilden einer Hf-Schicht in dem Kontaktloch, um den freigelegten Abschnitt der eingebetteten Cu-Leitung abzudecken, und Ausbilden einer leitenden Schicht auf dem Substrat einschließlich der Hf-Schicht.In order to attain these objects and other advantages, and in accordance with the purpose of the invention as expressed and broadly described herein, a method of fabricating a semiconductor device according to the present invention includes the steps of forming at least one protective insulating layer on a Cu line in one Substrate, forming a contact hole in the at least one protective insulating layer to expose a portion of the Cu line, forming a Hf layer in the contact hole to cover the exposed portion of the buried Cu line; and forming a conductive layer on the substrate including the Hf layer.
Die Hf-Schicht ist vorzugsweise 5–50 nm dick.The Hf layer is preferably 5-50 nm thick.
Die Hf-Schicht wird vorzugsweise durch IPVD (Ionized Physical Vapor Deposition) ausgebildet.The Hf layer is preferably by IPVD (Ionized Physical Vapor Deposition) trained.
Das Verfahren enthält vorzugsweise weiterhin den Schritt des Durchführens einer Vorreinigung mittels HF-Ätzen unter Verwendung von Ar+-Ionen, bevor die Hf-Schicht ausgebildet wird. Die Vorreinigung mittels HF-Ätzen entfernt besonders bevorzugt etwa 1–10nm der mindestens einen Schutzisolierschicht.The method preferably further includes the step of performing a pre-cleaning by means of RF etching using Ar + ions before the Hf layer is formed. The pre-cleaning by means of HF etching particularly preferably removes about 1-10 nm of the at least one protective insulating layer.
Vorzugsweise wird eine auf dem freigelegten Abschnitt der Cu-Leitung ausgebildete Oxidschicht durch die Hf-Schicht reduziert.Preferably is formed on the exposed portion of the Cu line Oxide layer reduced by the Hf layer.
Die leitende Schicht auf der Hf-haltigen Schicht ist vorzugsweise Al-haltig.The conductive layer on the Hf-containing layer is preferably Al-containing.
Der Schritt des Ausbildens der leitenden Schicht enthält vorzugsweise folgende Schritte: Ausbilden einer HfNx-Schicht auf der Hf-Schicht, Ausbilden eines Wolfram-Stiftes auf der Hf-Schicht im Kontaktloch und Abscheiden von Al über dem Substrat einschließlich des Wolfram-Stiftes. Die HfNx-Schicht wird besonders bevorzugt durch schnelles thermisches Glühen oder Ofenglühen ausgebildet.The step of forming the conductive layer comprises preferably the steps of: forming a HfN x layer on the Hf layer, forming a tungsten pin on the Hf layer in the contact hole and depositing Al on the substrate including the tungsten pin. The HfN x layer is particularly preferably formed by rapid thermal annealing or furnace annealing.
Der Schritt der Ausbildung der leitenden Schicht umfasst vorzugsweise folgende Schritte: Abscheiden eines aus der aus TiN, Ta und TaN bestehenden Gruppe ausgewählten Elements und Ausbilden eines Wolfram-Stiftes auf dem abgeschiedenen Element.Of the Step of forming the conductive layer preferably comprises following steps: depositing one of TiN, Ta and TaN existing group selected Elements and forming a tungsten pin on the deposited element.
Selbstverständlich besitzen sowohl die vorangegangene allgemeine Beschreibung als auch die nachfolgende ausführliche Beschreibung der vorliegenden Erfindung beispielhaften und erläuternden Charakter und sollen eine weitere Erläuterung der beanspruchten Erfindung bereitstellen.Of course own both the foregoing general description and the following detailed Description of the present invention by way of example and illustrative and should have another explanation of the claimed invention.
KURZE BESCHREIBUNG DER ZEICHNUNGENBRIEF DESCRIPTION OF THE DRAWINGS
Die beiliegenden Zeichnungen, die für ein weitergehendes Verstehen der Erfindung sorgen sollen und in diese Anmeldung eingearbeitet sind und einen Bestandteil davon darstellen, veranschaulichen Ausführungsbeispiel(e) für die Erfindung und dienen zusammen mit der Beschreibung der Erläuterung des Prinzips der Erfindung. Es zeigen: The enclosed drawings, which are for to provide a further understanding of the invention and in this application are incorporated and constitute a part thereof, illustrate embodiment (e) for the Invention and together with the description of the explanation the principle of the invention. Show it:
die
AUSFÜHRLICHE BESCHREIBUNG DER ERFINDUNGDETAILED DESCRIPTION OF THE INVENTION
Es wird nun ausführlich auf die bevorzugten Ausführungsformen der vorliegenden Erfindung Bezug genommen, Beispiele dafür sind in den beiliegenden Zeichnungen veranschaulicht. Soweit dies möglich ist, werden für die gleichen oder ähnliche Teile in allen Zeichnungen die gleichen Bezugszahlen verwendet.It will now be detailed to the preferred embodiments refer to the present invention, examples are given in illustrated in the accompanying drawings. As far as possible, be for the same or similar Parts in all drawings use the same reference numbers.
Die vorliegende Erfindung betrifft zunächst eine Metallisierungsstruktur und ein Verfahren für das Ausbilden einer Metallleitung auf einer Cu-Verdrahtung und insbesondere ein Verfahren für das Entfernen einer CuOx-Schicht (z.B. eines natürlichen Oxids), die sich am Boden eines Kontaktloches auf einer Cu-Leitung ausbildet, ohne HF-Ätzen oder anderweitiges Vorreinigen des Kontaktloches.The present invention first relates to a metallization and a method for forming a metal line on a Cu wiring, and more particularly to a method for the removal of a CuO x layer (for example, a native oxide) located at the bottom of a contact hole on a Cu line forms, without HF etching or otherwise pre-cleaning the contact hole.
Und zwar betrifft die vorliegende Erfindung ein Verfahren zum Abscheiden einer Auskleidung in einem Kontaktloch, wodurch sich ein guter Kontaktlochwiderstand sicherstellen lässt, indem CuOx reduziert, eine umfangreiche Ausbildung von Oxiden in der Auskleidung (z.B. Hf) vermieden und eine leitende (z.B. Metall-) Grenzfläche mit darunter liegendem Cu ausgebildet wird, indem man Hf (Hafnium) in dem Kontaktloch und auf einer freiliegenden Cu-Oberfläche abscheidet, statt den konventionellen Vorreinigungsprozess mittels HF-Ätzen zu verwenden.Namely, the present invention relates to a method of depositing a liner in a contact hole, which can ensure good contact hole resistance by reducing CuO x , avoiding extensive formation of oxides in the liner (eg, Hf), and forming a conductive (eg, metal) Forming interface with underlying Cu by precipitating Hf (hafnium) in the contact hole and on an exposed Cu surface, instead of using the conventional pre-cleaning process by means of RF etching.
Die vorliegende Erfindung ist indessen durch die Verwendung einer Hf-haltigen Schicht als Verbindungs- und/oder Barriereschicht gekennzeichnet. Hf, bei dem es sich um ein Metall von hervorragender Reaktivität mit Sauerstoff handelt, reduziert eine CuOx-Schicht, die nach der Beendigung einer Kontaktloch-Ätzung ohne den Einsatz der konventionellen Vorreinigung mittels HF-Ätzen am Boden eines Kontaktloches vorhanden sein kann, und stellt dadurch eine saubere und/oder leitende Grenzfläche zu einer Cu-Oberfläche bereit, wodurch ein guter Cu/Al-Grenzflächenwiderstand sichergestellt wird.However, the present invention is characterized by the use of a Hf-containing layer as a bonding and / or barrier layer. Hf, which is a metal of excellent reactivity with oxygen, reducing a CuO x layer, which may be present after the termination of a contact hole-etching without the use of the conventional pre-purification by means of HF etching at the bottom of a contact hole, and thereby provides a clean and / or conductive interface to a Cu surface, thereby ensuring good Cu / Al interface resistance.
Für die thermodynamische Reduzierung von CuOx durch Hf beträgt die Gibbssche Energie von HfO2 –352 kJ/mol bei 298 K, und die Gibbssche Energie von CuO beträgt etwa –297 kJ/mol bei 298 K. Daher wird Sauerstoff des natürlichen CuOx in der Hf-Schicht auf der CuOx-Schicht aufgefangen, wodurch das Cu mit einer sauberen Oberfläche versehen werden kann. Wenn Hf abgeschieden wird, wird CuOx an der Grenzfläche zwischen dem Boden des Kontaktloches und der tiefer liegenden Cu-Leitung effektiv entfernt, damit ein niedriger Kontaktlochwiderstand sichergestellt werden kann, während sich ein Kontaktloch-Ätzprofil unversehrt erhalten lässt, d.h. ohne Kontaktlochdeformation oder Vergrößerung der kritischen Abmessungen, die sich ergeben können, wenn zum Entfernen von Cu-Oxiden eine Vorreinigung mittels HF-Ätzen verwendet wird. Selbst wenn die Hf-Schicht im Bodenbereich dünner als etwa 5 nm ist, kann sie dessen ausreichenden Widerstand noch sicherstellen.For the thermodynamic reduction of CuO x by Hf, the Gibbs energy of HfO 2 is -352 kJ / mol at 298 K, and the Gibbs energy of CuO is about -297 kJ / mol at 298 K. Therefore, oxygen of the natural CuO x in of the Hf layer on the CuO x layer, whereby the Cu can be provided with a clean surface. When Hf is deposited, CuO x is effectively removed at the interface between the bottom of the contact hole and the underlying Cu line to allow a low contact hole to be deposited can be ensured, while maintaining a contact hole etch profile intact, ie, without contact hole deformation or increase in the critical dimensions, which can result when a pre-cleaning by means of HF etching is used to remove Cu oxides. Even if the Hf layer in the bottom region is thinner than about 5 nm, it can still ensure its sufficient resistance.
Die
In
In
In
Die Hf- oder HfN-Schicht kann mittels IPVD ausgebildet werden, bei der Hf für die Abscheidung auf der Cu-Oxidschicht mittels PVD ionisiert wird (wobei die Ausbildung von HfNx die IPVD von Hf in einer Stickstoffumgebung umfassen kann). Dadurch wird die Beschleunigung und das einfache Betriebsverhalten des ionisierten Hf im Vergleich zum gewöhnlichen PVD oder Sputtern verbessert, so dass sich die Reduzierung der Cu-Oxidschicht durch physikalische Einwirkung oder dergleichen beim Abscheiden der Hf-Schicht auf der Cu-Oxidschicht erreichen (oder aktivieren) lässt.The Hf or HfN layer may be formed by IPVD in which Hf is ionized by PVD for deposition on the Cu oxide layer (where the formation of HfN x may include the IPVD of Hf in a nitrogen ambient). Thereby, the acceleration and the simple performance of the ionized Hf are improved as compared with the ordinary PVD or sputtering, so that the reduction of the Cu oxide layer by physical action or the like can be achieved (or activated) in depositing the Hf layer on the Cu oxide layer. leaves.
Alternativ dazu kann die Hf- oder HfNx-Schicht nach der Beendigung der Vorreinigung mittels HF-Ätzen ausgebildet oder abgeschieden werden. Dadurch kann Hf nach einer Minimierung der HF-Ätzdauer abgeschieden und die durch A+-Ionen während des HF-Ätzens verursachte Deformierung des Kontaktlochprofils minimiert werden. Und zwar kann die Reduktionseigenschaft der Hf-Schicht verbessert sein, nachdem das Cu-Oxid durch die Ar+-Ionen aktiviert worden ist. Bei der Durchführung der HF-Ätzung wird die zu entfernende Dicke auf 1–10nm in Bezug auf ein thermisches Siliziumoxid (SiOx) der ersten oder der zweiten Isolierschicht eingestellt. Daher kann eine minimale physische Bombardierung der Cu-Oxidschicht während der Vorreinigung mittels HF-Ätzen ausreichend sein, um deren Reduzierung durch die Hf-Schicht zu aktivieren sowie die Deformierung des Kontaktlochprofils zu minimieren.Alternatively, the Hf or HfN x layer may be formed or deposited after completion of the pre-cleaning by means of RF etching. This allows Hf to be deposited after minimizing the RF etch time and minimizing the deformation of the via profile caused by A + ions during RF etching. Namely, the reduction property of the Hf layer can be improved after the Cu oxide is activated by the Ar + ions. In performing the RF etching, the thickness to be removed is set to 1-10nm with respect to a thermal silicon oxide (SiO x ) of the first or second insulating layer. Therefore, minimal physical bombardment of the Cu oxide layer during pre-cleaning by means of RF etching may be sufficient to activate its reduction by the Hf layer as well as minimizing the deformation of the via profile.
Dementsprechend entfernt die vorliegende Erfindung Cu-Oxid vor der Ausbildung des Kontaktlochstiftes unter Verwendung von Hf-Abscheidung statt Vorreinigung mittels Ätzen, wodurch (1) eine Vergrößerung der kritischen Abmessung (CD = Critical Dimension) des Kontaktloches durch die Vorreinigung mittels Trockenätzen und (2) ein Vordringen des Cu-Oxids entlang der Cu-Oberfläche verhindert oder minimiert wird. Die vorliegende Erfindung ermöglicht weiterhin die Beibehaltung der dem Entwurf entsprechenden kritischen Abmessung des Kontaktloches, sie verhindert, dass der Bodenbereich des Kontaktloches während einer Vorreinigung mittels Nassätzen durch die Reinigungslösung vergrößert wird und Sauerstoff oder Feuchtigkeit (aufgrund der Sauerstofffangeigenschaften der Hf-Schicht) durch den Pad zur Cu-Verdrahtung diffundiert.Accordingly, the present invention removes Cu oxide prior to the formation of the via pin using Hf deposition rather than prepurification by etching, thereby (1) increasing the contact dimension critical dimension (CD) by pre-cleaning by dry etching and (2) Preventing or minimizing penetration of the Cu oxide along the Cu surface. The present invention further enables the retention of the critical dimension of the contact hole corresponding to the design, it prevents the bottom portion of the contact hole Contact hole is enlarged by wet etching through the cleaning solution during pre-cleaning and oxygen or moisture (due to the oxygen-sensing properties of the Hf layer) diffuses through the pad to the Cu wiring.
Fachleuten wird klar sein, dass an der vorliegenden Erfindung verschiedene Modifikationen und Änderungen vorgenommen werden können. Die vorliegende Erfindung soll daher die Modifikationen und Änderungen dieser Erfindung mit abdecken, sofern sie in den Schutzbereich der beigefügten Ansprüche und ihrer Äquivalente fallen.professionals It will be clear that different from the present invention Modifications and changes can be made. The present invention is therefore intended to cover the modifications and variations Covering this invention, provided they are within the scope of the attached Claims and their equivalents fall.
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0100978 | 2003-12-30 | ||
KR1020030100978A KR100573897B1 (en) | 2003-12-30 | 2003-12-30 | Method for fabricating semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102004063702A1 DE102004063702A1 (en) | 2005-09-22 |
DE102004063702B4 true DE102004063702B4 (en) | 2008-01-31 |
Family
ID=34737937
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102004063702A Expired - Fee Related DE102004063702B4 (en) | 2003-12-30 | 2004-12-28 | A method of manufacturing a semiconductor device having an HfNx layer on a Hf-containing layer |
Country Status (5)
Country | Link |
---|---|
US (1) | US7098134B2 (en) |
JP (1) | JP2005197710A (en) |
KR (1) | KR100573897B1 (en) |
CN (1) | CN100338756C (en) |
DE (1) | DE102004063702B4 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100574560B1 (en) * | 2004-12-31 | 2006-04-27 | 동부일렉트로닉스 주식회사 | Method for forming metal line of semiconductor device |
KR100763697B1 (en) * | 2006-09-01 | 2007-10-04 | 동부일렉트로닉스 주식회사 | Method for preventing a w stud residue at via mim process |
US7713866B2 (en) * | 2006-11-21 | 2010-05-11 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
CN110957261B (en) * | 2018-09-26 | 2022-11-01 | 长鑫存储技术有限公司 | Preparation method of semiconductor device interconnection structure barrier layer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5714418A (en) * | 1995-11-08 | 1998-02-03 | Intel Corporation | Diffusion barrier for electrical interconnects in an integrated circuit |
US5824597A (en) * | 1995-04-12 | 1998-10-20 | Lg Semicon Co., Ltd. | Method of forming contact hole plug |
US6077782A (en) * | 1997-02-28 | 2000-06-20 | Texas Instruments Incorporated | Method to improve the texture of aluminum metallization |
US20030216029A1 (en) * | 2001-06-20 | 2003-11-20 | Advanced Micro Devices, Inc. | Method of selectively alloying interconnect regions by deposition process |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0719841B2 (en) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | Semiconductor device |
JPH0774243A (en) * | 1993-06-30 | 1995-03-17 | Kawasaki Steel Corp | Fabrication of semiconductor device |
JPH0741948A (en) * | 1993-07-30 | 1995-02-10 | Sony Corp | Formation of wiring |
JPH07130743A (en) * | 1993-10-29 | 1995-05-19 | Sony Corp | Wiring structure of semiconductor device and formation thereof |
US6069068A (en) | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US6130161A (en) | 1997-05-30 | 2000-10-10 | International Business Machines Corporation | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity |
JPH1187510A (en) * | 1997-07-10 | 1999-03-30 | Kawasaki Steel Corp | Wiring structure, forming method thereof, and semiconductor integrated circuit applying thereof |
JPH11204644A (en) * | 1998-01-20 | 1999-07-30 | Sony Corp | Semiconductor device and its manufacture |
US6180523B1 (en) * | 1998-10-13 | 2001-01-30 | Industrial Technology Research Institute | Copper metallization of USLI by electroless process |
KR100505449B1 (en) | 1998-12-24 | 2005-10-14 | 주식회사 하이닉스반도체 | Method of forming polyside gate electrode of semiconductor device |
US6235633B1 (en) * | 1999-04-12 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process |
JP3235062B2 (en) * | 1999-07-26 | 2001-12-04 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
JP3851752B2 (en) | 2000-03-27 | 2006-11-29 | 株式会社東芝 | Manufacturing method of semiconductor device |
KR100531464B1 (en) | 2000-06-30 | 2005-11-28 | 주식회사 하이닉스반도체 | A method for forming hafnium oxide film using atomic layer deposition |
JP3576143B2 (en) * | 2001-03-01 | 2004-10-13 | 株式会社東芝 | Semiconductor device and method of manufacturing semiconductor device |
JP4350337B2 (en) | 2001-04-27 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device |
KR100390849B1 (en) | 2001-06-30 | 2003-07-12 | 주식회사 하이닉스반도체 | Method for fabricating capacitor having hafnium oxide |
US20030011043A1 (en) | 2001-07-14 | 2003-01-16 | Roberts Douglas R. | MIM capacitor structure and process for making the same |
US6461914B1 (en) | 2001-08-29 | 2002-10-08 | Motorola, Inc. | Process for making a MIM capacitor |
US6838352B1 (en) | 2002-07-05 | 2005-01-04 | Newport Fab, Llc. | Damascene trench capacitor for mixed-signal/RF IC applications |
KR100476376B1 (en) | 2002-07-19 | 2005-03-16 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
US7023093B2 (en) * | 2002-10-24 | 2006-04-04 | International Business Machines Corporation | Very low effective dielectric constant interconnect Structures and methods for fabricating the same |
US6949461B2 (en) * | 2002-12-11 | 2005-09-27 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure |
JP4571781B2 (en) * | 2003-03-26 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US6955986B2 (en) * | 2003-03-27 | 2005-10-18 | Asm International N.V. | Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits |
JP2005150280A (en) * | 2003-11-13 | 2005-06-09 | Toshiba Corp | Manufacturing method of semiconductor device and semiconductor manufacturing device |
-
2003
- 2003-12-30 KR KR1020030100978A patent/KR100573897B1/en not_active IP Right Cessation
-
2004
- 2004-12-27 JP JP2004376944A patent/JP2005197710A/en active Pending
- 2004-12-28 DE DE102004063702A patent/DE102004063702B4/en not_active Expired - Fee Related
- 2004-12-29 US US11/027,839 patent/US7098134B2/en not_active Expired - Fee Related
- 2004-12-30 CN CNB2004101041819A patent/CN100338756C/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5824597A (en) * | 1995-04-12 | 1998-10-20 | Lg Semicon Co., Ltd. | Method of forming contact hole plug |
US5714418A (en) * | 1995-11-08 | 1998-02-03 | Intel Corporation | Diffusion barrier for electrical interconnects in an integrated circuit |
US6077782A (en) * | 1997-02-28 | 2000-06-20 | Texas Instruments Incorporated | Method to improve the texture of aluminum metallization |
US20030216029A1 (en) * | 2001-06-20 | 2003-11-20 | Advanced Micro Devices, Inc. | Method of selectively alloying interconnect regions by deposition process |
Also Published As
Publication number | Publication date |
---|---|
KR20050070769A (en) | 2005-07-07 |
CN100338756C (en) | 2007-09-19 |
JP2005197710A (en) | 2005-07-21 |
DE102004063702A1 (en) | 2005-09-22 |
US20050153116A1 (en) | 2005-07-14 |
US7098134B2 (en) | 2006-08-29 |
KR100573897B1 (en) | 2006-04-26 |
CN1649124A (en) | 2005-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE4342047B4 (en) | Semiconductor component with a diffusion barrier layer arrangement and method for its production | |
DE102005057075B4 (en) | Semiconductor device having a copper alloy as a barrier layer in a Kupfermetallisierungsschicht and method for its preparation | |
DE10059773B4 (en) | Semiconductor device | |
DE112010003936B4 (en) | Semiconductor unit with a copper connection | |
DE102012216153B4 (en) | Semiconductor components with copper compounds and processes for their manufacture | |
DE102006033319B4 (en) | Method for producing a semiconductor device in semiconductor chip size with a semiconductor chip | |
DE102008016427B4 (en) | Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protective layer | |
DE60036305T2 (en) | SELF-ADJUSTED METAL COVERINGS FOR INTERMEDIATE LAYER METAL CONNECTIONS | |
DE102008016431B4 (en) | Metal capping layer with increased electrode potential for copper-based metal regions in semiconductor devices and method for their production | |
DE4222142A1 (en) | SEMICONDUCTOR COMPONENT WITH A WIRING LAYER AND METHOD FOR THE PRODUCTION THEREOF | |
DE102011053149B4 (en) | The structure, die arrangement, and method of processing a die | |
DE19945820A1 (en) | Semiconductor device has an interlayer of titanium, molybdenum, tungsten or silicides or nitrides between and in contact with a connection layer and a connection pad electrode layer | |
DE19844451A1 (en) | Barrier layer structure, especially for copper interconnections in a VLSI | |
DE102006051491A1 (en) | Metallization layer stack with an aluminum termination metal layer | |
DE112017001420B4 (en) | Techniques for Improving Reliability in Cu Interconnects Using Cu Intermetallics | |
DE10301243A1 (en) | Method for producing an integrated circuit arrangement, in particular with a capacitor arrangement, and integrated circuit arrangement | |
DE102004063702B4 (en) | A method of manufacturing a semiconductor device having an HfNx layer on a Hf-containing layer | |
DE102011050953A1 (en) | Tracks and pads and methods of making same | |
DE102019118681B4 (en) | Power metallization structure for semiconductor devices | |
DE3343367A1 (en) | SEMICONDUCTOR COMPONENT WITH HUMPER-LIKE, METAL CONNECTION CONTACTS AND MULTIPLE-WIRE WIRING | |
DE102004063149B4 (en) | Method for producing a semiconductor device | |
DE10339990B4 (en) | A method of fabricating a metal line having increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line | |
DE102017113515B4 (en) | Method for forming an electrically conductive contact and electronic device | |
DE102005035771B4 (en) | Technique for producing a copper-based contact layer without an end metal | |
DE2134291A1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8127 | New person/name/address of the applicant |
Owner name: DONGBU ELECTRONICS CO.,LTD., SEOUL/SOUL, KR |
|
8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |
Effective date: 20140701 |