DE10153609A1 - Production of an electronic component used in chip technology comprises forming a first planar chip arrangement, forming a further planar chip arrangement, optionally applying interconnecting elements and forming electronic components - Google Patents

Abstract

Production of electronic component comprises: forming first planar chip arrangement by arranging functional chips at a distance from each other in a grid and filling the gaps with a filler; forming and/or arranging a further planar chip arrangement on the first chip arrangement; optionally applying interconnecting elements; and forming electronic components by removing frames of chip arrangements. Production of an electronic component comprises: forming a first planar chip arrangement by arranging functional chips at a distance from each other in a grid and filling the gaps with a filler to form a frame for isolating the chips and for forming an electrical contact to another chip of another chip arrangement; forming and/or arranging a further planar chip arrangement as in the first step on the first chip arrangement so that the chips and the frames of the arrangements lie over each other and the contact elements of both chip arrangements are connected together for a chip-chip contact; optionally repeating the previous step; optionally applying interconnecting elements according to use; and forming electronic components by removing the frames of the chip arrangements. An Independent claim is also included for the electronic component produced. Preferred Features: The first chip arrangement is produced using a support on which the chips are fixed using an adhesive. The support is a self-adhesive foil or strip or a passivated silicon support.

Description

The invention relates to a method for producing a electronic component with several superimposed stacked and contacted with each other on a chip Component carrier mountable and several on the component provided contact elements on the component carrier is contacted.

Known method for producing a device with several stacked chips in the third dimension can be roughly divided into two groups. For one thing Stacking of packaged chips, on the other hand stacking Bare chips. When stacking packaged chips, these become stacked on top of each other and with their contact elements (legs) connected with each other. Examples are z. B. stacked TSOP or stacked BOC. Draw these three-dimensional designs itself by so-called Interposer (thin or thick Boards or Leadframes) for connection between the stack levels, where these interposer are mounted on the chips and with suitable ones Method are connected to the chip-side contact elements. This method is expensive because of its installation effort it is based on a single process flow, d. H. it will processed exclusively separate individual packaged chips. Due to the sometimes necessary Interposer are the resulting components of considerable height. A thinning of the Chips during the stacking process is due to the already made possible housing.

A device produced by stacking naked chips On the other hand allows a lower construction height. The chip / chip Connection system leads through the respective chip. The to necessary fine Kontaktierungsvias are usually in one Generated a frontend-like process (Via etch / passivation / Via-filling). However, this process has crucial Disadvantages for the application. First, it sets a special one Chip design ahead, the generation of contacting or Passage vias allowed. The generation of the vias is very expensive, because they come in an additional, relatively long process of Frontend processes must be created. Although the essential processes can be carried out at the disk level, arise when stacking nude chips on disk level nevertheless difficulties regarding the yield. As each Slice only a finite yield of working chips has, when stacking the discs increases the risk for a working stack, the yield decreases exponentially with increasing stacked number of slices. An economic Component manufacturing by this method is not possible.

The invention is based on the problem, a method indicate that in a simple way the production is relatively low built-up components with high yield allows.

• a) Erzeugen einer ersten ebenen Chipanordnung durch zueinander beabstandetes Anordnen von funktionstüchtigen Chips in einem Raster und Verfüllen zumindest der Abstände zwischen den Chips mit einem Füllmittel zur Bildung eines die Chips fixierenden isolierenden Halterahmens mit chipeigenen, der elektrischen Kontaktierung zu einem anderen Chip einer anderen Chipanordnung dienenden, im Bereich des Halterahmens vorgesehenen Kontaktierungselementen und chipeigener Umverdrahtung,
• b) Erzeugen und/oder Anordnen einer weiteren ebenen Chipanordnung nach Schritt a) auf der ersten Chipanordnung derart, dass die Chips und die Halterahmen der beiden Chipanordnungen übereinander liegen und die jeweiligen Kontaktierungselemente der beiden Chipanordnungen für die elektrische Chip-Chip-Kontaktierung miteinander verbunden werden,
• c) gegebenenfalls ein- oder mehrmaliges Wiederholen des Schrittes b), und
• d) Vereinzeln der jeweils aus mehreren übereinander gestapelten Chips der einzelnen Chipanordnungen bestehenden Bauelemente durch Auftrennen der Halterahmen der fest miteinander verbundenen Chipanordnungen.

To solve this problem, a method of the type mentioned above is provided according to the invention with the following steps:

• a) producing a first planar chip arrangement by arranging functional chips in a grid spaced apart from one another and filling at least the spacings between the chips with a filler to form a chip-fixing insulating support frame with on-chip, the electrical contact with another chip of another chip assembly serving , provided in the region of the support frame contacting elements and on-chip rewiring,
• b) generating and / or arranging a further planar chip arrangement after step a) on the first chip arrangement in such a way that the chips and the holding frames of the two chip arrangements lie above one another and the respective contacting elements of the two chip arrangements are connected to one another for the electrical chip-chip contacting .
• c) if necessary, one or more repetitions of step b), and
• d) singulating the each of a plurality of stacked stacked chips of the individual chip assemblies existing components by separating the holding frame of the firmly interconnected chip assemblies.

The inventive method first proposes the creation a wafer consisting exclusively in a previous one Test as functionally tested chips. This so-called "Known Good Wafer" is by rastermäßig Position the chips and embed them in one insulating holding frame, preferably by means of a viscous non-conductive polymer used as filler is produced, manufactured. It is conceivable, either like chips or even different chips in theirs Properties and / or dimensions are different in these Integrate wafers. This wafer or this first level Chip arrangement is so by fan-out wafer-level packaging produced. This support frame for the fan-out wafer-level packaging is now used not only for fan-out, but serves also to the vias from the chip front to Chip back to take over, d. H. the via becomes shifted to the holding frame area. The following will now be on this way creates another chip arrangement, ie piled up, with the chips and the support frame congruent be positioned one above the other when the multi-chip stack is off similar or equal chips is constructed. It is but also possible, different in the different levels or different sized chips to arrange, in which case not always a congruent stacking due to the Size differences is possible. The above step will be so often repeated as separate chip layers are provided. Are all Chip layers stacked on top of each other, so are the individual Components by separating the stack in the area of Holding frame isolated.

The inventive method has over the known Process considerable advantages. First, it is a complete wafer-level process, as at disk level is worked and only after the components in their Entity generated by forming the stack were singling he follows. Because only working chips used the yield is very high. It can all Standard chips are used, being similar or different chips can be integrated in each level. Farther It is a very cost effective process because the contact vias for the contacts not by the conductive Silicon crystal with more expensive technology must be led, but through the support frame, resulting in much simpler thin-film and / or thick-film processes can take place. Further acts it is a process sequence that is very low Process temperatures (<150 ° C) can be performed, which is no has additional burden on the chips. Also allows that Stacking of chips or wafers, which are de facto naked, the Production of components with extremely low height, wherein during manufacture a very low risk regarding handling and breakage.

The inventive method allows a structure of a Multi-chip arrangement without mounting an additional Item, e.g. B. an interposer. Rather, here are the Chip assemblies directly set or built on each other. The Redistribution of the chips takes place immediately at wafer level, ie directly in the plane of the wafer and can be in wafer level Technology (thin film / thick film) are processed. This allows each surrounding a chip holding frame, as Contacting area serves, d. H. the electric chip chip Contacting (or even the module board) takes place in the area of the holding frame. In addition to a minimum of required Contact transitions (mechanical and especially electrical) are characteristic Such a manufactured multi-chip device also by his low height and the small lateral dimensions.

In a further development of the inventive idea can be provided that at least the first chip arrangement using a Carrier on which the chips are attached by means of an adhesive be generated. As a carrier can be a self-adhesive Foil or a self-adhesive tape can be used alternatively, the use of a on its surface preferably passivated silicon carrier conceivable.

• - Aufbringen der Kontaktierungselemente an vorbestimmten Positionen auf den Träger,
• - Befestigen der Chips auf dem Träger,
• - Erzeugen des isolierenden Halterahmens,
• - Entfernen des Trägers,
• - Erzeugen der Umverdrahtungen,
• - Anbringen von Verbindungsklebepunkten, wobei zwei Chipanordnungen anschließend über die Verbindungsklebepunkte miteinander verbunden werden.

A first alternative of the invention is characterized in that the individual chip arrangements are manufactured separately and then connected to one another. Ie. Each individual chip arrangement is manufactured in the form of a separate known-good wafer with the chip grid and the holding frame, these individual chip arrangements being first stacked and connected to one another after their manufacture. In this case, a separate chip arrangement can be produced, for example, with the following steps:

• Applying the contacting elements at predetermined positions on the carrier,
• - fixing the chips on the carrier,
• Generating the insulating support frame,
• Removing the carrier,
• - generating the rewiring,
• - Attaching bonding adhesive points, wherein two chip assemblies are then connected to each other via the bonding bonding points.

The carrier thus initially serves as a stabilizing element the contacting elements are applied and then the chip is positioned and the holding frame is generated. Then the carrier can be removed, as the then already finished finished good wafers is sufficiently stable. Finally, the rewiring is generated and the Bonding points of mainly conductive adhesive attached, after which two chip arrays are connected together. there is the holding frame expediently in its thickness dimensioned that the contacting elements protrude from it. The filler to form the support frame should expediently, the chips on their free side under education cover at least partially a protective layer, d. H. the Chips are on their side facing away from the carrier, free side expediently completely poured into the filler. The chips themselves are with their contacting side, on the the redistribution is to be applied to the carrier, so For example, the tape, attached, with the rewiring after removing the carrier is applied on this side.

As a bonding adhesive, with which the adhesive bonding points are formed, is expediently a conductive adhesive used on the side freed from the carrier exposed contacting elements, which there evenly with the Holding frame and the contacting side of the chip run, are arranged, is applied. After completion of the Aufstapelvorgangs is finally on the upper chip assembly a Protective coating applied.

As described, this method is characterized that the individual chip arrangements separately in the form of individual wafers are produced and then these wafers be connected and contacted. An alternative In contrast, the invention provides that another Chip arrangement on an already existing chip arrangement is built. Each new die / wafer layer will be on one already existing massive (thick, stable) chip arrangement mounted, which in particular for the handling of the ever thicker expectant stacks is an advantage.

• - Erzeugen weiterer Kontaktierungselemente der weiteren Chipanordnung auf den oberseitig freiliegenden Kontaktierungselementen der unteren Chipanordnung,
• - Aufbringen der Chips der weiteren Chipanordnung oberhalb und vorzugsweise deckungsgleich mit den Chips der unteren Chipanordnung,
• - Erzeugen des isolierenden Halterahmens derart, dass die Kontaktierungselemente noch aus dem Chip hervorragen und das Füllmittel die Chips oberseitig bis auf die chipseitigen Kontaktpads als Isolationsschicht abdeckt,
• - Erzeugen der Umverdrahtungen,
  wobei die Schritte sooft wiederholt werden, wie Chipanordnungen übereinander zu stapeln sind.

Another chip arrangement, which is built on an existing one, can be produced according to the invention with the following steps:

• Generating further contacting elements of the further chip arrangement on the upper-side exposed contacting elements of the lower chip arrangement,
• Applying the chips of the further chip arrangement above and preferably congruent with the chips of the lower chip arrangement,
• Generating the insulating holding frame in such a way that the contacting elements still protrude from the chip and the filling means covers the chips on the upper side except for the chip-side contact pads as an insulating layer,
• - generating the rewiring,
  wherein the steps are repeated as many times as chip assemblies are to be stacked on top of each other.

By generating the respective further contacting elements the vias are realized from top to bottom. Subsequently, the chips in the predetermined grid positioned and generates the support frame. The filler is so introduced that chips it down to the chip side Contact pads insulated on top, what for the following Generation of the rewiring is required.

• - Erzeugen der Kontaktierungselemente der ersten Chipanordnung auf dem Träger, insbesondere einem Silizium-Träger,
• - Aufbringen der Chips der ersten Chipanordnung,
• - Erzeugen des isolierenden Halterahmens derart, dass die Kontaktierungselemente noch aus dem Halterahmen hervorragen und das Füllmittel die Chips oberseitig bis auf die chipeigenen Kontaktpads als Isolationsschicht abdeckt,
• - Erzeugen der Umverdrahtungen.

The first chip arrangement, that is to say the lowest arrangement on which a further chip arrangement is constructed, can be produced with the following steps:

• Generating the contacting elements of the first chip arrangement on the carrier, in particular a silicon carrier,
• Applying the chips of the first chip arrangement,
• Producing the insulating holding frame in such a way that the contacting elements still protrude from the holding frame and the filling means covers the chips on the upper side except for the chip-own contact pads as an insulating layer,
• - Generating the rewiring.

It is expedient if, after the generation of the holding frame including the chips partially covering Frame section, the filling evenly ablative Cleaning step takes place, whereby a flat surface is generated, what for the subsequent generation of the rewiring is advantageous. In addition, the overall height is slightly thinner.

• a) Erzeugen von Umverdrahtungsbahnen mit Kontaktierungspunkten auf einem Träger, insbesondere einem vorzugsweise passivierten Silizium-Träger,
• b) Befestigen der bereits mit einer Umverdrahtung versehenen Chips mit ihrer die Umverdrahtung aufweisenden Seite zum Träger weisend, so dass die Umverdrahtung mit den Umverdrahtungsbahnen des Trägers verbunden werden,
• c) Erzeugen des Halterahmens derart, dass die Chips auch an ihrer freien Seite in das Füllmittel eingebettet werden, wobei in dem Halterahmen Kontaktvias zur Durchkontaktierung zu den darunter liegenden Kontaktierungspunkten ausgebildet werden,
• d) Erzeugen weiterer Umverdrahtungsbahnen mit Kontaktierungspunkten und -elementen, die die Kontaktvias füllen,

wonach die Schritte a) bis d) zur Bildung einer oder mehrere weiterer Chipanordnungen wiederholt werden. As an alternative to the production of the first and each further chip arrangement of the type described above in a structure of a chip arrangement on an existing one, a second method variant provides for generating the first chip arrangement (and also each further one) with the following steps:

• a) generating rewiring paths with contact points on a carrier, in particular a preferably passivated silicon carrier,
• b) attaching the chips already provided with a rewiring with their side having the rewiring facing the carrier so that the rewiring is connected to the rewiring paths of the carrier,
• c) generating the holding frame in such a way that the chips are also embedded in the filler on their free side, wherein contact vias are formed in the holding frame for the through-connection to the contacting points located underneath,
• d) generating further redistribution paths with contact points and elements that fill the contact vias,

after which steps a) to d) are repeated to form one or more further chip arrangements.

In this embodiment of the invention so chips are on the Carrier or an existing chip arrangement applied, which are already provided with a rewiring. It are only on the carrier or a lower Chip arrangement rewiring tracks, on the one hand by a aufzusetzenden chip to be contacted and the other hand in the Run area of the holding frame, generated.

After attaching the chips can be beneficial to the reduction the thickness of chip material are removed, d. H. here is active the thickness of a chip and thus the overall height of the chip resulting device reduced. The removal of the Chip material can be prepared by wet or dry etching or by mechanical treatment done.

The chips themselves are made by means of a non-conductive adhesive attached, since the actual contacting over the Rewiring tracks and the contact points and elements about the contact vias take place. After the generation of the last Chip assembly are at the top contact elements for Contact the components to be separated below with the Carrier generated, this being for both procedural Embodiments in which a chip arrangement on an already existing is established.

While the foregoing embodiments of the inventive method for contacting the rewiring paths two chip levels passing through the holding frame Provide contacting elements is basically also the Possibility to connect the rewiring tracks directly to each other to contact. A first, a quasi-direct contacting performing Embodiment is the method variant described above, be formed in the contact vias in the support frame, which then filled directly during the generation of the rewiring paths be, d. H. the rewiring tracks and their contacts in the Contact vias to the underlying rewiring level produced together.

• a) Anordnen der Chips auf einem Träger,
• b) Erzeugen des Halterahmens derart, dass die Chips zeitlich an ihren freien Seiten bis auf einen die Kontaktpads freilassenden Bereich in das Füllmittel eingebettet sind,
• c) Erzeugen von Umverdrahtungsbahnen, die sich bis in den Bereich der zwischen den Chips befindlichen Halterahmenabschnitte erstrecken, wobei die derart positionierten Enden der Umverdrahtungsbahnen die Kontaktelemente zur nachfolgend aufzubauenden oder anzuordnenden Chipanordnung bilden,
• d) Aufbringen eines nicht-leitenden Klebemittels zur Fixierung der Chips der zweiten Chipanordnung und zur Isolierung gegenüber den darunter liegenden Umverdrahtungsbahnen derart, dass die Kontaktelemente der ersten Chipanordnung frei liegen, und Aufbringen der Chips der zweiten Chipanordnung,
• e) Aufbringen eines nicht-leitenden weiteren Füllmittels zur Bildung eines Halterahmens derart, dass es die Chips seitlich und oberseitig bis auf den Bereich der Kontaktierungspads abdeckt, wobei die Kontaktelemente der ersten Chipanordnung nach wie vor frei bleiben,
• f) Erzeugen der Umverdrahtungsbahnen der zweiten Chipanordnung, die endseitig mit den Kontaktelementen der ersten Chipanordnung kontaktiert werden,
• g) gegebenenfalls ein- oder mehrmaliges Wiederholen der Schritte d) bis f).

In contrast, an embodiment enabling an immediate rewiring contact of two levels provides the following steps:

• a) arranging the chips on a carrier,
• b) generating the holding frame in such a way that the chips are embedded in the filler in time at their free sides except for an area leaving the contact pads free,
• c) generating rewiring paths which extend into the region of the holding frame sections located between the chips, the ends of the rewiring paths thus positioned forming the contact elements for the subsequently to be arranged or arranged chip arrangement,
• d) applying a non-conductive adhesive for fixing the chips of the second chip arrangement and for insulation with respect to the underlying rewiring paths such that the contact elements of the first chip arrangement are exposed, and applying the chips of the second chip arrangement,
• e) applying a non-conductive further filling agent to form a holding frame such that it covers the chips laterally and on the top side except for the area of the contacting pads, the contact elements of the first chip arrangement still remaining free,
• f) generating the rewiring paths of the second chip arrangement which are contacted at the end with the contact elements of the first chip arrangement,
• g) if necessary, one or more repetitions of steps d) to f).

In this embodiment of the invention, therefore, serve the ends of the Rewiring tracks themselves as contact elements to each adjacent redistribution level. The individual retaining frame of Chips of a second chip arrangement are doing so dimensioned that they embed the chip largely, but the Ends of the redistribution paths of the underlying chip level do not cover. The rewiring tracks of the second Chip arrangement now run on the support frame laterally in the underneath lying plane, where they immediately with the ending there Rewiring tracks are connected.

The contacting elements and the Umverdrahtungsbahnen and their contact points are suitably from a produced conductive polymer. They are preferably printed.

As a filler is as described suitably a non-conductive polymer used, printed on, sprayed on or spin-coated. Generally, after generating the Holding frame, especially if this one a chip covering section, a step to reduce the Thickness of the filler while leveling the surface respectively.

Besides the method, the invention further relates to electronic component with several stacked chips, the after one of the described variants of the method is produced.

Furthermore, the invention relates generally to a electronic component with multiple stacked chips, each one Chip own Umverdrahtungsbahnen has. The invention Component is characterized in that each chip in one Holding frame that surrounds him at least laterally added is, with the running into the area of the holding frame Rewiring paths of superimposed chips in the area of the holding frame are contacted with each other.

In the device according to the invention advantageously takes place electrical chip-chip contacting or ultimately the Contacting the module board, on which a finished processed chip is set, in the area of the holding frame to which the Rewiring paths from the central contact pads of a chip are guided. The inventively provided support frame provides So the required lateral area, one to the outside To allow drawn contact. It is therefore at component according to the invention no between two chips set items such as Interposer or The like required, but the chips can almost directly be stacked on top of each other. The rewiring between two Chips are thus directly, the rewiring of a individual chips from the central contact pads on the Holding frame runs quasi in the chip level. You reach in this way an element with a minimum of particular electrical Contact transitions due to avoidance of interposition additional interposer or the like.

In this case, the rewiring paths via contact elements be connected to each other, these contact elements as Durchkontaktierungselemente the contact through a support frame of the rewiring path of a first chip to the Rewiring path of a second chip. The can Contact elements of a first chip and the rewiring path a second chip directly or via a conductive adhesive be connected to each other.

Alternatively, there is also the possibility that Wiring paths directly to each other to connect, so without a den Holding frame through-contacting contact element. This can such that the rewiring paths of a chip on the side of the level of the chip above or below be guided and there on the Umverdrahtungsbahnen this Chip level are contacted. There is also the possibility of the Rewiring tracks by means of a conductive adhesive to connect with each other.

Overall, the inventive structure of a component the ability to switch between each chip level positioning interposer or the like to work. About that in addition, due to the immediate stacking the chips a component with a very low height getting produced. This also applies to the lateral Extensions, there for the respective support frame and there provided contacts also relatively little space needed becomes.

The contact elements and the rewiring tracks themselves are suitably made of a conductive polymer and can in known technologies are generated. It is useful furthermore, if the support frame has a chip both laterally as well at least partially covers on one of its flat side. Also a provided on the top chip protective coating, the optionally also covers the lower chips laterally, is appropriate.

Further advantages, features and details of the invention result from those described below Embodiments. Showing:

FIGS. 1a-1j, the individual process steps for manufacturing a device by preparing single separate chip assemblies are connected to each other,

FIGS. 2a-2l, the individual process steps for manufacturing a device in which a chip assembly is mounted on an existing chip arrangement,

Fig. 3a-3o the process steps for manufacturing a device in which a chip assembly is mounted on an existing chip array wherein individual chips are used with pre-arranged rewiring, and

Fig. 4a-4j, the process steps for manufacturing a device in which the Umverdrahtungsbahnen two chips can be contacted directly with each other.

FIGS . 1a-1j essentially show the method steps for producing separate chip arrangements in the form of known-good wafers, which are subsequently stacked on top of one another and contacted with each other and subsequently singulated.

Starting from a carrier 1 shown in Fig. 1a, which may be, for example, a conductive elastic polymer, such as conductive silicone in the form of a tape or a film, are applied to this via elements 2 , preferably printed, which expediently also from a conductive polymer. Already at this point it should be noted that in all representations of all figures, only a section of a chip arrangement is shown with only one chip. Of course, the chip arrangement continues laterally. A chip arrangement or a known-good wafer is expediently produced in customary wafer dimensions, for example with a diameter of 30 cm, which is why an arbitrarily large number of chips can be arranged depending on the respective size of a single chip and the selected grid.

According to FIG. 1b is a directed in a previous test to be functional tested chip 3 with its contact side to the carrier 1 is preferably affixed to the adhesive on its top support 1. It is obviously placed between the via elements 2 . According to Fig. 1c, a holding frame 4 is produced using an insulating filler 5 , which can be done by printing, rinsing or spin-coating of the viscous filler 5 . The thickness of the holding frame is dimensioned such that on the one hand, the via elements 2 still protrude from it, on the other hand, the free chip side is covered, so that forms a protective layer over the chip. After application of the filler and curing of the same, it is preferably cleaned in a plasma cleaning step or a wet or dry cleaning step and, if necessary, somewhat worn away. After curing of the filler 5 already results in a sufficiently stable chip arrangement, so that according to Fig. 1d, the carrier 1 can be removed, ie the tape is peeled off in a simple manner.

According to FIG. 1e, a metallic rewiring 6 is now produced on the side freed from the carrier, wherein this rewiring connects the contact pads 7 , now exposed on the chip, to the respective via elements 2 . The generation of this rewiring can be produced by sputtering or plating a metal layer, subsequent lithography and a subsequent etching process. A closer discussion on this is not necessary because the skilled person sufficient methods for producing the rewiring are known.

According to FIG. 1f, a bonding adhesive 8 is then punctiformly applied to the exposed via elements on the contacting side. Via these connection adhesive points 8 , the chip arrangement 9 produced in this way is now conductively connected to a second chip arrangement 9 , which has been produced in the same way ( FIG. 1 g). These conductive connection adhesive points are primarily made of conductive silicone, which is cured after connecting the chip arrangements. Any number of chip arrangements 9 can be glued together and contacted to form a stack. Fig. 1h shows a total of 4 separate chip assemblies 9 , wherein on the top chip assembly 9 according to FIG. 1h back a protective cover 10 , mainly made of a non-conductive polymer is applied.

The stack formed in this way from a total of four separate chip assemblies 9 is thus completed, the entire structure was carried out as part of a fan-out wafer-level packaging.

After carrying out the step according to FIG. 1h, the separation of the individual components 11 takes place , for which purpose the holding frame is separated, preferably sawn up. In Fig. 1i, such a separated component 11 is shown. As FIG. 1i shows, after being singulated onto the through-connection elements 2 , which are exposed on the contacting side of the lower chip arrangement 9 , further connection bonding points 8 made of a conductive adhesive, for example conductive silicone, are applied, according to which, see FIG. 1j, the component 11 a component carrier, at the contacting side already contacting points or tracks 12 are provided, glued and thus contacted.

FIGS . 2a-2l show the most important method steps for the production of a three-dimensional component in fan-out wafer-level packaging, in which case a chip arrangement is constructed on a respectively existing chip arrangement.

To form the first "lowermost" chip arrangement, first through-contacting elements 14 , preferably made of conductive silicon, are applied, primarily pressed, onto a carrier 13 , for example a passivated silicon carrier. According to Fig. 2b, a chip 15 is glued with its contacting side 16 facing up to the carrier 13 using a suitable adhesive. Referring to Fig. 2c, a holding frame 17 is produced using an insulating filler 18 , for example, epoxy resin or silicone. The filler is primarily printed. The holding frame is dimensioned such that the feedthrough elements 14 are not covered on top of him. Furthermore, the holding frame 17 extends substantially over the chip 15 , but leaves the upper-side contact pad 19 of the chip 15 free in the middle. In the step according to FIG. 2 d, the surface of the holding frame 17 is cleaned, for example by plasma etching or wet etching, and the holding frame is removed a little. In the step according to FIG. 2e, rewirings 20 are now applied to the upper side of the chip 15 , which is partially covered by the holding frame 17 . These rewirings 20 contact the via elements 14 with the contact pads 19 . The generation of the rewirings 20 takes place by sputtering or plating on a metal layer, a subsequent lithography and a subsequent wet etching step. Upon completion of the process step of Fig. 2e, the first "lower" chip assembly 21 is completed.

Now, see Fig. 2f, congruent with the via elements 14 of the lower chip assembly 21 further via elements 14 are applied to this lower chip assembly 21 . In step nch Fig. 2g now a second chip 15 is set congruent over the already existing chip 15 of the first chip arrangement. The chip 15 is expediently provided on its rear side with a passivation layer, so that it is insulated from the rewiring of the lower chip arrangement 21 .

In the step according to FIG. 2h, a holding frame 17 is again described using a filler 18 in the same way as with respect to FIG. 2c. This is then cleaned (see Fig. 2d) and slightly removed. In the step according to FIG. 21, the generation of the rewiring 20 of the second chip arrangement or plane takes place. This in turn is followed by the steps according to FIGS. 2f et seq. These are repeated as often as chip arrangements are to build. FIG. 2j shows a configuration with four chip arrangements 21 , wherein two contacting elements 14 are set on the uppermost chip arrangement 21 . If the configuration is completely established, the components are separated by separating the holding frame of all stacked chip assemblies 21 . FIG. 2j shows a singulated component 22 .

For mounting the component 22 on a component carrier 23 , this is now turned over (flip chip), on the exposed contact elements 14 are adhesive bonding points 24 , for example of conductive silicone, applied, via which the component 22 then on the component carrier 23 by contacting the feedthrough 14 with carrier side Contact elements 25 is attached.

FIGS . 3a-3o show the relevant method steps for producing a component by constructing a chip arrangement on an already existing one, whereby chips are used here which have already been tested as being functional and provided with a rewiring.

The starting point is a chip 26 shown in FIG. 3a, which has already been tested as being functional. At its Kontaktierungsseite a rewiring 27 and corresponding contact points 28 is already generated.

As shown in Fig. 3b shows, for the preparation of the first lower die assembly on a support 29, for example, the passivated surface is a silicon wafer) mainly 31 applying a rewiring means of a conductive polymer or Umverdrahtungsbahnen 30 and Umverdrahtungskontaktpunkte using a conductive polymer is printed primarily , By means of a non-conductive adhesive 32 is now, see Fig. 3c, the chip 26, glued with its contact side, ie the side where the rewiring is applied to the carrier 29. In this case, the chip-side rewiring 27 and the rewiring contact points 28 are contacted with the corresponding rewiring paths 30 and the rewiring contact points 31 on the carrier 29 . If the connection has hardened, a material removal takes place on the chip 26 in the step according to FIG. 3e, ie the chip is made thinner. The material can be removed for example by dry or wet etching or a mechanical treatment. As can be seen clearly reduces the height of the first chip arrangement significantly.

In the step according to FIG. 3 f, the given configuration for forming a holding frame 33 is then embedded in a filling material 34 . For this example, insulating silicone is printed and then cured. The holding frame 33 has Kontaktungsvias 35 , which allows a subsequent via to the rewiring tracks and rewiring contact points 30 , 31 , which are applied to the support surface. In step 3 g, the surface of the holding frame 33, which also covers the chip, is now leveled by dry or wet etching or by mechanical treatment, and the holding frame is made somewhat thinner.

In the step according to FIG. 3h, the rewiring paths 36 and rewiring points for the next chip arrangement are now produced by printing on a conductive polymer. As can be seen, the conductive polymer fills the Kontaktvias 35 , so that a via to the underlying redistribution takes place.

Subsequently, a nonconductive adhesive 32 is applied again in the step according to FIG. 31, whereafter in the step according to FIG. 3j a further chip 26 is placed with its contacting side facing downwards and glued on. Again, when bonding the contacting of the rewiring 27 with the corresponding rewiring tracks 36 on the surface of the lower chip assembly 37th

After sticking the chip 26 (see FIG. 3k), the chip 26 is also thinned here (see FIG. 31). Subsequently, the embedding into a filling material to produce the holding frame with the contacting vias and the renewed generation of the rewiring paths takes place again, as described in FIGS. 3f-3h.

If the entire configuration is constructed, the result is a stack of chip arrangements 37 , as shown in FIG. 3 m. Here, too, four chip arrangements 37 are stacked on top of one another by way of example. Subsequently, the individual components by separating the holding frame, which are of course superimposed on each other as in all embodiments, isolated. Fig. 3 shows an isolated component m 38th On its exposed upper side, in step 3, n connection adhesive dots 39 are then applied using a conductive adhesive, by which the component 38 is subsequently glued and contacted ( FIG. 30) onto a component carrier 40 , on the upper side of which carrier-side contact points 41 are located.

FIGS . 4a-4j show a fourth variant of the method for producing a component according to the invention, in which case the rewiring paths of two superimposed chips are connected directly to one another.

On a support 42 , z. As a film or a glass substrate is, as shown in FIG. 4a, a non-conductive polymer layer 43 , z. B. imprinted or spin coated. Subsequently, see Fig. 4b, a chip 44 is applied to the upper side preferably adhesive polymer layer 43 , after which the polymer layer is cured.

As shown in FIG. 4c, a filler 45 is then applied and cured to form a chip frame 44 both laterally and also visible on the top side up to the area of the contact pads 46 covering the holding frame. As FIG. 4d shows, the rewiring paths 47 are subsequently produced, which can be seen to run into the region of the lateral holding frame sections. The ends of the rewiring paths 47 thereby form contact elements 48 , which serve for the subsequent contacting to a chip arrangement to be arranged above.

A nonconducting adhesive 49 is now brought to the arrangement known from FIG. 4d, for example in a printing method, wherein this adhesive layer is dimensioned such that the contact elements 48 formed by the ends of the rewiring web 47 remain free. Subsequently, a second chip 50 is glued ( Fig. 4f), after which the adhesive layer is cured.

In the step according to FIG. 4g, a further filling agent 51 is now applied, which embeds for forming a second chip 50 and embeds both laterally and on the upper side except for the region of the contact pads 52 . Also, this support frame is laterally dimensioned such that the contact elements 48 of the rewiring paths 47 of the underlying chip planes remain free. The filler can be applied for example in a printing process.

Finally, see FIG. 4h, the rewiring paths 53 of the chip 50 are produced, wherein the rewiring paths 53 run laterally over the holding frame down into the rewiring path plane of the chip 44 , where they can be contacted with the contact elements 48 , ie the ends of the rewiring paths 47 , The rewiring paths, as well as the redistribution paths of the underlying chip plane, can be produced by sputtering and plating as well as by suitable photolithographic steps.

As shown in FIG. 41, contact elements 54 and 55 are subsequently produced on the active side of chip 50 . In the contact elements 54 are conductive adhesively to be contacted interconnect elements, in the contact elements 55 in the example shown to Lotbällchen. Of course, only one type of contact elements can be provided. They serve to make the subsequent contact with a carrier.

The carrier 42 is finally removed and the individual multichip modules separated to form isolated components 56 by sawing (see the indicated lateral Sägespalte) or the like. The separation takes place by separation in the region of the lower holding frame, and this can also be done for example by laser cutter or the like.

Subsequently, such a device 56 via the contact elements 54 , 55 with a module board 57 , at the top contact points 58 are provided, are fixed and contacted. In the case of the contact elements 54 , this is done using a conductive adhesive, the contact elements 55 are fused in a conventional soldering process, so that the electrical contact is formed.

It should be noted at this point that FIGS . 4a-4j show the generation of a multi-chip component 56 with two chips. Of course, it is also possible to stack a plurality of chips one above the other, wherein the rewiring paths of the chips are each guided from top to bottom into the plane of the rewiring tracks 47 of the lowermost chip 44 . However, it is also conceivable to contact each rewiring path plane only with the underlying one, so that rewiring paths do not have to be led down too far laterally along the chip stack. However, in these embodiments, the lateral dimension of the respective chip frames increases somewhat. List of Reference Numbers 1 carrier
2 via elements
3 chip
4 holding frames
5 fillers
6 rewiring
7 contact pad
8 bonding adhesive
9 chip arrangement
10 protective cover
11 component
12 train
13 carriers
14 via element
15 chip
16 contacting page
17 holding frame
18 fillers
19 contact pad.
20 rewiring
21 chip arrangement
22 component
23 component carrier
24 connection adhesive points
25 contact element
26 chip
27 rewiring
28 contact point
29 carriers
30 rewiring track
31 rewiring contact point
32 glue
33 holding frame
34 filling material
35 contacting via
36 rewiring track 41 with contact element
37 chip arrangement
38 component
39 Connection adhesive point
40 component carrier
41 contact point
42 carriers
43 polymer layer
44 chip
45 fillers
46 contact pad
47 rewiring track
48 contact element
49 glue
50 chip
51 fillers
52 contact pad
53 Umwredrahtungsbahn
54 contact element
55 contact element
56 component
57 module board
58 contact point

Claims (34)

1. A method for producing an electronic component with a plurality of stacked and contacted chips, which is mountable on a component carrier and contactable via a plurality of provided on the component contact elements on the component carrier, comprising the following steps: a) producing a first planar chip arrangement by arranging functional chips in a grid spaced apart from one another and filling at least the spacings between the chips with a filler to form a chip-fixing insulating support frame with on-chip, the electrical contact with another chip of another chip assembly serving , in the region of the holding frame provided contacting elements and on-chip rewiring, b) generating and / or arranging a further planar chip arrangement after step a) on the first chip arrangement in such a way that the chips and the holding frames of the two chip arrangements lie above one another and the respective contacting elements of the two chip arrangements are connected to one another for the electrical chip-chip contacting . c) optionally repeating step b) once or several times, and d) optionally applying the interconnect elements to the application board e) singulating the each of a plurality of stacked stacked chips of the individual chip assemblies existing components by separating the holding frame of the firmly interconnected chip assemblies. 2. The method according to claim 1, characterized, that at least the first chip arrangement using a Carrier on which the chips are attached by means of an adhesive will be generated. 3. The method according to claim 2, characterized, that as a carrier, a self-adhesive foil or tape or an its surface preferably passivated silicon carrier is used. 4. The method according to claim 2 or 3, characterized, that the individual chip arrangements are manufactured separately and then be connected together. 5. The method according to claim 4, characterized in that a separate chip arrangement is produced with the following steps: Applying the contacting elements at predetermined positions on the carrier, - fixing the chips on the carrier, Generating the insulating support frame, Removing the carrier, - generating the rewiring, - attaching adhesive bonding points, wherein two chip arrays are subsequently interconnected via the bonding pads. 6. The method according to claim 5, characterized, that the holding frame is dimensioned in such a thickness that the contacting elements protrude from it. 7. The method according to claim 5 or 6, characterized, that the filler for forming the holding frame and the chips on its free side to form a protective layer at least partially covered. 6. The method according to any one of claims 5 to 7, characterized, that the chips with their contacting side, on which the Re-wiring is to be mounted on the carrier, and that the rewiring on the side freed from the carrier the chips is applied. 9. The method according to any one of claims 5 to 8, characterized, that uses as conductive adhesive a conductive adhesive which is on the side freed from the carrier exposed contacting elements is applied. 10. The method according to any one of claims 5 to 9, characterized, that after completion of the stacking process on the upper Chip arrangement is applied a protective coating. 11. The method according to any one of claims 1 to 3, characterized, that a further chip arrangement on an already existing Chip assembly is constructed. 12. The method according to claim 11, characterized in that a further chip arrangement is produced with the following steps: Generating further contacting elements of the further chip arrangement on the upper-side exposed contacting elements of the lower chip arrangement, Applying the chips of the further chip arrangement above and preferably congruent with the chips of the lower chip arrangement, Producing the insulating holding frame in such a way that the contacting elements still protrude from the holding frame and the filling means covers the chips on the upper side except for the chip-side contact pads as an insulating layer, - generating the rewiring, wherein the steps are repeated as many times as stacking chip arrays. 13. The method according to claim 12, characterized in that the first chip arrangement, on which a further chip arrangement is set up, is produced with the following steps: Generating the contacting elements of the first chip arrangement on the carrier, in particular the silicon carrier, Applying the chips of the first chip arrangement, Producing the insulating holding frame in such a way that the contacting elements still protrude from the holding frame and the filling means covers the chips on the upper side except for the chip-side contact pads as an insulating layer, - Generating the rewiring. 14. The method according to claim 12 or 13, characterized, that after the generation of the support frame including the Chips partially covering frame section a the Filling material evenly removing cleaning step takes place. 15. The method according to claim 11, characterized in that the first chip arrangement is produced with the following steps: a) generating rewiring paths with contact points on a carrier, in particular a preferably passivated silicon carrier, b) attaching the chips already provided with a rewiring with their side having the rewiring facing the carrier so that the rewiring is connected to the rewiring paths of the carrier, c) generating the holding frame in such a way that the chips are also embedded in the filler on their free side, wherein contact vias are formed in the holding frame for the through-connection to the contacting points located underneath, d) generating further redistribution paths with contact points and elements that fill the contact vias, after which steps a) to d) are repeated to form one or more further chip arrangements. 16. The method according to claim 15, characterized, that after attaching the chips to reduce the thickness Chip material is removed. 17. The method according to claim 15 or 16, characterized, that the chips are fixed by means of a non-conductive adhesive become. 18. The method according to any one of claims 15 to 17, characterized, that after generation of the last chip arrangement at the Top contact elements for contacting the following to isolating components are produced with a carrier. 19. The method according to claim 11, characterized by the following steps: a) arranging the chips on a carrier, b) generating the holding frame such that the chips are embedded laterally and on their free side except for an area leaving the contact pads free in the filler, c) generating rewiring paths which extend into the region of the holding frame sections located between the chips, the ends of the rewiring paths thus positioned forming the contact elements for the subsequently to be arranged or arranged chip arrangement, d) applying a non-conductive adhesive for fixing the chips of the second chip arrangement and for insulation with respect to the underlying rewiring paths such that the contact elements of the first chip arrangement are exposed, and applying the chips of the second chip arrangement, e) applying a non-conductive further filling agent to form a holding frame such that it covers the chips laterally and on the top side except for the region of the contacting pads, wherein the contact elements of the first chip arrangement remain free, f) generating the rewiring paths of the second chip arrangement which are contacted at the end with the contact elements of the first chip arrangement, g) optionally repeating steps d) to f) once or several times 20. The method according to any one of the preceding claims, characterized, that the contacting elements and the rewiring tracks and their contact points of a conductive polymer be generated. 21. The method according to any one of the preceding claims, characterized, that the contacting elements and the rewiring tracks and their contact points are printed. 22. The method according to any one of the preceding claims, characterized, in that a non-conductive polymer is used as filler. 23. The method according to claim 22, characterized, that the filler printed, sprayed or is spun on. 24. The method according to any one of the preceding claims, characterized, that after generating the holding frame, in particular when this one having a chip covering section, a Step to reduce the thickness of the filler Simultaneous leveling of the surface takes place. 25. The method according to claim 24, characterized, that the thickness reduction by wet or dry etching or done by mechanical treatment. 26. Electronic component with several stacked chips, prepared according to the method of any one of claims 1 to 25th 27. Electronic component with a plurality of stacked chips, each chip having its own rewiring paths, characterized in that each chip ( 3 , 15 , 26 , 44 , 50 ) is received in a holding frame which surrounds it at least laterally, wherein the up to the region of the holding frame running Umverdrahtungsbahnen ( 6 , 20 , 27 , 30 , 36 , 47 , 53 ) of superimposed chips in the region of the holding frame are contacted with each other. 28. Electronic component according to claim 27, characterized in that the rewiring paths ( 6 , 20 , 27 , 30 ) via contact elements ( 2 , 14 , 25 ) are interconnected. 29. Electronic component according to claim 28, characterized, that the contact elements of a first chip and the Rewiring paths of a second chip directly or via a conductive adhesive are connected together. 30. Electronic component according to claim 27, characterized in that the rewiring paths ( 36 , 47 , 53 ) are connected directly to each other. 31. Electronic component according to claim 30, characterized, that the rewiring tracks by means of a conductive adhesive connected to each other. 32. Electronic component according to one of claims 27 to 31, characterized in that the contact elements 2 , 14 , 25 ) and the rewiring tracks ( 6 , 20 , 27 , 30 , 36 , 47 , 53 ) are made of a conductive polymer. 33. Electronic component according to one of claims 27 to 32, characterized in that the holding frame at least partially covers a chip ( 3 , 15 , 26 , 44 , 53 ) both laterally and on one of its flat sides. 34. Electronic component according to one of claims 27 to 33 characterized, that the top chip with a protective coating, the optionally also the lower chips is provided laterally covering.