DE10134981A1 - Large parallel multi-processor system has a modular design with individual modules linked to a central array logic chip so that system capability is used more efficiently and effective system power is increased - Google Patents

Abstract

Large parallel multi-processor system comprises a multiplicity of process modules (PM), where each module comprises a processor, logic chip and signal expander (SE). The signal expander is configured to transfer data from the processor to certain ports. The individual process modules are linked to a central array (CA) logic chip so that all the signals from the modules are input into the array.

Description

State of the art Single processor systems

Such a system consists at least of the modules processor, memory for Commands and data, and InOut system. These modules can consist of separate chips consist of or even just a microcontroller that already has all the modules on integrated the chip.

Command and data storage can be in the same logical storage area (from Neumann; one port to storage), or in different storage areas (Harvard; Command and data memories have separate ports to the memory), or there can be several give different, separate areas for commands and data (modified Harvard, for example in digital signal processor (DSP)), or there are different complexes Combinations from the above possible.

The processor processes the user and IO data in accordance with the stored commands. The processor can be of type SISD (Single Instruction Single Data) or SIMD (Single Instruction Multiple Data). SIMD machines have that The advantage of executing several identical commands during one instruction cycle can save program memory and thus be more efficient.

If several different, non-time-synchronous tasks are to be processed by one CPU must be normal using a multitasking-capable basic system software Interrupt driven, happen.

The term or part of the term processor is also intended for microprocessor, controller, Microcontroller, CPU, DSP, special processor or special module with independent sequentially working data transfer unit, and with the designation chip or the additional chip becomes a physical refers to the electrical component, the electrical connections used with the Conductor tracks of a carrier board are connected.

It should be noted that many processors, despite the high clock frequency, are very bad Have interrupt behavior, which means that they may have 10. .100 and more clock cycles until the jump into the interrupt service routine. In addition, in this Interrupt service routine still executed several register handling commands until the actual routine itself is processed.

Depending on the basic architecture of the software or the type of Operating system architecture can change this jump-in time in the worst case scenario take a few hundred to a few thousand CPU clocks. Should Multiple tasks can be processed by just one processor, which only have short runtimes The CPU overhead can have and should also be executed in real time may become too big. Under certain circumstances, the overhead alone could already be Multiples of the useful routine itself, which means that the CPU useful performance is very low would be low and only the CPU reactive power would be large. Including DMA transfers (DirectMemoryAccess) can change this very little.

If such real-time requests are executed with only one processor, apart from a very high clock frequency, there would also be extremely small overall context Switch times (a few ns) required, which cannot be achieved in this area. Thus, with such real-time requirements, a system implementation with only one is Processor no longer feasible and other solutions have to be found.

Multiprocessor systems

• 1. Die Prozessoren sind mittels eines, normalerweise asynchronen, Schnittstellenbausteins mit einer seriellen Busleitung verbunden. Dies ist unter anderem bei einem typischen Feldbusystem zu finden, wobei typische Buszugriffsverfahren wie Master-Slave oder Multi-Master verwendet werden.
  Eine oft benutzte Zugriffssteuerung bei Multi-Master ist CSMA/CD (Carrier Sense with Multiple Access and CollisionDetect) oder CSMA/CA (. . . and CollisionArbitration).
  Bedingt durch diese Zugriffssteuerungsverfahren ist der Bussystemdurchsatz zum Teil sehr klein und/oder die Signallaufzeiten der Busleitung fallen bei der Übertragung stark ins Gewicht.
  Dieses System wird innerhalb Anlagen, Räumen oder Gebäuden, eventuell auch geräteintern eingesetzt.
• 2. Ähnlich 1), jedoch mit zusätzlichen Busrepeatern, welche eine grössere Bus- Reichweite und -Ausdehnung erlauben, maximal einige Kilometer. Durch diese starke Verlängerung der Signallaufzeiten werden CollisionDetect (/CD) und/oder CollisionArbitration (/CA) allerdings schwerer zu handhaben, die entsprechenden Zeitabschnitte werden länger, und die Systemleistung nimmt weiter stark ab.
• 3. Wird das System 2) mit weiteren Repetern, Bridges, Routern usw erweitert, lässt sich die Bus-Reichweite und -Ausdehnung nochmals sehr stark erhöhen, wobei die entsprechenden technischen Probleme ebenfalls grösser werden.
  Das Internet, welches ja auch in gewisser Weise ein Multiprozessorsystem, allerdings extrem langsam, darstellt, gehört auch hierzu.
• 4. Wird beim Feldbussystem nach 1) die räumliche Ausdehnung verkleinert, lässt sich normal auch die Geschwindigkeit erhöhen und die Collisionslaufzeiten senken, da die Signallaufzeiten in etwa proportional zur Leitungslänge sind.
• 5. Prozessoren sind mittels integrierter serieller Schnittstelle, Beispiel SPI, IIC oder UART, verbunden. Dies wird oft innerhalb des Geräts oder der Leiterplatte eingesetzt.
• 6. Prozessoren sind mittels verschiedener integrierter Schnittstellen verbunden, wobei die Daten hauptsächlich über DMA übertragen werden.
  Zwar sind DMA-gesteuerte Daten-Transfers zwischen internen oder externen Peripherieelementen des Prozessors und des Speichers effizienter als der Daten-Transfer über CPU, aber während des DMA-Transfers sinkt die Rechenleistung des betreffenden Prozessors stark ab.
  So wird bei Hardware-DMA im CycleStealMode abwechselnd ein Takt für die CPU und für die DMA-Steuerung genutzt, womit die CPU während dieses Zustandes nur zur Hälfte arbeiten kann.
  Bei Hardware-DMA im ExclusivMode wird die CPU während des Betriebes der DMA-Steuerung complett angehalten und kann somit während dieser Zeit nicht auf den betreffenden Speicher zugreifen.
  Bei Software-DMA, das zwar mit weniger Siliciumfläche auf dem Chip realisierbar ist, werden aber auch bis zu circa 8. .12 CPU-Takte Overhead in Anspruch genommen und die Transfer-Ausführung ist langsamer als bei Hardware-DMA.
• 7. Als weitere System-Leistungssteigerung sind Parallelrechensysteme realisierbar, mit verschieden leistungsfähigen und verschieden aufwendigen Funktionselementen.
  • - Ein mögliches System besteht aus einer Vielzahl von Elementen mit Prozessor und SinglePortSpeicher. Zwischen Prozessor und Speicher befindet sich eine Speicherportschaltung, die mehrere Ports auf den Speicher bereitstellt. Zu einem Zeitpunkt kann immer nur ein Port aktiv sein und somit nur ein Prozessor auf den Speicher zugreifen. Ein Port der Speicherportschaltung ist mit dem zugehörigen Prozessor verbunden, während die anderen Ports mit anderen Prozessoren verbunden sind. Für jede Verbindung des Prozessors mit dem Speicher ist ein separater Port und somit zusätzliche Logikschaltungen und -Leitungen erforderlich. Da viele dieser Prozessoren gegenseitig mit diesen zusätzlichen Ports verbunden sind ist der Aufwand der zusätzlichen Hardware und auch der Aufwand für die Verbindungsleitungen sehr gross.
    Will ein Prozessor nun auf den Speicher eines anderen Prozessors zugreifen, muss der entsprechende Port zuerst vom momentan aktiven Prozessor freigegeben werden. Zu diesem Zweck löst der sendewillige Prozessor bei dem momentan aktiven Prozessor einen Interrupt aus. Dies verursacht natürlich einen grossen Systemoverhead, weil bis zur Einsprungroutine viele Prozessor-Taktzyklen vergehen. Ausserdem müssen alle Prozessoren, die auch auf diesen Speicher zugreifen wollen, abwarten, bis der momentan aktive Prozessor den Speicher wieder freigegeben hat.
    Durch Zufügen von, in der Grösse begrenzten, FIFO-Speicher (FirstInFirstOut) und/oder Multiport-Speicher zu der Speicherportschaltung kann die Interrupt-Belastung zwar etwas gesenkt werden und die Systemleistung erhöht werden, aber die Hardware- Kosten steigen ebenfalls stark an.
  • - Eine weitere Realisierungsmöglichkeit besteht darin, dass als Speicher nun Dual- oder Multiport-Speicher oder Dual- oder Multiport-FIFOs benutzt werden.
    Die Prozessoren können dann direkt an die vorhandenen Ports der Multiport-Bausteine angeschlossen werden. Dual- oder Multiport-Speicher oder -FIFOs haben jedoch relativ wenige Ports und sind in der Speicher-Grösse stark begrenzt und ausserdem sehr teuer.
  • - Weiter kann ein System dadurch bestehen, das die Prozessoren über ein ringförmiges Bussystem, das verschieden breit sein kann, miteinander verbunden sind. Dem geringeren Hardwareaufwand steht eine geringere Systemleistung gegenüber, weil der Bus wesentlich langsamer ist und hier auch nur ein Prozessor gleichzeitig zugreifen kann.
    Auch wenn statt einem Bus mehrere Busse parallel benutzt werden, steigt zwar die Systemleistung an, aber die grundsätzlichen Nachteile sind noch immer vorhanden.

Different implementation options for a multiprocessor system are:

• 1. The processors are connected to a serial bus line by means of a, usually asynchronous, interface module. This can be found, among other things, in a typical fieldbus system, using typical bus access methods such as master-slave or multi-master.
  An often used access control with Multi-Master is CSMA / CD (Carrier Sense with Multiple Access and CollisionDetect) or CSMA / CA (... And CollisionArbitration).
  As a result of these access control methods, the bus system throughput is sometimes very small and / or the signal propagation times of the bus line are significant during the transmission.
  This system is used within systems, rooms or buildings, possibly also within the device.
• 2. Similar to 1), but with additional bus repeaters, which allow a larger bus range and extension, a maximum of a few kilometers. This strong increase in the signal propagation times makes CollisionDetect (/ CD) and / or CollisionArbitration (/ CA) more difficult to handle, the corresponding time periods become longer and the system performance continues to decrease significantly.
• 3. If the system 2) is expanded with additional repeaters, bridges, routers, etc., the bus range and extension can be increased again very greatly, with the corresponding technical problems also becoming greater.
  The Internet, which in a way represents a multiprocessor system, albeit extremely slow, is also part of this.
• 4. If the spatial expansion is reduced in the fieldbus system according to 1), the speed can normally also be increased and the collision transit times reduced, since the signal transit times are roughly proportional to the cable length.
• 5. Processors are connected by means of an integrated serial interface, for example SPI, IIC or UART. This is often used inside the device or circuit board.
• 6. Processors are connected by means of various integrated interfaces, the data being mainly transmitted via DMA.
  Although DMA-controlled data transfers between internal or external peripheral elements of the processor and the memory are more efficient than data transfer via the CPU, the computing power of the processor concerned drops significantly during the DMA transfer.
  In hardware DMA in CycleStealMode, a clock is alternately used for the CPU and for the DMA control, with which the CPU can only work halfway during this state.
  With hardware DMA in exclusive mode, the CPU is stopped completely during operation of the DMA controller and therefore cannot access the relevant memory during this time.
  With software DMA, which can be implemented with less silicon area on the chip, up to approximately 8-12 CPU clock cycles are used and the transfer execution is slower than with hardware DMA.
• 7. As a further system performance increase, parallel computing systems can be implemented with differently powerful and differently complex functional elements.
  • - A possible system consists of a multitude of elements with processor and single port memory. There is a memory port circuit between processor and memory, which provides several ports to the memory. Only one port can be active at a time and therefore only one processor can access the memory. One port of the memory port circuit is connected to the associated processor, while the other ports are connected to other processors. A separate port and therefore additional logic circuits and lines are required for each connection of the processor to the memory. Since many of these processors are mutually connected to these additional ports, the additional hardware and the connection lines are very expensive.
    If a processor now wants to access the memory of another processor, the corresponding port must first be released by the currently active processor. For this purpose, the processor willing to send triggers an interrupt on the currently active processor. This naturally causes a large system overhead because many processor clock cycles pass before the jump-in routine. In addition, all processors that also want to access this memory must wait until the currently active processor has released the memory again.
    By adding FIFO memory (FirstInFirstOut) and / or multiport memory to the memory port circuit, which is limited in size, the interrupt load can be reduced somewhat and the system performance increased, but the hardware costs also rise sharply.
  • - Another possible implementation is that dual or multiport memories or dual or multiport FIFOs are now used as the memory.
    The processors can then be connected directly to the existing ports of the multiport modules. However, dual or multi-port memories or FIFOs have relatively few ports and are very limited in terms of memory size and are also very expensive.
  • - Furthermore, a system can consist in that the processors are connected to one another via a ring-shaped bus system, which can be of different widths. The lower hardware expenditure is offset by lower system performance because the bus is much slower and only one processor can access it at the same time.
    Even if several buses are used in parallel instead of one bus, the system performance increases, but the basic disadvantages are still present.

Problems and disadvantages of previous systems

• - If processors are connected to each other via a common bus, the Only one processor on the bus at a time and thus on the memory access while all other processors have to wait for access. are For example, 20 processors included in the system, so with more even Time allocation, a processor can use a maximum of only 1/20 of the gross bus bandwidth.
• - Should the communication between the processors via separate logic and separate Connections are made
• - there is either a limited communication performance due to missing component and wiring resources, or
• - The costs for component and wiring are very high.

With previous systems, there are always processors that are currently not - or only can communicate with other processors with limited performance because of the Connection bus, or the connection lines of others at the moment Processors are occupied, be it by bus occupancy, interrupt overhead or general CPU overhead.

The previously known multiprocessor systems all have the disadvantage in relation to Architecture too rigid and inflexible and therefore not very efficient.

abstraction

Combining all technical possibilities, one can say that basically any multiprocessor topology or architecture technically can enable any processor to be global or local Reads or describes memory data from another processor, or that any processor communicates with any other processor. This applies to all topologies, regardless of whether the bus system is global The extent of one kilometer is within a building Has an extent of a few meters, whether it is inside the device, whether it is within a Circuit board or whether it is inside a chip, no matter whether the connections of the processors to each other, with a line Bus line, with a ring system, with chain-shaped connecting lines, or with separate lines for each processor to special memory modules are.

And this communication is possible through appropriate, more or less complex hardware circuitry or by appropriate software, some of which the data is transferred accordingly at the lower machine level, or a combination from hardware interconnection and special software.

A communication ^performance comparison of different possible systems can be up to 1: 10 ^{6. .9} or more.

The key question with all these multiprocessor systems is:
How powerful are the systems, how intelligent and how fast can the communication between the processors be realized, and how complex is the system to implement.

The new multi-processor architecture

• - beseitigt die, bei bisher bekannten Systemen, vorhandenen Nachteile, Probleme und Einschränkungen
• - stellt eine völlig neue Systemarchitektur mit vielen Vorteilen dar und
• - eröffnet eine völlig neue Dimension von Möglichkeiten und völlig neue Gesichtspunkte der Multi-Prozessor-Kommunikation.

The inventive multi-processor architecture presented here

• - eliminates the disadvantages, problems and restrictions that exist with previously known systems
• - represents a completely new system architecture with many advantages and
• - opens up a completely new dimension of possibilities and completely new aspects of multi-processor communication.

A system architecture with many, individual processors is all the better and more powerful, the more freely available logic switching elements respectively Logic gates are available for coupling, and the closer and closer they are Logic switching elements are arranged. Many logic switching elements because of that the possible complexity of transfers among one another increases and because of this, many Functions can be done in parallel, dense arrangement, because this creates the Logic speed is high.

These properties are, for example, in a programmable logic device Given FPGA / CPLD, the individual logic functions via programmable Bits can be freely interconnected and created, so to speak.

For high system performance, it is therefore ideal if all processors of all relevant Processor control signals (address, data, control) in a centrally arranged, complex, possibly programmable, logic module.

This centrally arranged logic module is called Centralarray (CA). It communication could also be established with fewer processor pins, this but would be much less efficient.

Now all relevant processor control signals from all the processors involved and the associated processor control lines (Adr, Data, Control, special port pins and possibly interrupt pins) flow together in the central array, this is the possible one Number of processors severely limited because of the logic chip in which the Centralarray is implemented, has a limited number of pins, and even if that Central array consists of several chips, is the available number of pins limited.

So the key question is how to get everyone relevant to communication Processor control signals can result in the central array, but without the high Need number of pins.

In order to accomplish this task, an additional logic chip will be given below Called signal expander (SE), each connected between processor and central array, the processor pins leading to the signal expander and different lines of the Lead signal expanders to the central array, and signal expanders and central array are equipped with special logic functions for communication.

These logic functions in the signal expander and central array are such that various signals transmitted by the processor or individual parts or all parts of the Memory and InOut protocol of the processor into several small command, address and Data packets are broken down and then transferred to the central array. To the For example, individual protocol components of the Processor are stored in the signal expander and immediately afterwards as small, fast command, address and data packets are sent to the central array. This individual command, address and data packets with communication package or Comm packet are then reconstructed in the central array, whereby the complete, original information is now available in the central array Available.

When designing the system, the bit width of the comm packets is one of them the number of lines of the main connection from signal expander to central array free selectable, of course with the same bit transmission frequency and increasing Comm packet bit width or number of lines the amount of data transferred each Unit of time becomes larger.

As an example, the information of a write command from the processor where 28 address and 32 data bits for a processor clock are active in the signal expander be saved, and with the beginning of the validity of the write command of the processor (e.g. / WR signal = low) a comm packet with the content of the write command to Centralarray are transmitted and then the addresses and data with 4 × 16Bit-, 8 × 8-bit, 16 × 4-bit or 32 × 2-bit comm packets or with other comm packet packets Bit widths are transmitted. In the event that the signal expander is 8 × 8 bits Comm packets sent to the central array are at least 8, typically around 10 Cables from the signal expander to the central array are required, although with a direct connection from the processor to the module, however, about 60 lines would be necessary. This matches with Factor 6, which means 6 times as many processors to the central array in this case can be connected than would otherwise be possible.

The register sets described here, consisting of logic switching elements, have Control connections, with which, among other things, the storage of bits or bit groups in the register set and outputting stored bits or bit groups from the Register set is possible and the term logic switching elements stands for any one Combination of any complex transceivers, gates, registers, flip-flops, Latches or similar logic gates.

So that the communication and signal flow between processor, signal expander and Centralarray can take place, these chips are connected accordingly.

This is how the processor connections with a connection group are called Processor connection port, connected to the signal expander. Further from Signal expander using the connectors called central array connector port Signal expander connection port named, Connections of the central array connected. Chip internally are directly connected to each other in the signal expander: the Processor connector port with the processor register set and the Central array connector port with the central array register set. And are in the central array the signal expander connector port is connected to the signal expander register set.

The logic functions of signal expanders and of the logic part in the central array, the over the corresponding signal expander register set with the signal expander is connected so that the relevant one, in the respective chip contained registers or register sets the relevant data and Can exchange information bits with each other, within the chip. For this the corresponding connection structures exist in the chip.

So that this data exchange between the register sets can take place, the individual control connections of the relevant register sets and thus the relevant Logic switching elements with the outputs of a state machine, typically with different registers is connected. This state machine is in hereinafter referred to as state machine.

The command-triggering control bits or flags in the corresponding register sets lead to the inputs of the state machine, which then react accordingly can.

Because the state machine with the individual, sequential signals Control connections of the register sets, it is possible that the register sets targeted individual information and address or data bits from the register sets connect the connected connecting cables. Thus, by means of the State machine, the register sets and the corresponding connections with each other, the desired information bits are exchanged with each other.

The state machine of signal expanders and of the logic part in the central array, the over the corresponding signal expander register set with the signal expander internally can be such that all individual states are synchronized binary counters controlled by the clock signal. The smallest Time unit for a state and the smallest possible command or control state corresponds to the period of the clock signal, which is normally always the same length, or half the period for two-edge evaluation.

Control of the individual register sets with this synchronous binary counter is possible, a combinatorial decoding network can be connected downstream of the meter that certain outputs are activated depending on the specific input counter reading.

These individual outputs of the decoding network are also the outputs of the State machine and these then lead to the individual control connections on the relevant register sets. Depending on the determined meter reading, individual, certain state machine outputs are activated.

The control connections on the respective register set can, for example, be one Control multiplexer or demultiplexer on the register set, the individual bits or Bit groups addressed, and these bits to the input or output or the input or output group of the register set switches. Thus, among other things, is a transfer of certain bits or bit groups, mainly the comm packets between different register sets possible.

Each individual binary state of the synchronous binary counter can be separate command or signal to control the register sets interpreted become. It is also possible to use more significant bits of the counter than groups Interpret command groups.

A concrete division with a 14-bit synchronous binary counter can look like this:

• - interne Befehlspakete darstellen, wie beispielsweise Write-Befehl mit nachfolgend 16 Adr/Daten-Paketen, Write-Befehl mit nachfolgend 8 Adr/Daten-Paketen oder Read- Befehl mit nachfolgend 10 Adr/Datenpakete, oder
• - Adress- und Datenpakete darstellen.

The top bit (B13) marks whether the state machine is active. If it is active, the next bit (B12) indicates whether the transfer relates to program or data memory. If it refers to data storage, the next bit (B11) marks the action Write or Read. Bit (B10) marks whether the comm packets sent from the signal expander to the central array

• - Represent internal command packets, such as a write command followed by 16 addr / data packets, a write command followed by 8 addr / data packets or a read command followed by 10 addr / data packets, or
• - Show address and data packets.

The next 6 bits (B9 ... 4) stand for the number of the currently transmitted Comm packet, with which these 6 bits transmit a maximum of 64 comm packets can be, which are command packets or Adr / data packets can. However, very few of the command packages become one required, which is why the upper bits of these 6 bits have no meaning in this case.

The 4 lowest bits (B3.. .0) indicate the current status of the individual Control lines of the individual register sets within the respective individual Come package. This means that a maximum of 16 individual logic and register states are each Comm packet possible, whereby these individual states cause among other things that individual control connections of the relevant register set are switched.

Specific functional example for - data writing - with 26 Adr bits and 32 data bits, with a comm packet bit width of 4 bits

The processor places the address and data bits on the processor connection port of the Signal expander on, and with the processor's active WR signal, the Addresses and data are stored in the processor register set of the signal expander. At the same time, the WR flag is activated in the processor register set.

This active WR flag causes the state machine in the signal expander in the write To go into command mode.

In this mode, the state machine first causes the central array register set stores a certain bit pattern and then this to the central array connection port is transmitted.

This bit pattern sent from the signal expander to the central array is used by the Central array recognized and interpreted as a write command, after which the state machine of the Centralarrays goes into receive mode.

From the next cycle, the state machine of the signal expander causes the im Processor register set contain addresses and data as separate comm packets for Centralarray will be sent. These are first 7 address packets and then 8 data Packets, these comm packets are each 4 bits wide. The last 2 bits of the last Adr packets have no meaning because there are only 26 AdrBits.

Because the state machine in the central array is already in the correct mode the incoming comm packets can now be in the correct form interpret and in the correct order in the corresponding register in the Transfer the central array.

If all comm packets have been transmitted, the WR flag is deactivated again State machines from Signalsxpander and Centralarray go back to inactive Mode, and are ready to receive new commands again. The transmission end The comm machine can recognize the comm packets because the number of to transmitting comm packets is fixed as soon as the WR command from the central array Will be received.

Specific function example for - reading data - with 26 Adr bits and 32 data bits, with a comm packet bit width of 4 bits

The processor applies the address bits to the processor connector port of the signal expander, and with the active RD signal of the processor, the addresses and data in the Processor register set of the signal expander saved. At the same time Processor register set the RD flag activated.

This active RD flag causes the state machine in the signal expander in the read To go into command mode.

In this mode, the state machine first causes the central array register set stores a certain bit pattern and then this to the central array connection port is transmitted.

This bit pattern sent from the signal expander to the central array is used by the Central array recognized and interpreted as a read command, after which the state machine of the Centralarrays goes into output mode.

From the next cycle, the state machine of the signal expander causes the im Processor register set contain addresses as separate comm packets to the central array be sent. These are 7 address packets, these comm packets each 4 bits are wide. The last 2 bits of the last Adr packet have no meaning because only 26 AdrBits are present.

Because the state machine in the central array is already in the correct mode the incoming comm packets can now be in the correct form interpret and in the correct order in the corresponding register in the Transfer the central array, with which the address is then in the corresponding register. When all address packets have been transferred, the state machine of the central array increases the data belonging to the address and transmits them, also in comm packets, to the Signal expander.

The signal expander's state machine, in turn, has the addresses after it has switched accordingly and now reads those from the central array transmitted comm packets, which represent data, and transmits this to Data register of the processor register set of the signal expander.

Once all comm packets have been transmitted, the RD flag is deactivated again State machines from Signalsxpander and Centralarray go back to inactive Mode, and are ready to receive new commands again. The transmission end The comm machine can recognize the comm packets because the number of to transmitting comm packets is fixed as soon as the RD command from the central array Will be received.

The data now contained in the processor register set of the signal expander can be from Processor can be read out.

Reading the program data from the central array works in an analog way, like reading the data.

Due to the variable comm packet bit width for different signal expanders, the entire central array bandwidth can be used and it can Bandwidth can be divided variably between the individual process modules.

• - es sind keine speziellen Transfer-Befehle des Prozessors nötig
• - es müssen auch keine zusätzlichen Wartezyklen ausgeführt werden
• - die Prozessoren sind bezüglich der Kommunikation permanent mit dem Centralarray verbunden, womit die completten Adressen und Daten permanent, automatisch, ohne irgendwelche zusätzlichen Programmassnahmen übertragen werden.

The integration of the signal expander between each individual processor and central array thus enables a very large number of processors to be coupled to the central array very efficiently, because

• - No special transfer commands from the processor are required
• - No additional waiting cycles have to be carried out
• - The processors are permanently connected to the central array for communication, so that the complete addresses and data are permanently, automatically, transferred without any additional program measures.

Due to the very easy integration of any processor or microcontroller, by means of Signal expander, in this system, can be the best and for the respective task most effective microcontroller or processor can be used.

This means that the system can be scaled very well, while at the same time maximizing Utilization of the processors and controllers used.

This type of system performance increase does not only increase the software functionality expanded, but due to the increasing parallelism of the hardware with others Scaling, runtime requirements are those running on other processors Routines are not impaired, and so the overall calculated Total system interrupt latency and total context switch time, with increasing Hardware scaling is getting shorter and shorter.

Implemented into the central array with the one described in detail below MultiPort memory machine, which due to its special, completely new architecture, as a variable, scalable in port size and number, completely asynchronously operable, readable and writable MultiPort memory is functional, there are more significant benefits that open up a whole new dimension of possibilities and open aspects of multi-processor communication.

• - Es kann jeder beliebige Prozessor, ohne Zufügen von dedizierter Hardware, für jeden anderen beliebigen Prozessor als hardwaremässig direkt - breitbandig angekoppelter Co-Prozessor dienen. Dies ist sehr bemerkenswert, weil hierfür normalerweise dedizierte Hardware, für jeden betreffenden Prozessor separat, erforderlich ist. Weiterhin gilt bei diesem neuen System, dass
• - jeglicher CPU-Overhead, wie Overhead für Interrupt, Wartezyklen oder sonstiges, der normal bei der Kommunikation entsteht, entfällt
• - in den typischen Fällen der explizite Datentransfer sogar überhaupt nicht erforderlich ist, weil es möglich ist, dass der Prozessor während seiner eigentlichen Bearbeitungsroutine (nicht Datentransferroutine) die Daten automatisch direkt in den entsprechenden Speicherbereich schreibt, und dieser Speicherbereich von den anderen Prozessoren ebenfalls zugänglich ist. Dadurch dass das Prozessor-spezifische Busprotokoll in dem Signalexpander äquivalent umgesetzt wird und in das Centralarray übertragen wird, existiert hinsichtlich der konkreten Assembler- und Maschinenbefehle und auch der dafür erforderlichen CPU-Takte, überhaupt kein Unterschied zwischen physikalischem Speicher nahe der CPU oder externem Speicher. Der physikalisch externe Speicher ist somit ohne irgendwelche Einschränkungen voll in den internen Speicherbereich eingebaut.
• - Der Prozessor kann während seiner eigentlichen Bearbeitungsroutine (nicht Datentransferroutine) die Daten automatisch direkt in den entsprechenden Speicherbereich schreiben, wobei dieser Speicherbereich von den anderen Prozessoren ebenfalls zugänglich ist.
  Das besondere daran ist, dass jeder Prozessor für sich selbst, mit seinem logisch internen Datenspeicher, sein Programm ausführt, und diese Daten automatisch, ohne eine speziell ausgeführte Datentransferroutine, allen anderen Prozessoren zur Verfügung steht. Die Prozessoren brauchen also alle für sich nur ihre eigenen internen Bearbeitungsroutinen auszuführen, und sind über dieses Massiv-parallel-gekoppelte- Multiprozessorsystem so miteinander verkoppelt, dass jeder Prozessor ohne irgendwelche Sonderroutinen automatisch auch auf den Speicher jedes anderen Prozessors zugreifen kann.
  Man könnte sagen, dem einzelnen Prozessor steht das ganze Wissen des gesamten MultiSystems für seine eigenen lokalen Bearbeitungsroutinen zur Verfügung und er kann dazu beitragen, dieses gesamte Wissen zu erweitern ohne spezielle Datentransfers durchführen zu müssen.

The following advantages, among others, apply to the processors which are integrated into the system by means of the massively parallel-coupled multiprocessor system described here:

• - Any processor, without adding dedicated hardware, can serve as a hardware-direct, broadband coupled co-processor for any other processor. This is very remarkable because it usually requires dedicated hardware, for each processor in question. Furthermore, with this new system it applies that
• - Any CPU overhead, such as overhead for interrupt, wait cycles or anything else that normally arises during communication, is eliminated
• - In the typical cases, explicit data transfer is not even necessary at all, because it is possible that the processor automatically writes the data directly into the corresponding memory area during its actual processing routine (not data transfer routine), and this memory area is also accessible by the other processors , Due to the fact that the processor-specific bus protocol is implemented in the signal expander and transferred to the central array, there is no difference whatsoever between physical memory near the CPU or external memory with regard to the specific assembler and machine instructions and also the CPU clocks required for this. The physical external memory is thus fully integrated into the internal memory area without any restrictions.
• The processor can automatically write the data directly into the corresponding memory area during its actual processing routine (not the data transfer routine), this memory area also being accessible by the other processors.
  The special thing about it is that each processor executes its program for itself with its logically internal data memory, and this data is automatically available to all other processors without a specially executed data transfer routine. The processors therefore all need to carry out their own internal processing routines for themselves and are coupled to one another via this massively parallel-coupled multiprocessor system in such a way that each processor can automatically access the memory of any other processor without any special routines.
  You could say that the individual processor has all the knowledge of the entire MultiSystem available for its own local processing routines and it can help to expand this entire knowledge without having to carry out special data transfers.

The fact that the program data can also be made accessible to the central array in the same way results in yet another significant advantage:
For example, special data and values that a processor in the system calculates with its internal processing routine can be used directly by another processor as program memory without separate data transmission. This program could be a critical, very fast procedure in the us or ns range, the properties of which depend on various external factors that are accessible to the MultiSystem.

This set of aspects and points of view of this massively parallel coupled In principle, multiprocessor systems open up new approaches and completely new ones Dimensions of communication possibilities and capabilities of Multiprocessor systems.

Explanation of the individual protection claims

Protection claim 1 explains the core components and core elements of the Multiprocessor system.

Protection claims 2 to 5 explain different circuit, functional and Logic details of the system.

Protection claim 6 confirms the advantage that the processor-specific memory and InOut bus protocol of the processor used in the process module, in an equivalent Bus protocol can be converted, and its signals to the central array can be passed on.

Because this converted bus protocol, with unchanged meaning, less Lines required than the bus protocol of the processor are correspondingly fewer Pins needed for the central array. This way you can do a lot more Processors are connected, as it would be different. So that's it possible, with the pin count possibly greatly reduced, the full functionality of the individual processor-specific memory and InOut bus protocols of the individual Transfer processors to the central array. Since all these signals are now in the Central array are present is a very high performance of the multiprocessor system possible.

Protection claim 7 extends the system in that in the signal expander Evaluation circuit is available, which reports to the outside via pins whether the Signal expander internal state machine is free or is still busy. This can the connected processor may detect whether the data is still from the State machine are processed or whether the signal expander accept further data can.

Protection claim 8 explains that an additional logic circuit in the signal expander can provide the clock signal for the connected processor. This can be obtained from the logic clock in the signal expander, for example. Is the state machine in the signal expander over a certain period of time busy, the logic circuit can stop the clock signal to the processor clean, which means that there are no disruptive edges and all parts of the clock signal in the specified range.

Protection claim 9 shows the advantage that an address comparator and in the signal expander Evaluation logic for the addresses transmitted by the processor is implemented. This Evaluation logic enables that instead of the concrete addresses only short ones Address commands with a few bits, such as address autoincrement, Address auto decrement, or address equality, are transferred to the central array. This may mean that the number of transferred to the central array Decrease comm packets because the transfer of the complete address bits is not is required and instead a special comm packet, which is a special one Command is sent. For example, does the processor access a 32 bit Address that is only one higher than the last address, the Signal expander can send the address autoincrement command to the central array, and can thus do not send the 32 address bits, which may be quite a bit Saves time. A corresponding circuit in the central array then calculates from this short address command the exact address.

Protection claim 10 shows the advantage that an address comparator in the signal expander and evaluation logic is implemented for the addresses transmitted by the processor. This evaluation logic enables that instead of the concrete addresses to be expanded Address commands can be transferred to the central array with just a few bits. This Extended address commands can, for example, cause predefined Addresses and memory pages can be jumped to in a memory area. This may mean that the number of transferred to the central array Decrease comm packets because the transfer of the complete address bits is not is required and instead a special comm packet, which is a special one Command is sent. For example, does the processor access one beforehand specified memory area, the signal expander can use the corresponding Send command to the central array, and can thus send the 32 address bits do without, which may save a lot of time. A corresponding circuit in the central array then the corresponding resulting value takes from a, in Hardware stored, table and stores it in the corresponding register.

Protection claim 11 extends the signal expander chip in that the free logic resources and free pins of the signal expander chip are used for this , by means of additionally implemented registers and additional inclusion of Pins, the existing direct InOut port signals and pins of the connected Processor. Are there still some macro cells in the signal expander and some pins are empty, these pins can be used as additional separate ones Input pins are used that can be read by the connected processor. For example, there are more separate input pins than one Microcontrollers alone would be available.

The extension made in protection claim 12 means that several narrow interconnected logic chip chips can represent a central array, and Lines to the signal expander can also be connected in parallel to several chips in the central array being able to lead. Because the individual chips work as a whole as a central array it is particularly important that these chips have the highest possible bandwidth and are thus connected with each other with the shortest possible lines in order to fast, optimal interaction of the individual chips belonging to the central array to ensure. The individual logic functions in the individual chips are like this procure that, in their entirety, they form a large, complex central array. This larger number of chips gives the central array a higher number Efficiency and flexibility, and also a larger number of pins. Because of something limiting connection channel between the chips is an extension of one Recommended on several chips only if the complexity or the number of pins of one individual chips can no longer be increased.

The extension made in protection claim 13 means that several are also narrow interconnected logic chip chips can represent a signal expander, and lines to the central array also to several chips of the signal expander in parallel being able to lead. Because the individual chips in their entirety like a signal expander It is important that these chips work with the highest possible bandwidth and are thus connected with each other with the shortest possible lines in order to optimal interaction of the individual chips belonging to the signal expander guarantee. The individual logic functions in the individual chips are like this procure that, in their entirety, they are a large, complex signal expander form. This larger number of chips means higher performance and Flexibility, and also a larger number of pins, given the signal expander.

The extension made in protection claim 14 means that several Signal expander, and thus several process modules, in parallel on one or more Connection lines to the central array can be connected. Depending on the moment It is the active signal expander mode, which can be switched from the outside then a certain signal expander possible, these lines additionally for the Use data transfer with. Thus the bit width of the comm packets for the relevant signal expanders are enlarged and the transfer is accelerated. At the same time, process modules that currently do not have such a high data throughput need only one or a few lines or pins on the central array occupied.

The mode switch of the signal expanders can be done very quickly, in the ns range, , which means that the mode may be several million times per second can be switched, and so an optimal use of the connecting lines is made possible.

Protection claim 15 characterizes a system expansion in the form that one or a few additional lines from the central array to the signal expanders go, the logic circuits implemented in central array and signal expanders cause these extra lines, commands and special messages can be transferred from the central array to the signal expander. Thus, over another information channel, regardless of the main connection channel Signal expander to central array, additional information and possibly Status messages are transmitted. Because this additional information channel is normal consists of only one or a few lines, the maximum that can be transmitted over it Data rate is of course much lower than the data rate for the main connection channel. However, this data rate is completely sufficient for this category of information.

If necessary, the data transmitted by the central array can be used with suitable data Funds are passed to the processor.

In protection claim 16 there is an extension such that the signal expander consists of several chips and different chips thereof Standard shift register blocks, typically TTL blocks, are. The control of this Shift registers are taken over by separate logic circuits which are used by the Processor signals are controlled. Thus, under certain circumstances, too Inexpensive standard TTL modules can be used if the specific system and the specific protocol division allows this.

Protection claim 17 extends protection claim 16 in the form that the logic circuits for controlling the shift registers for several signal expanders in are combined on a chip. This allows the shift register control may make it more efficient.

Protection claim 18 explains the circuit function, which enables that already Time of the active ALE signal of the processor the data to be read from Centralarray be transmitted to the signal expander and this data only in the case of RD signal generated by the processor are transmitted to the processor. To this In this way, the system may be more efficient because the connecting lines from the Signal expanders to the central array can be better used. The data is, so to speak transmitted to the signal expander under advance assumption, but only to the processor transferred if desired.

The advantage of protection claim 19 is that the signals from three control lines of the Processor are combined in a signal line, and this to the central array be transmitted.

Protection claim 20 substantiates protection claim 19 in that the type and Way of signal sampling is described.

In protection claim 21, the importance of different registers, and the type of Interconnection of the individual registers in the central array explained.

In protection claim 22, the type of interconnection of the individual memory blocks in Centralarray explains.

Protection claim 23 explains that the interconnection of the registers, or the memory blocks is designed so that certain register or Storage areas with access rights and access priorities regarding the various signal expander connection ports can be equipped.

This makes it possible to separate certain memory areas or parts of certain ones Protect process modules, or data transfer only in one allow desired direction.

Protection claim 24 explains the core components and core elements of the in Centralarray implemented system, the following with MultiPort memory machine is called.

With this logic module is the number of ports and thus the number of possible external processors that can access the memory, variable and scalable, the bit width of the individual ports is also variable.

Cost-effective standard memories can be used as the memory, or the Memory can also be in the same chip as the system or like that Central array.

This system represents a completely new storage architecture and therefore new, very powerful systems can be created.

The term external processor is used for such a processor or module used that on the central memory of the MultiPort memory machine accesses, whereby the external processor is outside the MultiPort memory machine, but is inside or outside the Central array chips can be located.

The new architecture is characterized by the fact that sequential logic control, in the form of a state machine constructed with logic switching elements, in the following Called ramming machine, is present, and this ramming machine is continuous sequentially to a variety of port registers connected to connection ports accesses, and the addresses and data available in the corresponding port registers with the memory, hereinafter referred to as central memory, with which the system Functional as a variable, multi-port memory, scalable in port size and number is.

The individual external processors are connected to the individual connection ports MultiPort memory machine connected, with which the data write or data Read jobs from the external processors are stored in the port register records.

The pile driver scans the individual port register sets one after the other if necessary, transfers the corresponding addresses and data between Central memory and the respective port register set.

In this way, the system of the MultiPort memory machine behaves as a variable, Multi-port memory scalable in port size and number.

It can read to the central memory or via each individual connection port write access, and access via a connection port is complete independent and asynchronous from the access of the other connection ports.

The logic functions of the multi-port memory machine are designed so that the relevant registers or register sets contained in the respective chip the relevant data and information bits among themselves, within the chip, can exchange. The corresponding connection structures exist in the chip.

So that this data exchange between the register sets can take place, the individual control connections of the relevant register sets and thus the relevant Logic switching elements with the outputs of the pile driving machine, which are typical with different registers is connected.

The command-triggering or command-influencing control bits or flags in the corresponding register sets lead to the inputs of the pile driver, which can then react accordingly.

The fact that the pile driver with the individual, sequential signals Control connections of the register sets, it is possible that the register sets targeted individual information and address or data bits from the register sets connect the connected connecting cables. Thus, by means of the Piling machine, the register sets and the corresponding connections the desired information bits are interchanged with each other.

The piling machine, typically in the form of a built with registers State machines can be implemented internally so that all of them States represented by a synchronous binary counter controlled by the clock signal become. The smallest unit of time for a state and a smallest possible command corresponds to the period of the clock signal, which is normally always the same length, or half the period for two-edge evaluation.

So that this synchronous binary counter controls the individual Logic circuits, registers and transceivers is possible, the counter can combinatorial decoding network, so depending on certain counter reading the corresponding control lines of the transceivers, Logic circuits and registers can be activated accordingly. Each individual binary state of the synchronous binary counter can be separate command can be interpreted. It is also possible to make groups more significant Interpret bits of the counter as command groups.

A possible division and coding of the state of the synchronous binary counter would be that the most significant part of the counter (MSB) is the currently selected one Port register set represents, and the least significant part of the counter (LSB) the respective switching state of the individual logic circuits, transceivers and registers represents what as a specific control command within the selected Port register set can be seen.

A 12-bit synchronous binary counter can serve as an example.

The 5 MSB bits represent the selected port register set, with a maximum of 32 Port register sets and thus 32 connection ports can be operated.

The 7 LSB bits represent the individual commands within a port register set, with which 128 separate commands are available within a port register set. The top bit (B6) differentiates whether the currently selected port is active or is inactive. If it is active, the next bit (B5) differentiates between write (WR) and read (RD) request. The lowest 5 bits (B4. .B0) are used in conjunction with a decoding logic for controlling the individual control lines of the individual Logic circuits, transceivers and registers.

Now the scanning of the port register records is done with a fixed, deterministic Time division and if 32 port register sets are implemented in the system, the Run through the synchronous binary counter from zero to complete, and again at the maximum start from zero (turnaround).

Protection claim 25 includes the extension that the connected processor Can read out the control bit in order to be able to currently write to the port prevent if the pile driver does not yet have the previously entered data processed.

Protection claim 26 includes the extension that the connected processor Can read the control bit in order to possibly wait to read from the port, if the pile driver has not yet transferred the requested data to the port.

In protection claim 27 there is an extension that allows the Processor instead of wide addresses only short addresses with a few bits, transmitted, which are interpreted as short address commands. Thus, for example, with the Command autoincrement or autodecrement a wide address increases or decreases without the complete address being transmitted, whereby Transmission bandwidth can be saved. You can also use commands for autoincrement or decrement generated with an address spacing greater than one become. If such a short address command is recognized, be it by the detection a certain address range or by detecting one from the processor additionally transmitted bits, the corresponding resulting value is determined using Hardware calculated and stored in the address register of the port register set.

This enables, for example, a 32 bit with an address width of only 8 bits Change address in a targeted manner. Due to the direct implementation in hardware no additional clock required.

In protection claim 28 there is an extension that allows the processor instead of broad addresses, only short addresses are transmitted, which are extended Address commands can be interpreted. These extended address commands can be used for Example cause predefined addresses and memory pages in one Memory area can be jumped to.

If such an extended address command is recognized, be it by detecting one certain address range or by detecting an additional by the processor transmitted bits, the corresponding resulting value from a, in hardware stored, table taken and in the address register of the port register set stored. This makes it possible, for example, with an address width of only 8 bits jump to different targeted memory pages in the 32-bit address range. Through the direct implementation in hardware, no additional clock is required.

In the protection claims 29 to 33 different variants of scanning the Port register sets out, which have certain advantages depending on the application. The The piling machine is created depending on the scanning variant. All Decisions to be made regarding the scanning process, and all calculations for this are done directly in hardware by the pile driver executed, with no additional clock loss for more complex scanning processes and so the entire time available exclusively for data transfer is usable.

In the variant in protection claim 29, the scanning of the port register records takes place with fixed, deterministic timing. Thus, for each port register set timeslot of the same length used, it is irrelevant whether at the moment scanned port register set a transfer from or to the central memory has to be or not.

This ensures that there is no longer time when transferring all port register sets is required than when transferring only a few port register sets or only one Port register set, which ensures that the worst case conditions always be fulfilled.

In the variant in protection claim 30, the scanning takes place in that the Ramming machine jumps directly to the next port register record, if at the current one Port register set no transfer is necessary.

This means that the time saved is available for the transfer of other ports and that System may work with higher throughput.

Variant according to protection claim 31 is characterized in that the order which can change port register record scans using control signals. The necessary for this Control connections lead to the inputs of the pile driver.

This extension enables different scan patterns and Sequences are executed, and thus the system can run better and more efficiently the different applications are set.

Variant according to protection claim 32 has the advantage that during a complete Runs through port register set scans one or more port register sets be scanned once. These ports have a correspondingly higher one Data throughput possible than would have been possible with previous scan modes. Consequently can also serve the otherwise critical ports sufficiently quickly become.

Variant according to protection claim 33 has the advantage that the data transfers for DataRead or DataWrite are executed immediately one after the other can. Only data read commands or follow in a time period data write commands only. This may result in the Transfer speed between the central memory and the individual Port register records, possibly through special pipeline stages, can be increased.

Variant according to protection claim 34 extends the system with the possibility that a certain status of the pile driver can be triggered by a port register set can. Thus, the pile driver can access a specific one Port register set preset and thus synchronized. So it is possible access by a processor to the port register sets, the internal scan Automatically control operations of the pile driver.

Protection claim 35 denotes the extension, that in the central array several MultiPort memory machines can be implemented.

Protection claim 36 explains logic function that the different Signal expander register sets with other logic parts or with port register sets of the MultiPort storage machine connects within the central array.

This is a continuous signal and data flow from signal expander connection port to the central memory of the MultiPort memory machine.

Protection claim 37 describes the way program data from the MultiPort memory machine can be read out.

By having the appropriate addresses from a logic decoding network are implemented, it is possible that this program data in a separate Address area will be relocated, causing a conflict between the data area and the program area of the central memory is excluded, or certain Areas can be implemented in a targeted manner.

The addresses of the program data are immediately after the signal expander implemented and can then to any register sets or logic parts within the Centralarrays are transferred.

Protection claim 38 describes a second way how program data from the MultiPort memory machine can be read out.

The addresses of the program data are changed from the signal expander to the corresponding one Transfer the port register set of the MultiPort memory machine in unchanged form. The Addresses are then stored in the MultiPort memory machine according to the requirements implemented accordingly.

Drawings and concrete examples Fig. 1

Fig. 1 shows a typical embodiment.

The central array (CA) is the central chip. Located around this CA. there are several process modules (PMx) which, by definition, all have a signal expander (SE) contain.

PM1 consists of a microcontroller (MCU) and is via the signal expander (SE) coupled to the central array.

PM2 and PM3 each consist of a microprocessor (CPU) with immediate connected memory, and are also via the signal expander (SE) to the Centralarray coupled. An additional control line leads from the CA to the SEs from PM2 and PM3.

With PM4, which contains a microcontroller (MCU), the signal expander exists of two coupled chip chips, thus within the SE enable more extensive functions.

PM5 consists of a microcontroller (MCU) and is via the signal expander (SE) coupled to the central array.

PM6 consists of a microprocessor (CPU) with a directly connected Memory and peripheral module. The processor is connected to the via the signal expander (SE) Centralarray coupled.

In addition, there is also a RAM memory chip (Mem) directly on the central array connected so that larger amounts of data can be stored here. The central array and the signal expanders are supplied by a clock signal. The number of connections from the central array to each Signal expanders are not specified.

Fig. 2

Fig. 2 shows a minimal system, which consists only of Central array (CA) and two process modules (PMx). PM1 and PM2 each consist of a microcontroller (MCU) and are coupled to the central array via the signal expander (SE). The central array and the signal expanders are supplied by a clock signal. For the system to work, at least one line is required from the signal expander to the central array, but a larger number of lines increases the bandwidth from PM to CA.

Fig. 3

Fig. 3 shows a more extensive multiprocessor system.

The central array (CA) is again the central chip. To this central array there are several process modules (PMx) around, all of which, by definition Signal expanders included.

The central array and the signal expanders are provided with at least one clock signal provided.

The process modules PM0. .7 each have a microcontroller (MCU) and are above their Signal expander connected to the central array.

PM0 and PM1 each have a 32-bit microcontroller and 24 address, 32 data and 6 control lines go to the signal expander. 16 + 4 = 20 lines go from the signal expander to the central array, making a comm packet 16 bits wide. In normal mode, 4 comm packets are transmitted from the signal expander to the central array per processor command. If the signal expander is in special mode, the number of comm packets can also be reduced.

PM2 also has a 32-bit microcontroller with 24 address lines, 32 data lines and 6 control lines for the signal expander. However, only 8 + 3 = 11 lines go from the signal expander to the central array, which means that a comm packet is 8 bits wide. In normal mode, 8 comm packets are transmitted from the signal expander to the central array per processor command. If the signal expander is in special mode, the number of comm packets can also be reduced here.

A 32-bit microcontroller with only 18 address, 16 Data lines and 4 control lines to the signal expander. Only go from SE here 4 + 2 = 6 lines to the CA, which means that a comm packet is 4 bits wide and per processor Command now 9 comm packets are required in normal mode.

PM4 and PM5 each have a command-optimized 16-bit CISC microcontroller internal periferie, like UART, USART, ADC, DAC and special timers, which with 17 Address, 16 data lines and 4 control lines are connected to the signal expander. Here only 2 + 1 = 3 lines go to the CA, which means that a comm packet is only 2 bits wide and working in normal mode with 17 comm packets per processor instruction. The coupling from the SE to the CA runs over differential lines, for example LVDS, which makes the physical frequency very high.

PM6 has a fast 8-bit RISC microcontroller with special peripherals that with 15 address, 8 data lines and 4 control lines connected to the signal expander is. The SE-CA connection runs here with 4 + 1 = 5 lines and 4 bits set the width of the comm packet, which means that after 6 comm packets in normal mode, a processor Command has been implemented.

PM7 also has a fast 8-bit RISC microcontroller with special Periferie, but only with 8 port lines and 2 control lines to the signal expander connected is. For the SE-CA connection, 2 lines are sufficient, which means the The width of the comm packet is 2 bits. Since here only 8 bits from the processor to the CA 4 comm packets are transmitted in normal mode.

In PM8. .15 each works with a 32 bit microprocessor (CPU) connected program and data memory and separate peripheral components. The Processor is on with 24 address lines, 8 data lines and 12 additional control lines the signal expander connected. 4 + 3 = 7 lines each lead from SE to CA, which is a comm packet 4 bits wide.

With PM12, PM13 and PM14, a common line leads from the SE to the CA, which the CA can use to transmit general commands for this PM5.

In contrast to most other process modules, PM16 consists of 3 separate microcontrollers (MCU). There is a between SE and the controllers Bus multiplexer. Each of these microcontrollers can thus send its signals separately to the Transmit signal expander (SE). However, within a timeslot, only ever a processor transmit its signals to SE and therefore only one processor is active. The signal expander passes the information on to the central array. Therefor the SE8 + 4 = 12 lines, with which 8 bit wide comm packets are transmitted.

PM17 has an intelligent, fast 24 bit analog / digital converter upstream OPs, which independently read the read via different signal lines Data sent. The converter has 2 address, 8 data and 2 control lines all are led to the signal expander. There are 4 from the signal expander to the central array Lines available, with which 4 bits can be transmitted with a comm packet, and thus 6 comm packets are required to read an analog value to the Centralarray transfer.

In PM18, a 16-bit FixedPoint DSP (digital signal processor) works as a controller with integrated, coordinated periferie elements. The DSP has 18 address, 16 Data, 6 control lines and 4 additional special port lines on the Signal expander connected. The SE-CA connection runs with 8 + 5 = 13 lines, with which the comm packet width is 8 bits and because of the additional 5 lines further complex information can be transmitted.

The PM19, which contains a microcontroller (MCU), has the Signal expander made of 2 closely coupled chip chips, so inside of the SE to enable more extensive functions.

In the process modules PM20, PM21 and PM22, the SE consists of two discrete TTL shift registers and from the corresponding logic part, the one with SC designated chips. Thus, in this case, a conversion under additional Carried out using standard building blocks.

The central array consists of a complex, fine-grained and fast FPGA / CPLD, which, among other things, also offers various options for clock Offset (DLL, PLL, otherwise) offers, and special registers near the output pins has the highest possible in-out frequencies (thus high throughput Comm packets). The signal expanders exist because of their high flexibility from programmable, fast logic modules, but here for efficiency Macrocell PLDs with a wide input matrix per logic block, variable Product term sharing and with a large number of clock signals and options each Macrocell can be used. The individual signal expanders are star-shaped around that Central array arranged in order to get the shortest possible signal transit times, and around possibly to make special line terminations obsolete, and thus high Comm packet throughput between each individual signal expander and the Get centralarray.

Other elements that are not included in protection claims:
The multiprocessor system also contains a microcontroller (MCU), which is only connected directly to the CA with 3 pins due to the low data transfer volume to the central array. With an additional signal expander, the total number of pins required could be reduced to 1 pin, but this was not used in this case.

In order to obtain additional memory areas, two memory modules are connected to the central array. Mem 1 is an S / D / Q / O / H-DR-ZBT-flowtrough-SSRAM. Mem2 is an S / D / Q / O / H-DR SDRAM, FCRAM or other more powerful DRAM type.

Fig. 4

In FIG. 4 is a detailed circuit, as explained in protection claim 12, drawn. To further increase the functionality of the multiprocessor system, the central array consists of two logic chip chips. These two building blocks are closely interconnected. This interconnection runs over differential lines in order to obtain very high bit speeds per line. If a single central array block is not sufficient in terms of complexity, an improvement and efficient expansion of the system can be achieved.

Fig. 5

In Fig. 5 is a detailed circuit, as explained in protection claim 14, drawn. The 2 PM5 each consist of a microcontroller that is connected to the signal expander. 4 lines lead from the signal expander in PM1 and PM2 to the central array, additionally 4 lines from the central array are connected in parallel to the signal expander of PM1 and PM2. Depending on the signal expander mode, which can be switched from the outside, these 4 additional lines are available to the SE from PM1 or PM2. This means that an SE now has 8 lines instead of 4 lines, so the bit width of the comm packets can also increase from 4 to 8 bits for this SE.

This allows the processor that currently has the most amount of data must transfer, another 4 connecting lines must be allocated

Fig. 6

In FIG. 6 shows a possible implementation of the signal expander (SE). The processor (PZ) is coupled to the processor register set (PZRS) of the signal expander. The central array is coupled via the central array register set (CARS) of the signal expander. The processor register set contains registers for the flags, addresses and data. The central array register set contains registers for a control line to the central array and registers for the forwarding of the comm packets. The state machine (SM) is connected to the control inputs and outputs of the register sets. A connection structure between PZRS and CARS enables the transfer of addresses and data between the register sets.

Fig. 7

FIG. 7 shows the individual elements, modules and interconnections of a possible implementation of the multi-port memory machine, as described in protection claim 24.

The external processors (PZ) communicate with the port register sets (PRS), normally via address, data and control lines.

The piling machine (RM) consists of a binary counter (CNT) and decoder (DEC). The Binary counter outputs lead to the decoder. The purely combinatorial Decoder converts the individual bit patterns of the counter into individual output Control signals around, these control signals to the control terminals of the Maintain port register records and the central memory transceiver (CSTR). The signals of the Flags from the port register records lead to the inputs of the pile driver. The Central memory transceiver transfers the corresponding signals to the Central memory (CS).

Fig. 8

Fig. 8 abstracts the basic function of the system of the multi-port memory machine.

The external processors (PZ) communicate with the port register sets (PRS). The Ram machine permanently transfers the values between the port register sets and the central memory (CS).

Claims (38)

1. multiprocessor system,
characterized in that a plurality of process modules (PM) are present, one process module for itself
consists of at least one processor chip with internal or external memory,
and the term or part of the term processor can also stand for microprocessor, controller, microcontroller, CPU, DSP, special processor or special module with an independently sequential data transfer unit, and the name chip or the additional chip denotes a physical electrical component, the electrical connections used with the conductor tracks a carrier board are connected
consists of at least one logic module chip, called signal expander (SE) in the following due to its function, the connections of the processor relevant to processor communication being connected to the signal expander, this connection group on the signal expander being referred to below as the processor connection port
the logic function of the signal expander is designed in such a way that the processor signals that are fed in for data transmission can be passed on to a separate connection group on the signal expander, hereinafter referred to as the central array connection port
the individual process modules used in the system according to the invention are connected by means of their central array connection ports of the signal expanders to at least one logic module chip, hereinafter referred to as central array (CA) due to its function,
whereby at least one pin is assigned to each process module connected to the central array
and in the following each of these individual pin groups on the central array, referred to as the signal expander connection port,
Signal expander and central array are each supplied with at least one clock signal, the logic function of the central array is designed so that communication between the connected process modules can take place. 2. Multiprocessor system according to claim 1, characterized in that the logic functions of the signal expander and central array are designed such that
the register sets defined here have control connections, which, among other things, enable bits to be stored in the register set and output of stored bits from the register set,
and the term logic switching elements can represent any combination of any complex transceivers, gates, registers, flip-flops, latches or similar logic gates
the processor connection port of the signal expander is connected to a multiplicity of logic switching elements contained in the signal expander, hereinafter referred to as processor register set
the central array connection port of the signal expander is connected to a multiplicity of logic switching elements contained in the signal expander, hereinafter referred to as the central array register set
In the signal expander there is a state machine called logic machine, which is constructed with logic switching elements and controlled by the clock signal and which controls the transfer of the correspondingly required addresses and data between the processor connector port of the signal expander and the central array connector port of the signal expander, and thus the transfer between signal expander and central array, in connection with the associated logic switching elements
the signal expander connection port of the central array is connected to a multiplicity of logic switching elements contained in the central array, hereinafter referred to as the signal expander register set
in the central array there is a state machine called a state machine, associated with each signal expander port and constructed with logic switching elements and controlled by the clock signal, which controls the transfer of the required addresses and data between the signal expander connection port of the central array and the internal registers and logic switching elements of the central array, and thus controls the transfer between the signal expander and the central array, in conjunction with the associated logic switching elements, the state machine in the central array receiving the corresponding commands from the signal expander
There are logic circuits in the central array which enable the information bits sent by the signal expander to be passed on to various logic switching elements within the central array
the logic functions of the signal expander and the logic part of the central array, which is connected to the corresponding signal expander, are compatible with one another, so that the data transfer between the signal expander and the central array can take place in an ordered form,
The data transfer between processor, signal expander and central array takes place in such a way that the processor
the data is written in that
the information bits of the data to be written, which are supplied by the processor and are required for communication, are temporarily stored in the processor register set of the signal expander
these temporarily stored information bits are transported in packets to the central array register set of the signal expander by means of a state machine and are thus transported to the central array connection port
the reading of the data happens in that
the information bits of the data to be read, which are supplied by the processor and are required for communication, are temporarily stored in the processor register set of the signal expander
these temporarily stored information bits are transported in packets to the central array register set of the signal expander by means of a state machine and are thus transported to the central array connection port
the corresponding resulting data bits are transported in packets from the signal expander connection port of the central array to the central array connection port of the signal expander by means of a state machine, these data bits are then transported further to the processor register set of the signal expander
these data bits can then be read by the processor from the processor register set of the signal expander. 3. Multiprocessor system according to claim 1 or 2, characterized in that the signal expander is such that
whose processor register set has separate registers or flip-flops for addresses, data and control flags, and the control flags contain at least the appropriate flags "WR" for write and "RD" for read
whose processor register set is such that the processor
the data is written in that
the address and data bits relevant for communication, the data to be written by the processor, are stored in the address and data register of the processor register set by means of the responsible control line also coming from the processor
the WR flag is activated
the reading of the data happens in that
the address bits relevant for communication, the data to be read, are stored in the address register of the processor register set by means of the control line also coming from the processor
the RD flag is activated
the processor can read the data from the data register of the processor register set
whose central array register set is designed such that it can, depending on control signals applied to the central array register set, place certain bit patterns on the central array connection port, so that the connected central array can receive and decode these bits as a corresponding command
whose connection structures between processor register set and central array register set are designed in such a way that
the address and data bits with which the bit width required for the central array register set can be transferred from the processor register set to the central array register set,
the data bits contained in the central array register set, with the bit width required for the central array register set, can be transferred to the processor register set
at least one clock signal and the signals of the WR and RD flags of the processor register set lead to the inputs of the state machine in the signal expander
the outputs of the state machine in the signal expander lead to the control connections of the processor register set and the central array register set in the signal expander
whose state machine, processor register set and central array register set and the relevant registers are designed and processor register set and central array register set and the relevant registers are controlled by the state machine such that
an active WR or RD flag in the processor register set activates the state machine, the state machine executing a write command when the WR flag is active and executing a read command when the RD flag is active
the write command initiated by the state machine is executed in that
the central array register set is caused to output a bit pattern to the central array port, which bit pattern serves as a write command for the central array
the address and data bits from the processor register set are transferred to the central array connection port of the signal expander by means of sequential, with the aid of the clock, transmitted individual packets, referred to as communication packet or comm packet, the bit width and the amount of these comm packets depending on the width of the central array connection port
the WR flag of the processor register set is deactivated
the read command initiated by the state machine is carried out in that
the central array register set is caused to output a bit pattern to the central array port, which bit pattern serves as a read command for the central array
the address bits from the processor register set are transferred to the central array connection port of the signal expander by means of individual comm packets transmitted sequentially, with the aid of the clock, the bit width and the amount of comm packets depending on the width of the central array connection port
the data arriving in the central array register set and sent by the central array are transferred to the processor register set by means of sequential, with the help of clock, transmitted individual comm packets, the bit width and the amount of comm packets depending on the width of the central array connection port, then
the RD flag of the processor register set is deactivated. 4. Multiprocessor system according to one of claims 1 to 3, characterized in that the central array and the individual logic circuits and register sets in the central array are such that
the state machine associated with the respective signal expander port, in the case of the inactive state, samples the signals on the signal expander port according to known bit patterns and thus according to known commands, and when the command is recognized the correspondingly required state is set in the state machine, whereby
in the event of a recognized write command, the addresses and data supplied by the signal expander in individual comm packets are transferred to the appropriate registers, and the state machine returns to the inactive state after the transfer
in the event of a recognized read command, the addresses supplied by the signal expander in individual comm packets are transferred to correspondingly provided registers, then the data corresponding to the delivered address are transferred to the signal expander port, and the state machine returns to the inactive state after the transfer. 5. Multiprocessor system according to one of claims 1 to 4, characterized in that the signal expander and the central array is such that
the processor register set in the signal expander additionally contains the control flag with the corresponding designation "PRG" for program memory
the processor register set in the signal expander is such that the processor
the reading of the program data happens in that
the address bits relevant for communication, the program data to be read, are stored in the address register of the processor register set by means of the control line also coming from the processor
the flag PRG is activated
the processor can read the program data from the corresponding register of the processor register set
in the central array there is a state machine called a state machine, associated with each signal expander port and constructed with logic switching elements and controlled by the clock signal, which transfers the correspondingly required addresses and program data between the signal expander connection port of the central array and the internal registers and logic switching elements of the central array, and thus controls the transfer between the signal expander and the central array, in conjunction with the associated logic switching elements, the state machine receiving the corresponding commands from the signal expander
There are logic circuits in the central array which enable the information bits sent by the signal expander to be passed on to various logic switching elements within the central array and that the program data can be transmitted to the signal expander in a form which is compatible with the signal expander. 6. Multiprocessor system according to one of claims 1 to 5, characterized in that
All relevant processor connections that are necessary for the transmission of the processor-specific memory and InOut bus protocol of the processor used in the process module are connected to the signal expander
the logic function of the signal expander is designed so that the entire processor-specific memory and InOut bus protocol of the processor used in the respective process module is broken down into comm packets, these comm packets are transferred to the central array register set and thus to the central array connection port of the signal expander and these comm packets thus to the central array are transferred, the central array reassembling these comm packets, with which all of the information contained in the bus protocol of the processor is transferred from the signal expander to the central array. 7. Multiprocessor system according to one of claims 1 to 6, characterized in that An evaluation circuit is present in the signal expander, which can be adjusted using pins reports from the outside whether the signal expander internal state machine is free or still is busy. 8. Multiprocessor system according to one of claims 1 to 7, characterized in that a logic circuit in the signal expander is created so that the clock signal for the connected processor can be made available, this Logic circuit enables a clean stopping of the clock signal as long as the signal expander internal state machine is still busy. 9. Multiprocessor system according to one of claims 1 to 8, characterized in that in at least one signal expander an address comparator and evaluation logic for the addresses transmitted by the processor is implemented, which enables that instead of specific addresses, only short address commands to the central array are transferred, after which the currently recognized short in the central array Address command is converted into a valid address and accordingly responsible register is filed. 10. Multiprocessor system according to one of claims 1 to 9, characterized in that in at least one signal expander an address comparator and evaluation logic for the addresses transmitted by the processor is implemented, which enables that instead of specific addresses, extended address commands to the central array are transferred, then in the central array depending on the current recognized extended address command, a predefined valid address in the the relevant register appears. 11. Multiprocessor system according to one of claims 1 to 10, characterized in that the free logic resources and free pins of the signal expander chip are used for this through additional registers and additional inclusion of pins, the existing direct InOut port signals and pins of the connected processor to expand. 12. Multiprocessor system according to one of claims 1 to 11, characterized in that The central array consists of several logic chip chips that are tightly wired together exists, the logic functions in these chips are such that the Chips work in their entirety like a large, complex central array, and that lines coming from the signal expanders to the central array also to several Can lead chips of the central array in parallel. 13. Multiprocessor system according to one of claims 1 to 12, characterized in that a signal expander consisting of several logic chip chips that are tightly wired together exists, the logic functions in these chips are such that the Chips work in their entirety like a large, complex signal expander, and the lines coming from the central array to the signal expander can carry several chips of the signal expander in parallel. 14. Multiprocessor system according to one of claims 1 to 13, characterized in that at least one connection line from the central array to the signal expander additionally to at least one other signal expander from another Process module is run in parallel. 15. Multiprocessor system according to one of claims 1 to 14, characterized in that one or a few additional lines from the central array to the signal expanders lead, with implemented logic circuits in central array and signal expander ensure that these additional lines, commands and special Messages can be transferred from the central array to the signal expander. 16. Multiprocessor system according to one of claims 1 to 15, characterized in that the signal expander consists of several chips and different chips thereof Standard shift register building blocks are, whereby these shift registers are by suitable logic circuits are controlled and the shift registers the parallel Serial or serial-parallel conversion of the addresses and the read ones and write data. 17. Multiprocessor system according to claim 16, characterized in that the logic circuits for controlling the shift registers for several signal expanders are combined in one chip. 18. Multiprocessor system according to one of claims 1 to 17, characterized in that the logic circuit in the signal expander is designed in such a way that at the time the active ALE signal (AdressLatchEnable) of the processor the data to be read are transferred from the central array to the signal expander and this data is only stored in the If the RD signal generated by the processor are transmitted to the processor. 19. Multiprocessor system according to one of claims 1 to 18, characterized in that there is a line from the signal expander to the central array, via which the ALE signal and the WR and RD signals of the Processor can be transferred to the central array. 20. Multiprocessor system according to claim 19, characterized in that isochronous signal sampling on the connecting line and that Protocol is designed so that the first active level on the line as an ALE signal of the processor is interpreted and the subsequent level change on the line is interpreted as an active WR / RD signal of the processor and at the next clock the specific WR or RD signal, depending on the signal level, is detected. 21. Multiprocessor system according to one of claims 1 to 20, characterized in that there are individual registers in the central array and these are interconnected so that several process modules via the respective signal expander connection ports on Centralarray, read and write access to these registers, and in various data blocks can be stored in these registers. 22. Multiprocessor system according to one of claims 1 to 21, characterized in that In the central array, there are also several memory blocks and these can be created using Logic circuits are connected in such a way that several process modules are connected via the respective signal expander connection ports on the central array, reading and writing can access these blocks of memory. 23. Multiprocessor system according to one of claims 1 to 22, characterized in that the interconnection of certain registers or certain memory blocks or storage areas in the central array is designed so that these areas with Access rights and access priorities regarding the different Signal expander register sets can be equipped. 24. Multiprocessor system according to one of claims 1 to 23, characterized in that
In the central array there is a group of special logic circuits, hereinafter referred to as multi-port memory machines, whose sequential logic control, through continuous access to a large number of logic switching elements connected to connection ports, and the transfer of the corresponding addresses and data with a central memory, as a variable, in Port size and number of scalable, readable and writable MultiPort memory is functional, whereby the individual connection ports can be operated completely asynchronously
at least one memory module, hereinafter referred to as the central memory, containing at least one connection group for address, data and control signals, is present in the system, the central memory being located in the central array or being a separate chip
the signal connections of the central memory are connected to the logic circuit of the multi-port memory machine via logic switching elements, the amount of these logic switching elements being referred to below as the central memory transceiver
the logic circuit of the MultiPort memory machine contains a plurality of connection ports, whereby
individual connection ports are intended for the completely independent and asynchronous, read or write access of the individual, external processor to the central memory,
and the term external processor is used for such a processor or module that accesses the central memory of the multi-port memory machine via the port register sets, the external processor being located outside the multi-port memory machine, but can be located inside or outside the central array chip
the individual connection port has connections so that the address, data and control signals can be transmitted
Different logic switching elements, called port register sets, are connected to the individual connection port, the individual port register set has separate registers or flip-flops for addresses, data and control flags, and the control flags contain at least the appropriate flags "WR" for write and "RD" for read
the port register sets are such that the external processor
the data is written in that
the address and data bits of the data to be written are stored in the address and data register of the port register set
the WR flag is activated
the reading of the data happens in that
the address bits of the data to be read are stored in the address register of the port register set
the RD flag is activated
the data can be read from the data register of the port register set
the port register sets and the central storage transceiver are designed in this way, and the connection structures between the port register sets and the central storage transceiver are created,
that the address and data bits can be transferred to the central memory in any port register set, and the data bits in the central memory can be transferred to any port register set
a sequential logic control, in the form of a state machine, constructed in the form of logic switching elements and controlled by the clock signal, hereinafter referred to as a ram machine, is present in the multi-port memory machine, wherein
at least one clock signal and the required flags of the port register sets lead to the inputs of the pile driver
the outputs of the pile driver lead to the control connections of the port register sets and the central memory transceiver
the pile driver, the port register sets and the relevant registers are designed and the port register sets and the relevant registers are controlled by the pile driver in such a way that
In order to recognize a necessary data transfer between individual port register sets and central memory, at least the WR and RD flags of the corresponding port register sets are scanned, hereinafter referred to as scanning, whereby, when the WR flag is active, the writing of the data into the central memory is initiated, with active RD Flag reading data from the central store is initiated, and if all flags are inactive, no transfer is performed
the writing of the data initiated by the pile driver from the corresponding port register set to the central memory occurs in that
the address and data bits from the port register set are transferred to the corresponding address and data connections of the central memory
the control signals for creating the addresses and for writing the data into the central memory are switched
the WR flag is deactivated
the reading of the data from the central memory into the corresponding port register set initiated by the ram happens in that
the address bits are transferred from the port register set to the address connections of the central memory,
the control signals for reading the data are switched to the central memory,
the data read from the central memory are then transferred to the data register of the corresponding port register set, then
the RD flag is deactivated. 25. Multiprocessor system according to claim 24, characterized in that
at least one port register set has the flag with the corresponding designation "WB" for WriteBusy
at least one connection port and port register set is such that the external processor can read the flag WB
the WB flag is activated when the external processor writes data into the port register set
the function of the pile driver and the relevant registers are designed in such a way that the writing of the data into the central memory from the corresponding port register set initiated by the pile machine takes place in that after the data has been transferred to the central memory, the flag WB is deactivated. 26. Multiprocessor system according to one of claims 24 to 25, characterized in that
at least one port register set has the flag with the corresponding designation "RE" for ReadEnd
at least one connection port and port register set is such that
the external processor can read the RE flag
when the external processor writes a data read request to the port register set, the RE flag is deactivated
the function of the pile driver and the relevant registers are designed in such a way that the reading of the data from the central memory into the corresponding port register set, which is initiated by the pile machine, takes place in that after the data has been transferred to the data register of the port register set, the flag RE is activated. 27. Multiprocessor system according to one of claims 24 to 26, characterized in that
at least one connection port and port register set are such that certain control bits and addresses transmitted by the external processor are interpreted as short address commands,
after which the currently recognized short address command is converted into a valid address and stored in the address register of the port register set. 28. Multiprocessor system according to one of claims 24 to 27, characterized in that at least one connection port and port register set is created that certain control bits and addresses transmitted by the external processor as extended address commands are interpreted, after which, depending on the currently recognized extended address command, a predefined valid address in the address register of the port register set appears. 29. Multiprocessor system according to one of claims 24 to 28, characterized in that the system and the pile driver is designed so that the scanning of the Port register records with fixed, deterministic time division happens and so for each port register set uses an equally long timeslot, with which it It is irrelevant whether a transfer from the port register set currently being scanned or must be carried out to the central memory or not. 30. Multiprocessor system according to one of claims 24 to 29, characterized in that the system and the pile driver is designed so that the scanning of the Port register records in the way that happens when scanning a Port register set the need for data transfer is not determined that Pile driver directly scans the next port register set, and does not wait for the time it would take to transfer data. 31. Multiprocessor system according to one of claims 24 to 30, characterized in that the system and the piling machine is designed so that the order of the Port register set scans can be changed using control signals, the required Lead the control connections to the inputs of the pile driver. 32. Multiprocessor system according to one of claims 24 to 31, characterized in that the system and the piling machine is designed so that during a complete Runs through port register set scans one or more port register sets be scanned once. 33. Multiprocessor system according to one of claims 24 to 32, characterized in that the system and the piling machine is designed so that the piling machine before it performs the transfer between central memory and port register records, first from reads the individual jobs into all port register records, these according to DatenRead and DataWrite maps, and then the data transfers for DataRead respectively DataWrite runs in quick succession. 34. Multiprocessor system according to one of claims 24 to 33, characterized in that the system and the piling machine is designed so that a certain status of the Ram machine can be triggered by a port register set. 35. System according to one of claims 24 to 34, characterized in that several MultiPort memory machines are implemented in the central array. 36. System according to one of claims 1 to 35, characterized in that
the logic circuit in the central array is such that the write, read or program read jobs pending on the corresponding signal expander register set are processed in that
the corresponding address and data bits and the corresponding control signals are transferred between the respective signal expander register set in the central array and the processing logic part of the circuit in the central array or the corresponding port register set in the multi-port memory machine. 37. System according to one of claims 24 to 36, characterized in that
in the central array there is a combinatorial logic decoding network belonging to the signal expander register set, hereinafter called preadress descriptor, which enables the bit patterns of the output to depend on the bit patterns of the input and on an algebraic function, which algebraic function can be fixed or depending on control signals at the pre-address descriptor
the logic circuit in the central array is such that
a control logic associated with the corresponding signal expander register set is present and that reading of the program data initiated by this control logic takes place in that
the address bits from the signal expander register set are routed to the inputs of the pre-address descriptor
the bits at the outputs of the pre-address descriptor are forwarded to the logic part of the circuit which is to be further processed or to the corresponding port register set of the MultiPort memory machine
the control signals required for reading the program data are connected to the logic part of the circuit which is to be further processed or to the corresponding port register set of the MultiPort memory machine. 38. System according to one of claims 24 to 37, characterized in that
at least one port register set additionally contains the control flag with the corresponding designation "PRG" for program memory, and that the signals of these PRG flags lead to the inputs of the pile driver
there is a combinatorial logic decoding network associated with each port register set, hereinafter called the address descriptor, which enables the bit patterns of the output to depend on the bit patterns of the input and on an algebraic function, which algebraic function may be fixed or itself , depending on control signals at the address descriptor
the port register sets are such that the external processor
reading the program data is done by the fact that
the address bits of the program data to be read are stored in the address register of the port register set
the flag PRG is activated
the program data can be read from the corresponding register in the port register set
the pile driver, the port register sets and the relevant registers are designed and the port register sets and the relevant registers are controlled by the pile driver in such a way that
In order to recognize a necessary data transfer between individual port register sets and central memory, the PRG flags of the corresponding port register sets are additionally scanned, reading of the program data from the central memory being initiated when the PRG flag is active
the reading of the program data from the central memory into the corresponding port register set initiated by the ramming machine occurs in that
the address bits are transferred from the port register set to the inputs of the address descriptor
the bits at the outputs of the address descriptor are transferred to the address connections of the central memory,
the control signals for reading the data from the central memory are switched,
the data read from the central memory are then transferred to the corresponding register of the corresponding port register set, then
the PRG flag is deactivated.