CN1901161A - 连续电镀制作线路组件的方法及线路组件结构 - Google Patents

连续电镀制作线路组件的方法及线路组件结构 Download PDF

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CN1901161A
CN1901161A CNA2006100994900A CN200610099490A CN1901161A CN 1901161 A CN1901161 A CN 1901161A CN A2006100994900 A CNA2006100994900 A CN A2006100994900A CN 200610099490 A CN200610099490 A CN 200610099490A CN 1901161 A CN1901161 A CN 1901161A
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layer
metal
metal level
microns
thickness
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CN1901161B (zh
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林茂雄
罗心荣
周秋明
周健康
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Qualcomm Inc
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Megica Corp
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Abstract

本发明提供一种形成覆盖有聚醯亚胺(polyimide，PI)的连续电镀结构的方法，其包括(a)提供一半导体基底；(b)在该半导体基底上形成一黏着/阻障层；(c)在该黏着/阻障层上形成复数金属线路层(metal trace)；(d)在该些金属线路层中选择一目标区域做为接垫，并在该接垫上形成一金属层；(e)去除未被覆盖的该黏着/阻障层；以及(f)形成一聚醯亚胺在该半导体基底上，并暴露出该金属层。

Description

连续电镀制作线路组件的方法及线路组件结构
技术领域
本发明涉及一种连续电镀制作线路组件的方法及线路组件结构，特别涉及一种覆盖聚醯亚胺(polyimide，PI)的连续电镀成型结构。
背景技术
现今大多的半导体组件是用来处理数字资料，然而也有部分的半导体组件整合有模拟的功能，如此半导体组件便可以同时处理数字资料及模拟资料，或者半导体组件亦可以仅具有模拟的功能。制造模拟电路的主要困难点之一是在于许多用于模拟电路的电子组件甚大，难以与次微米极的电子组件整合，尤其是针对被动组件而言，此乃因为被动组件的尺寸过于庞大。
美国专利公告第5,212,403号(Nakanishi)公开一种形成线路联机的方法，其中内部及外部的线路联机是形成在位于芯片上的线路基底内，并且逻辑线路的设计会取决于线路联机的长度。
美国专利公告第5,501,006号(Gehman，Jr.et al.)公开一种集成电路与线路基底之间具有绝缘层的结构，而藉由分散出去的引脚可以是芯片的接点与基板的接点电性连接。
美国专利公告第5,055,907号(Jacobs)公开一种整合型半导体结构，可以允许制造商将一薄膜多层线路形成在支撑基板上或芯片上，藉以整合位在芯片外的电路。
美国专利公告第5,106,461号(Volfson et al.)公开一种多层联机结构，其是藉由TAB结构并利用聚醯亚胺(polyimide)的介电层及金属层交互叠合于芯片上而成。
美国专利公告第5,635,767号(Wenzel et al.)公开一种在PBGA结构中降低电阻电容迟缓效应的方法，其中多层金属层是分开配置。
美国专利公告第5,686,764号(Fulcher)公开一种覆晶基板，藉由将电源线与输入输出引线分开配置，可以降低电阻电容迟缓效应。
美国专利公告第6,008,102号(Alford et al.)公开一种利用两层金属层所形成的螺旋状电感组件，其中此两层金属层可以利用导通孔连接。
美国专利公告第5,372,967号(Sundaram et al.)公开一种螺旋状电感组件。
美国专利公告第5,576,680号(Ling)及第5,884,990号(Burghartz et al.)公开一种其它形式的螺旋状电感组件。
美国专利公告第6,383,916号公开一种芯片结构具有重配置线路层及金属联机层，是配置在介电层上，其中介电层是位于传统芯片的保护层上。保护层是位于集成电路上，而厚的聚合物层是选择性地配置在保护层上，宽的或厚的金属联机是位在保护层上。
美国专利公告第6,303,423号公开一种形成具有高感应系数的电感组件于芯片的保护层上的结构。此种具有高感应系数的电感组件可以应用在高频电路中，并且可以减少电能的损耗。在此案中，还公开电容组件及电阻组件，可以形成在硅基底的表面上，藉以减少位于硅基底下的电子组件所引发出的寄生效应。
美国专利公告第6,869,870号(Lin)公开一种变压器形成在晶圆的保护层上。
有鉴于此，本发明是针对上述被动组件各种技术，提出一种连续电镀制作线路组件的方法及线路组件结构，用以应用在半导体被动组件领域上。
发明内容
本发明的主要目的是在于提供一种连续电镀制作线路组件的方法及线路组件结构，其是在保护层上具有一线圈线路层的半导体芯片，其中顶层线圈线路层可以承受高电压高电流，且控制顶层线圈线路层的电流变化可以产生一感应电动势以感应其它线圈。
本发明的另一目的是在于提供一种连续电镀制作线路组件的方法及线路组件结构，其是公开数种在线圈上以连续电镀方式形成对外的接点，比如形成接垫(pad)、凸块(bump)等，此接垫及凸块皆可透过打线或异方式导电胶电连接至外界电路上，使半导体组件的应用更具多元化连接方式。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金线路层，位在该保护层上，该金线路层具有一接垫；一镍层，位在该接垫上；一焊料层，位在该镍层上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一第一金属层，位在该接垫上；一第一聚合物层，位在该保护层及该金属线路层上，该第一聚合物层具有至少一开口曝露出该第一金属层。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金线路层，位在该保护层上，该金线路层具有一第一接垫及一第二接垫；一镍层，位在该第一接垫上；一焊料层，位在该镍层上；一导线，位在第二接垫上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；一金线路层，位在该保护层上，该金线路层具有一接垫；一铜层，位在该接垫上；一焊料层，位在该铜层上。
为了本发明上述的目的，提出一种线路组件结构，包括：一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金线路层，位在该保护层上，该金线路层具有一第一接垫及一第二接垫；一铜层，位在该第一接垫上；一焊料层，位在该铜层上；一导线，位在该第二接垫上。
为了本发明上述的目的，提出一种线路组件结构，包括：一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一铜线路层，位在该保护层上，该铜线路层具有一接垫；一镍层，位在该接垫上；一焊料层，位在该镍层上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；一铜线路层，位在该保护层上，该铜线路层具有一第一接垫及一第二接垫；一镍层，位在该第一接垫上；一焊料层，位在该镍层上；一金层，位在该第二接垫上；一导线，位在该金层上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一铜线路层，位在该保护层上，该铜线路层具有一接垫；一金层，位在该接垫上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一铜线路层，位在该保护层上，该铜线路层具有一第一接垫及一第二接垫；一第一金层，位在该第一接垫上，该第一金层的厚度是介于10微米至50微米之间；一第二金层，位在该第二接垫上，该第二金层的厚度是介于0.1微米至10微米之间。
为了本发明上述的目的，提出一种线路组件结构，包括：一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一铜线路层，位在该保护层上，该铜线路层具有一接垫；一镍层，位在该接垫上；一金层，位在该镍层上，该金层的厚度是介于1微米至50微米之间。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；一金线路层，位在该保护层上，该金线路层具有一接垫；一金层，位在该接垫上；一导线，位在该金层上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一第一金属层，位在该接垫上；一第一聚合物层，位在该保护层及该金属线路层上，该第一聚合物层具有至少一开口曝露出该第一金属层。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该第一线圈上；一线圈金属层，位在该保护层上，该线圈金属层具有一第一接垫及一第二接垫；一第一图案化聚合物层，位在该线圈金属层上，该第一图案化聚合物层的开口曝露出该线圈金属层的该第一接垫及该第二接垫；一凸块，位在该线圈金属层的该第一接垫；一导线，位在该线圈金属层的该第二接垫。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一保护层，位在该半导体基底上；
一第一图案化线路层，位在该保护层上；一第一图案化聚合物层，覆盖在该第一图案化线路层及该保护层上，该第一图案化聚合物层的开口曝露出该第一图案化线路层；一第一金属层，位在该第一图案化聚合物层的开口内；一第一线圈，位在该第一图案化聚合物层上并电连接至该第一金属层。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一第一金属层，位在该接垫上；一第一聚合物层，位在该第一金属层的侧缘包覆该第一金属层，其中位在该第一金属层顶部的该第一聚合物层具有至少一开口曝露出该第一金属层。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一金层，位在该接垫上；利用卷带自动贴合(Tape AutomatedBonding；TAB)使该金层接合在一软性基板上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一金层，位在该接垫上；利用一异方性导电胶(ACF)使该金层接合在一软性基板上。
为了本发明上述的目的，提出一种线路组件结构，包括一半导体基底；一细联机结构，位在该半导体基底上；一保护层，位在该细联机结构上；一金属线路层，位在该保护层上，该金属线路层具有一接垫；一金层，位在该接垫上；利用一异方性导电胶(ACF)使该金层接合在一玻璃基板上。
此外，为了本发明上述的目的，提出一种连续电镀制作线路组件的方法，其特征在于，其步骤包括：
提供一半导体基底、一细联机结构、一第一线圈及一保护层，其中该细联机结构位在该半导体基底上，该保护层位在该细联机结构上，该第一线圈位在该保护层上，该第一线圈具有一接垫位在该保护层上；
形成一第一图案化光阻层在该第一线圈及该保护层上，该第一图案化光阻层具有至少一开口暴露出该接垫；
形成一第一金属层在该第一图案化光阻层的该开口内；以及
去除该第一图案化光阻层。
底下藉由具体实施例配合所附的图式详加说明，当更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1a至图1d为本发明半导体基底的细联机结构及保护层的制作方法剖面示意图；
图2a至图2v为本发明第一实施例的制作方法剖面示意图；
图3a至图3b为本发明第二实施例的制作方法剖面示意图；
图4a至图4h为本发明第三实施例的制作方法剖面示意图；
图5a至图5c为本发明第四实施例的制作方法剖面示意图；
图6a至图6d为本发明第五实施例的制作方法剖面示意图；
图7a至图7k为本发明第六实施例的制作方法剖面示意图；
图8a至图8f为本发明第七实施例的制作方法剖面示意图；
图9a至图9f为本发明第八实施例的制作方法剖面示意图；
图10a至图10l为本发明第九实施例的制作方法剖面示意图；
图11a至图11z为本发明第十实施例的制作方法剖面示意图。
附图标记说明：10半导体基底；12电子组件；14细联机结构；16薄膜绝缘层；18细线路层；20导通孔；22保护层；24接垫；202聚合物层；204聚合物层；206黏着/阻障层；208种子层；210光阻层；212开口；214金属层；216光阻层；218开口；220金属层；222聚合物层；224开口；226半导体组件；228导线；230软性基板；232聚合物；234异方性导电胶；236玻璃基板；238软板；240外界电路板；242聚合物层；244镍金属层；246金层；248聚合物层；250开口；252聚合物层；254开口；256光阻层；258开口；260金属层；262光阻层；264开口；266金属层；268光阻层；270开口；272金属层；274黏着/阻障层；276种子层；278光阻层；280开口；282金属层；284聚合物层；286开口；288聚合物层；290开口；294黏着/阻障层；296种子层；298光阻层；300开口；302金属层；304重配置线路层；306图案化光阻层；308开口；310金属层；312聚合物层；314黏着/阻障层；316种子层；318光阻层；320开口；322金属层；324光阻层；326金属层；328光阻层；330金属层；332聚合物层；334开口。
具体实施方式
本发明为连续电镀制作线路组件的方法及线路组件结构，其中在此发明之中公开数种在金属线路层上以连续电镀方式形成接垫(pad)、凸块(bump)等方法及结构，而所公开的每一种方法及结构皆是建构在一半导体基底上，且在此半导体基底上更设有一细联机结构及一保护层，因此首先解说此半导体基底、细联机结构及保护层的结构及形成方法后，再进行本发明各种实施例的解说。
请参阅图1a所示，此半导体基底10为的形式比如是硅基底、砷化镓基底(GAAS)、硅化锗基底、具有磊晶硅在绝缘层上(silicon-on-insulator，SOI)的基底，半导体基底10在此实施例中为圆形之一半导体晶圆，且此半导体基底10具有一主动表面，在半导体基底10的主动表面透过掺杂五价或三价的离子(例如硼离子或磷离子等)形成多个电子组件12，此电子组件12例如是金属氧化物半导体或晶体管，金氧半导体组件(MOS devices)，P信道金氧半导体组件(p-channel MOSdevices)，n信道金氧半导体组件(n-channel MOS devices)，双载子互补式金氧半导体组件(BiCMOS devices)，双载子连接晶体管(Bipolar Junction Transistor，BJT)，扩散区(Diffusion area)，电阻组件(resistor)，电容组件(capacitor)及互补金属氧化半导体(CMOS)等。
请参阅图1b所示，在半导体基底10的主动表面上形成一细联机结构14，此细联机结构14是由复数厚度小于3微米的薄膜绝缘层16及厚度小于3微米的细线路层18所构成，其中细线路层18是选自铜金属材质或铝金属材质，而薄膜绝缘层16又称为介电层，一般是利用化学气相沉积的方式所形成。此薄膜绝缘层16比如为氧化硅、化学气相沉积的四乙氧基硅烷(TEOS)氧化物、SiwCxOyHz、氮硅化合物、氟化玻璃(FSG)、黑钻石薄膜(Black Diamond)、丝印层(SiLK)、多孔性氧化硅(porous silicon oxide)或氮氧硅化合物，或是以旋涂方式形成的玻璃(SOG)、聚芳基酯(polyarylene ether)、聚苯恶唑(polybenzoxazole，PBO)，或者薄膜绝缘层16为其它介电常数值小于3的材质。
在形成复数细线路层18在半导体基底10上的过程中，就金属镶嵌制作方法而言，是先溅镀一扩散阻絶层在一薄膜绝缘层16的开口内的底部及侧壁上及薄膜绝缘层16的上表面上，接着再溅镀一层例如是铜材质的种子层在扩散阻絶层上，接着再电镀一铜层在此种子层上，接着再利用化学机械研磨(chemical mechanicalpolishing，CMP)的方式去除位在该薄膜绝缘层16的开口外的铜层、种子层及扩散阻絶层，直到曝露出薄膜绝缘层16的上表面为止。而另一种方式亦可以先溅镀一铝层或铝合金层在一薄膜绝缘层16上，接着再利用微影蚀刻的方式图案化铝层或铝合金层。此细线路层18可透过薄膜绝缘层16内的导通孔20相互连接，或连接至电子组件12上，其中细线路层18一般的厚度是在0.1微米到0.5微米之间，在进行微影制作方法时细线路层18的细金属线路是使用五倍(5X)的曝光机(steppers)或扫描机(scanners)或使用更佳的仪器来制作。
请参阅图1c及图1d所示，接着在半导体基底10的表面利用化学气相沉积(CVD)方式设置一保护层22，此保护层22可开设复数缺口曝露出多数接垫24，此接垫24在本发明后续实施例中的应用，在此并不详加叙述。保护层22可以保护半导体基底10内的电子组件12免于湿气与外来离子污染物(foreign ioncontamination)的破坏，也就是说保护层22可以防止移动离子(mobile ions)(比如是钠离子)、水气(moisture)、过渡金属(transition metal)(比如是金、银、铜)及其它杂质(impurity)穿透，而损坏保护层22下方的晶体管、多晶硅电阻组件或多晶硅-多晶硅电容组件的电子组件12或细金属线路。为了达到保护的目的，保护层22通常是由氧化硅(silicon oxide)、氧硅化合物、磷硅玻璃、氮化硅(silicon nitride)、及氧氮化硅(silicon oxy-nitride)等所组成，而保护层22以目前制作方式约有10种不同方法。
第一种保护层22制作方法是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该氧化硅层上。
第二种保护层22制作方法可以是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层，接着再利用电浆加强型化学气相沉积的步骤形成厚度介于0.05至0.15微米间的一氮氧化硅层在该氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该氮氧化硅层上。
第三种保护层22制作方法可以是先利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的一氮氧化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层在该氮氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该氧化硅层上。
第四种保护层22制作方法可以是先利用化学气相沉积的步骤形成厚度介于0.2至0.5微米间的一第一氧化硅层，接着再利用旋涂法(spin-coating)形成厚度介于0.5至1微米间的一第二氧化硅层在该第一氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至0.5微米间的一第三氧化硅层在该第二氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该第三氧化硅层上。
第五种保护层22制作方法可以是先利用高密度电浆化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的一氧化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该氧化硅层上。
第六种保护层22制作方法可以是先形成厚度介于0.2至3微米间的一未掺杂硅玻璃层(undoped silicate glass，USG)，接着形成比如是四乙氧基硅烷(TEOS)、硼磷硅玻璃(borophosphosilicate glass，BPSG)或磷硅玻璃(phosphosilicate glass，PSG)等的厚度介于0.5至3微米间的一绝缘层在该未掺杂硅玻璃层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该绝缘层上。
第七种保护层22制作方法可以是选择性地先利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的一第一氮氧化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层在该第一氮氧化硅层上，接着可以选择性地利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的一第二氮氧化硅层在该氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该第二氮氧化硅层上或在该氧化硅层上，接着可以选择性地利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的一第三氮氧化硅层在该氮化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层在该第三氮氧化硅层上或在该氮化硅层上。
第八种保护层22制作方法可以是先利用化学气相沉积(PECVD)的步骤形成厚度介于0.2至1.2微米间的一第一氧化硅层，接着再利用旋涂法(spin-coating)形成厚度介于0.5至1微米间的一第二氧化硅层在该第一氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一第三氧化硅层在该第二氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该第三氧化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一第四氧化硅层在该氮化硅层上。
第九种保护层22制作方法可以是先利用高密度电浆化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的一第一氧化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氮化硅层在该第一氧化硅层上，接着再利用高密度电浆化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的一第二氧化硅层在该氮化硅层上。
第十种保护层22制作方法可以是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一第一氮化硅层，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一氧化硅层在该第一氮化硅层上，接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的一第二氮化硅层在该氧化硅层上。
其中在半导体基底10上的保护层22的厚度一般是大于0.35微米，在较佳的情况下，氮化硅层的厚度通常大于0.3微米。
至此半导体基底10、细联机结构14及保护层22解说完成，以下就依序分别解说本发明的各个实施例，其中每一实施例皆是在保护层22上进行。
第一实施例
此第一实施例是以在半导体基底10上形成被动组件为说明标的，其中此被动组件例如是电感(线圈)组件、电阻组件、电容组件等，请参阅图2a所示，利用旋涂(spin-coating)方式形成一聚合物层202在保护层22，此聚合物层202具有絶缘功能，且此聚合物层202的材质是选自材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide，PI)、苯基环丁烯(benzo-cyclo-butene，BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料其中之一。而此聚合物层202除了利用旋涂(spin-coating)方式也可以利用热压合干膜方式、网版印刷方式进行，此聚合物层202的厚度是介于2微米至50微米之间。
请参阅图2b所示，另外为了加强此聚合物层202的絶缘功能，可再利用旋涂方式再形成另一聚合物层204，增加整体絶缘的性能，其中此聚合物层204的厚度是介于2微米至50微米之间。
接着将聚合物层202及聚合物层204以烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度，以硬化(curing)聚合物层202及聚合物层204，硬化后的聚合物层202及聚合物层204在体积上会呈现缩小的情形，且聚合物层202及聚合物层204含水率小于1％，此含水率是将聚合物层202及聚合物层204置放在温度介于摄氏425度至450度下时，其重量变化率小于1％。
请参阅图2c所示，接着溅镀形成厚度介于400埃至7000埃一黏着/阻障层206(Adhesion/Barrier/seed layer)在保护层22及聚合物层204上，此黏着/阻障层206的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一，接着如图2d所示，形成一种子层208在此黏着/阻障层206上，此种子层208有利于后续金属线路的设置，因此种子层208的材质也随后续的金属线路材质有所变化，此外在本文后续实例中所有黏着/阻障层上皆形成有一种子层，在此特以说明。
当种子层上是电镀形成铜材质的金属线路时，种子层的材料是以铜为佳；当要电镀形成银材质的金属线路时，种子层的材料是以银为佳；当要电镀形成钯材质的金属线路时，种子层的材料是以钯为佳；当要电镀形成铂材质的金属线路时，种子层的材料是以铂为佳；当要电镀形成铑材质的金属线路时，种子层的材料是以铑为佳；当要电镀形成钌材质的金属线路时，种子层的材料是以钌为佳；当要电镀形成铼材质的金属线路时，种子层的材料是以铼为佳；当要电镀形成镍材质的金属线路时，种子层的材料是以镍为佳。
请参阅图2e所示，形成一光阻层210在种子层208上，此光阻层210为正光阻型式。如图2f所示，图案化此光阻层210形成多数开口212曝露出种子层208，在形成开口212的过程中是以一倍(1X)的曝光机(steppers)或扫描机(scanners)进行曝光显影，在此实施例的开口212具有一线圈形状。
请参阅图2g所示，电镀形成厚度介于1微米至50微米之间的一金属层214在开口212所曝露出的种子层208上，此金属层214较佳的厚度是介于2微米至30微米之间，此金属层214比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层。
如图2h所示，接着去除光阻层210，而所留下金属层214即呈现一线圈形状，请参阅图2i所示，此线圈形状的金属层214可作被动组件中的电感，当此线圈形状的金属层214通过电流时，即产生感应电动势，使保护层22下方的细线路层18感应。另外在此说明此线圈形状的金属层214在使用时(通入电流)，会产生大量的静电，大约为1500伏特(V)，因为聚合物层202及聚合物层204必须有一定程度的厚度，才能防止细线路层18及薄膜绝缘层16损坏。
如图2j所示，接着形成一光阻层216在金属层214及种子层208上；如图2k所示，同样利用一倍(1X)的曝光机(steppers)或扫描机(scanners)进行曝光显影，图案化此光阻层216，在光阻层216内形成多数开口218曝露出金属层214顶面。
如图2l所示，电镀形成厚度介于1微米至150微米之间的一金属层220在开口218内所曝露出的金属层214上，此金属层220较佳的厚度是介于2微米至30微米之间，此金属层220比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层，由上述金属材质所形成的金属层220较佳厚度可介于2微米至30微米之间。此外，金属层220除了上述所提的金属材质外也可使用焊料材料取代，此焊料材料为锡铅金属层、锡银金属层、锡银铜合金层、无铅焊料层。此金属层220若为焊料材质，则金属层220的较佳厚度是介于3微米至150微米之间。
如图2m所示，去除光阻层216；如图2n所示，利用含有碘的蚀刻液去除未在金属层214下的种子层208，例如碘化钾等蚀刻液，并再利用双氧水蚀刻去除未在金属层214下的黏着/阻障层206，其中去除黏着/阻障层206的方式分为干式蚀刻及湿式蚀刻，其中干式蚀刻使用高压氩气进行溅击蚀刻，而进行湿式蚀刻时若种子层208为金的种子层时，则可使用碘化钾溶液进行去除，若黏着/阻障层206为钛钨合金时，则可使用双氧水进行去除。
如图2o所示，形成一聚合物层222在金属层220及金属层214上，如图2p所示，利用蚀刻方式图案化此聚合物层222形成多数开口224曝露出金属层220，其中值得注意的是，当聚合物层222为感光材质时，则比如可以利用微影制作方法(photolithography process)，将聚合物层222图案化；当聚合物层222为非感光材质时，则比如可以利用微影蚀刻制作方法(photolithography process and etchingprocess)，将聚合物层222图案化并加热硬化。接着如图2q所示，切割此半导体基底10形成多数半导体组件226。
此外，另一值得注意的地方在于第一实施例中金属层214及金属层220材质及厚度上的变化，使得第一实施例后续的应用及结构型态有所不同。如图2r所示，当金属层220为一金层时，则可利用一打线制作方法形成一导线228在半导体组件226所曝露出的金属层220上，藉由此导线226使半导体组件226电连接至一外界电路，此外界电路为软版、半导体芯片、印刷电路板陶瓷基板或玻璃基板等。
请参阅图2s所示，例如当金属层220的厚度是介于10微米至30微米之间时，也就是金属层220是应用在凸块(bump)时，将图2n所示的结构藉由卷带自动贴合(Tape Automated Bonding；TAB)制作方法，使半导体组件226上的金属层220接合在一软性基板230上。在此实施例中金属层220及金属层214较佳材质分别为铜金属材质及金金属材质，当半导体组件226接合在软性基板230后，可再包覆一聚合物232以保护金属层220与软性基板230的接合处。
请参阅图2t所示，例如当金属层220是应用在凸块(bump)时，也可利用一异方性导电胶(ACF)234将半导体组件226上的凸块(金属层220)电性接合在一玻璃基板236上，此方式也就是玻璃覆晶封装(Chip-on-glass)，此COG技术是将IC芯片直接黏结在主动矩阵液晶显示器(LCD)边缘的制造方法，以提供更小的封装面积、更高的品质，并可改良坚固度，在此金属层220及金属层214较佳材质分别为铜金属材质及金金属材质。
请参阅图2u所示，例如当金属层220是应用在凸块(bump)时，同样也可利用异方性导电胶(ACF)234将半导体组件226上的凸块(金属层220)电性接合在一软板(film)238上，此方式也就是COF(chip on film)技术，主要应用以手机为主，或未来应用于PDP(电浆显示器)的驱动IC，及其它面积不大的LCD产品上。在此金属层220及金属层214较佳材质分别为铜金属材质及金金属材质。
请参阅图2v所示，例如当金属层220是应用在凸块(bump)时，且金属层220的材质为焊料时，比如锡铅金属层、锡银金属层、锡银铜合金层、无铅焊料等等，在进行切割半导体基底10的步骤前，则先进行再加热制作方法，使金属层220到达熔点而内聚成球形，之后再进行切割半导体基底10的步骤形成多数半导体组件226，接着以覆晶(Flip Chip，FC)方式接合在一外界电路板240上，接着可形成一聚合物层242在外界电路板240与半导体组件226之间以提供保护。
第二实施例
此实施例与第一实施例相似，不同点在于当金属层214的面积太小时，使覆盖在金属层220及金属层214上的聚合物层222进行微影蚀刻时，无法蚀刻出如此微细的开口，因此会形成如图3a所示的结构，使得金属层220及金属层214完全曝露在外，再进行加热使聚合物层222硬化，接着如图3b所示，切割此半导体基底10形成多数半导体组件226。接着使金属层220接合在外界电路板240上，接着同样形成聚合物层242在外界电路板240与半导体组件226之间以提供保护。
第三实施例
此实施例与第一实施例相似，不同点在于电镀形成一金属层220在开口218内的步骤及金属材质不同，如图4a所示，将第一实施例中在光阻层216的开口218内是先电镀形成厚度介于2微米至30微米之间的一镍金属层244，接着如图4b所示，再电镀形成厚度介于2微米至30微米之间的一金层246在镍金属层244上，接着如图4c所示，去除光阻层216；如图4d所示，利用含有碘的蚀刻液去除未在金属层214下的种子层208，例如碘化钾等蚀刻液，并再利用双氧水蚀刻去除未在金属层214下的黏着/阻障层206。
如图4e所示，形成一聚合物层248在金层246及金属层214上，如图4f所示，利用蚀刻方式图案化此聚合物层248形成多数开口250曝露出金层246，再进行加热使聚合物层248硬化，接着如图4g所示，切割此半导体基底10形成多数半导体组件226。其中图4e至图4g的详细制作方法与第一实施例相同，在此就不加以重复叙述。
如图4h所示，利用一打线制作方法形成一导线228在半导体组件226所曝露出的金层246上，藉由此导线228使半导体组件226电连接至一外界电路，此外界电路为软版、半导体芯片、印刷电路板陶瓷基板或玻璃基板等。其中金属层214较佳的材质为铜金属，与镍金属层244及金层246构成铜/镍/金层结构。此外另一值得注意的地方在于镍金属层244上除了可电镀形成金层246外，也可电镀一铂层(Pt)、钯层(Pd)、银层(Ag)等金属层取代。
第四实施例
此实施例与第一实施例相似，不同点在于图案化聚合物层222的步骤，请参阅图5a及图5b所示，在第一实施例中图案化聚合物层222仅是曝露出金属层220，而在此实施例中则是以蚀刻方式图案化此聚合物层222形成多数开口224同时曝露出金属层220及金属层214，如图5c所示，在进行完切割半导体基底10后产生多数半导体组件226，每一半导体组件226上的聚合物层222开口同时曝露金属层220及金属层214，当金属层214为金(Au)金属材质时，在聚合物层222开口所曝露的金属层214则可利用打线制作方法形成导线228电连接至外界电路，而曝露于外界的金属层220则可利用TAB、COG、COF及FC等技术接合在一外界基板上。
第五实施例
请参阅图6a所示，此实施例是由第一实施例图2h所发展而来，在第一实施例去除光阻层210后，形成厚度介于2微米至30微米之间的一聚合物层252在金属层214上，如图6b所示，利用蚀刻方式图案化此聚合物层252形成多数开口254曝露出未在金属层214下的种子层208及部分的金属层214，其中部分的聚合物层252仍包覆着金属层214，仅特定部分金属层214顶面曝露出，接着将此聚合物层252加热硬化，接着如图6c所示，去除种子层208及黏着/阻障层206，如第6d图所示，进行切割半导体基底10形成多数半导体组件226，并且藉由打线制作方法形成导线228在所曝露出的金属层214顶面上，使半导体组件226电连接至外界电路。
第六实施例
请参阅图7a所示，此实施例是由第五实施例的图6b发展而来，此实施例将包覆在金属层214的聚合物层252硬化，接着形成一光阻层256在金属层214及种子层208上，接着如图7b所示，利用微影蚀刻方式在光阻层256上形成多数开口258曝露出金属层214表面，如图7c所示，电镀形成一金属层260在开口258内，此金属层260的厚度是介于1微米至150微米之间，当金属层260的材质为金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层时，则金属层260较佳的厚度是介于2微米至30微米之间。若金属层260的材质为焊料时，比如是锡铅金属层、锡银金属层、锡银铜合金层、无铅焊料其中之一，则金属层260的厚度较佳是介于3微米至150微米之间。
如图7d所示，去除光阻层256，并去除种子层208及黏着/阻障层206，接着如图7e所示，切割此半导体基底10形成多数半导体组件226。
请参阅图7f所示，利用打线制作方法形成导线228在金属层260上，使半导体组件226电连接至外界电路上。如图7g所示，也可藉由卷带自动贴合(TapeAutomated Bonding；TAB)制作方法，使半导体组件226上的金属层260接合在一软性基板230上，如图7h所示，也可藉由玻璃覆晶封装(Chip-on-glass)技术，利用异方性导电胶(ACF)234将半导体组件226上的金属层260电性接合在一玻璃基板236上，如图7i所示，同样也可藉由COF(chip on film)技术，利用异方性导电胶(ACF)234将半导体组件226上的金属层260电性接合在软板238上，如图7j所示，当金属层260材质为焊料时，则在进行切割半导体基底10的步骤前，则先进行再加热制作方法，使金属层260到达熔点而内聚成球形，之后再进行切割半导体基底10的步骤形成多数半导体组件226，接着如图7k所示，以覆晶(Flip Chip，FC)方式接合在外界电路板240上，接着可形成聚合物层242在外界电路板240与半导体组件226之间以提供保护。
第七实施例
请参阅图8a所示，此实施例与第五实施例相似，同样是因金属层214的面积太小时，使覆盖在金属层214及种子层208上的聚合物层252进行微影蚀刻时，无法蚀刻出如此微细的开口，因此在微影蚀刻时会形成如图8a所示的结构，接着将此聚合物层252进行加热硬化，接着如图8b所示，形成一光阻层262在聚合物层252及种子层208上，如图8c所示，利用微影蚀刻方式使光阻层262形成多数开口264曝露出金属层214，如图8d所示，电镀形成厚度介于1微米至150微米之间的一金属层266在开口264内，此金属层266的材质为金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层时，则金属层266较佳的厚度是介于2微米至30微米之间。若金属层266的材质为焊料时，比如是锡铅金属层、锡银金属层、锡银铜合金层、无铅焊料其中之一，则金属层266的厚度较佳是介于3微米至150微米之间。
如图8e及图8f所示，去除光阻层262，并去除种子层208及黏着/阻障层206，接着切割此半导体基底10形成多数半导体组件226，而每一半导体组件226皆可使用打线制作方法、卷带自动贴合(Tape Automated Bonding；TAB)制作方法、玻璃覆晶封装(Chip-on-glass)技术、COF(chip on film)技术及覆晶(Flip Chip，FC)技术连接至外界电路上，其中接合的过程己在第一实施例中解说，在此就不重复说明。
第八实施例
此实施例是由第五实施例的图6a发展而来，请参阅图9a所示，其中在图6b蚀刻方式图案化此聚合物层252时，形成多数开口254曝露出未在金属层214下的种子层208及部分的金属层214，接着将此聚合物层252进行加热硬化，接着如图9b所示，形成一光阻层268在聚合物层252、金属层214及种子层208上，如图9c所示，利用微影蚀刻方式使光阻层268形成多数开口270曝露出部分的金属层214，其中值得注意的地方在于光阻层268同时将部分曝露的金属层214予以覆盖，与第七实施例不同，如图9d所示，电镀形成厚度介于1微米至150微米之间的一金属层272在开口270内，此金属层272的材质及厚度如上述第七实施例中的金属层266一样，在此就不加以重复解说。
如图9e及图9f所示，去除光阻层262，并去除种子层208及黏着/阻障层206，并且进行半导体基底10的切割步骤，形成多数半导体组件226，而半导体组件226上的金属层272可藉由则可利用TAB、COG、COF及FC等技术接合在一外界基板上，而当金属层214为金(Au)金属材质时，在聚合物层252开口所曝露的金属层214则可利用打线制作方法形成导线228电连接至外界电路。
第九实施例
此实施例是由第一实施例中的图2o所发展而来，请参阅图10a所示，其中在形成一聚合物层222在金属层220及金属层214上后，进行加热使聚合物层222硬化，如图10b所示，利用化学机械研磨(CMP)进行一研磨的步骤，使聚合物层222厚度减少直到金属层220露出，接着溅镀厚度介于400埃至7000埃一黏着/阻障层274在聚合物层222及金属层220上，此黏着/阻障层274的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一，接着如图10c所示，再溅镀形成一种子层276在黏着/阻障层274上，如图10d所示，形成一光阻层278在种子层276上，如图10e所示，图案化此光阻层278形成多数开口280曝露出种子层276，在形成开口280的过程中是以一倍(1X)的曝光机(steppers)或扫描机(scanners)进行曝光显影，在此实施例的开口280具有一线圈形状。
接着如图10f所示，电镀形成厚度介于1微米至50微米之间的一金属层282在开口280所曝露出的种子层276上，此金属层282较佳的厚度是介于2微米至30微米之间，此金属层282比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层。如图10g所示，接着去除光阻层278，而所留下金属层282即呈现一线圈形状。
如图10h所示，接着去除未在金属层282下方的种子层276及黏着/阻障层274，如图10i所示，形成一聚合物层284在金属层282及聚合物层222上；如图10j所示，利用蚀刻方式蚀刻此聚合物层284，使聚合物层284形成多数开口286曝露出金属层282，如图10k所示，进行切割半导体基底10，形成多数半导体组件226，接着如图10l所示，利用打线制作方法形成导线228在曝露出金属层282上，藉由导线228使半导体组件226电连接至一外界电路上。
第十实施例
此实施例的结构与上述九种实施例不同，但皆有应用到连续电镀形成金属层的概念，其中上述九种实施例皆是以被动组件中的电感(线圈)型式为例，此实施例则是以重配置线路(RDL)为实施例。
请参阅图11a所示，在完成此保护层22后，接着形成厚度介于3微米至50微米之间的一聚合物层288在此保护层22上，此聚合物层288具有絶缘功能，且此聚合物层288的材质是选自材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide，PI)、苯基环丁烯(benzo-cyclo-butene，BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料。而此聚合物层288主要是利用旋涂方式设置，另外也可利用热压合干膜方式、网版印刷方式进行，接着如图11b所示，利用蚀刻方式对此聚合物层288进行图案化，而形多数开口290曝露出半导体基底30上的接垫24。其中值得注意的是，当聚合物层288为感光材质时，则比如可以利用微影制作方法(photolithography process)，将聚合物层288图案化；当聚合物层288为非感光材质时，则比如可以利用微影蚀刻制作方法(photolithography process and etching process)，将聚合物层288图案化。
并且将图案化的聚合物层288后，可利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度，以硬化(curing)聚合物层288，硬化后的聚合物层288在体积上会呈现缩小的情形，且聚合物层288含水率小于1％，此含水率是将聚合物层288置放在温度介于摄氏425度至450度下时，其重量变化率小于1％。
如图11c所示，以溅镀方式形成厚度介于400埃至7000埃之一黏着/阻障层294及一种子层296(Adhesion/Barrier/seed layer)在聚合物层288及接垫24上，其中此黏着/阻障层294的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一。
接着如图11d所示，形成一图案化光阻层298在位于此黏着/阻障层294上的种子层296上，此图案化光阻层298具有多数开口300曝露出部分的位在黏着/阻障层294上的种子层296，在形成开口300的过程中比如是一倍(1X)的曝光机(steppers)或扫描机(scanners)，且此图案化光阻层298为正光阻型式。
如图11e所示，接着电镀形成厚度介于1微米至50微米之间的一金属层302在开口300所曝露出的种子层296上，此金属层302较佳的厚度是介于2微米至30微米之间，使金属层302电连接至细联机结构14，此金属层302比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层。
接着如图11f所示，去除此图案化光阻层298，即形成一重配置线路层304，值得注意的特点在于此重配置线路层304主要是将金属层302形成在开口290上及延伸至部分的聚合物层288上，并不是单纯形在开口290上，而所延伸的金属层302上则有利于后续的线路的设置。
如图11g所示，接着形成一图案化光阻层306在此重配置线路层304上及位在黏着/阻障层294上的种子层296上，此图案化光阻层306的多数开口308曝露出此重配置线路层304。
接着如图11h所示，电镀形成厚度介于1微米至20微米之间的一金属层310在此开口308内，且此金属层310的最大横向寛度是介于3微米至50微米，此金属层310的材质的材质选自金、铜、银、钯、铂、铑、钌、铼或镍其中之一或所组成的群组的至少其中之一，此金属层310较佳的厚度是介于2微米至10微米之间。
其中值得注意的是金属层310的材质若是铜金属时，则重配置线路层304较佳的顶层金属材质为铜金属；金属层310的材质若是银金属时，则重配置线路层304较佳的顶层金属材质为银金属；金属层310的材质若是钯金属时，则重配置线路层304较佳的顶层金属材质为钯金属；金属层310的材质若是铂金属时，则重配置线路层304较佳的顶层金属材质为铂金属；金属层310的材质若是铑金属时，则重配置线路层304较佳的顶层金属材质为铑金属；金属层310的材质若是钌金属时，则重配置线路层304较佳的顶层金属材质为钌金属；金属层310的材质若是铼金属时，则重配置线路层304较佳的顶层金属材质为铼金属；金属层310的材质若是镍金属时，则重配置线路层304较佳的顶层金属材质为镍金属。
如图11i所示，接着去除图案化光阻层306，并利用双氧水蚀刻去除未在重配置线路层304下的黏着/阻障层294，其中除了利用双氧水去除黏着/阻障层294外，并利用含有碘的蚀刻液去除种子层296，例如碘化钾等蚀刻液。
如图11j所示，在去除金属层302下的黏着/阻障层294及种子层296后，以旋涂方式形成一聚合物层312在此半导体基底10上将金属层310覆盖，此聚合物层312的材质是选自材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide，PI)、苯基环丁烯(benzo-cyclo-butene，BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料。
请参阅图11k所示，利用烘烤加热、微波加热、红外线加热其中之一方式进行加热使聚合物层312硬化，并利用化学机械研磨(CMP)方式使金属层310曝露出。
如图11l所示，接着溅镀厚度介于400埃至7000埃一黏着/阻障层314在聚合物层312及金属层310上，此黏着/阻障层314的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一，接着如图11m所示，再溅镀形成一种子层316在黏着/阻障层314上，如图11n所示，形成一光阻层318在种子层316上，如图11o所示，图案化此光阻层318形成多数开口320曝露出种子层316，在形成开口320的过程中是以一倍(1X)的曝光机(steppers)或扫描机(scanners)进行曝光显影。
接着如图11p所示，电镀形成厚度介于1微米至50微米之间的一金属层322在开口320所曝露出的种子层316上，此金属层322较佳的厚度是介于2微米至30微米之间，此金属层322比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构，或是由上述金属材质所组成的复合层。如图11q所示，接着去除光阻层318，而所留下金属层322。
如图11r所示，再形成一图案化光阻层324在金属层322上，图案化光阻层324的开口曝露出金属层322，如图11s所示，电镀形成一金属层326在图案化光阻层324的开口内，如图11t所示，去除图案化光阻层324，并形成另一图案化光阻层328，此图案化光阻层328的厚度比原有的图案化光阻层324高至少3微米以上，此图案化光阻层328的多数开口曝露出金属层322，如图11u所示，形成一金属层330在图案化光阻层328的开口内，如图11v所示，去除此图案化光阻层328，并去除未在金属层322下的黏着/阻障层314及种子层316。
如图11w所示，以旋涂方式形成一聚合物层332覆盖在金属层330及聚合物层312上，如图11x所示，利用微影蚀刻方式图案化聚合物层332，形成多数开口334曝露出金属层326及金属层330，如图11y所示，进行加热使此聚合物层332硬化，接着进行切割半导体基底10步骤，形成多数半导体组件226，接着如图11z所示，利用打线制作方法形成导线228在金属层326上，而金属层330则可利用TAB、COG、COF及FC等技术接合在一外界基板上。
本发明在半导体基底(晶圆)上藉由连续电镀的方式，产生了许多不同型态的连接结构，形成各种不同对外的接点结构，比如形成接垫(pad)、凸块(bump)等，此接垫及凸块皆可透过打线或异方式导电胶电连接至外界电路上，使半导体组件的应用更具多元化连接方式。
以上所述是藉由实施例说明本发明的特点，其目的在使熟悉该技术普通一般技术人员能暸解本发明的内容并据以实施，而非限定本发明专利的权利要求保护范围，故，凡其它未脱离本发明所揭示的精神所完成的等效修饰或修改，仍应包含在以下所述的权利要求范围中。

Claims (26)

1.一种连续电镀制作线路组件的方法，其特征在于，其步骤包括：
提供一半导体基底、一细联机结构、一第一线圈及一保护层，其中该细联机结构位在该半导体基底上，该保护层位在该细联机结构上，该第一线圈位在该保护层上，该第一线圈具有一接垫位在该保护层上；
形成一第一图案化光阻层在该第一线圈及该保护层上，该第一图案化光阻层具有至少一开口暴露出该接垫；
形成一第一金属层在该第一图案化光阻层的该开口内；以及
去除该第一图案化光阻层。
2.如权利要求1所述的连续电镀制作线路组件的方法，其特征在于，该形成该保护层的步骤包括沉积厚度介于1000埃至15000埃之间的氮硅化合物层、磷硅玻璃层、氧硅化合物层及氮氧硅化合物层其中之一或组成。
3.如权利要求1所述的连续电镀制作线路组件的方法，其特征在于，该形成该第一线圈步骤前更形成厚度介于2微米至50微米之间的聚醯亚胺化合物层、苯基环丁烯化合物层及环氧树脂层其中之一在该保护层上。
4.如权利要求1所述的连续电镀制作线路组件的方法，其特征在于，该提供该第一线圈的步骤包括：
形成一第二金属层在该保护层上；
形成一第二图案化光阻层在该第二金属层上，该第二图案化光阻层的多数开口暴露出该第二金属层；
形成一第三金属层在该第一图案化光阻层的该开口内，该第一图案化光阻层的该开口包括一线圈形状；以及
去除该第二图案化光阻层。
5.如权利要求4所述的连续电镀制作线路组件的方法，其特征在于，该形成该第二金属层步骤包括溅镀厚度介于400埃至7000埃的钛钨合金层、钛金属层、氮化钛层、钽金属层、氮化钽层、铬金属层、铬铜合金层其中之一或组成在该保护层上。
6.如权利要求4所述的连续电镀制作线路组件的方法，其特征在于，该形成该第三金属层的步骤包括形成厚度介于1微米至50微米之间的金金属层、铜金属层、银金属层、镍金属层其中之一。
7.如权利要求1所述的连续电镀制作线路组件的方法，其特征在于，该去除该第一图案化光阻层的步骤后更包括形成一第二图案化聚合物层在该半导体基底及该第一线圈上，该第二图案化聚合物层的开口暴露出该第一金属层。
8.如权利要求7所述的连续电镀制作线路组件的方法，其特征在于，该形成该第二图案化聚合物层的步骤包括形成厚度介于2微米至50微米之间的聚醯亚胺化合物层、环氧树脂层或苯基环丁烯化合物层。
9.如权利要求1所述的连续电镀制作线路组件的方法，其特征在于，该形成该第一金属层的步骤包括形成厚度介于1微米至50微米之间的金金属层、铜金属层、银金属层、镍金属层及含锡的焊料层其中之一。
10.一种线路组件结构，其特征在于，包括：
一半导体基底；
一保护层，位在该半导体基底上；
一第一图案化线路层，位在该保护层上；
一第一图案化聚合物层，覆盖在该第一图案化线路层及该保护层上，该第一图案化聚合物层的开口暴露出该第一图案化线路层；
一第一金属层，位在该第一图案化聚合物层的开口内；以及
一第一线圈，位在该第一图案化聚合物层上并电连接至该第一金属层。
11.如权利要求8所述的线路组件结构，其特征在于，该保护层的材质是选自氮硅化合物、磷硅玻璃、氧硅化合物、氮氧硅化合物其中之一或及其组成。
12.如权利要求10所述的线路组件结构，其特征在于，更包括一第二聚合物层位在该保护层与该第一图案化线路层之间，该第二聚合物层的材质是选自厚度介于2微米至50微米的聚醯亚胺化合物、苯基环丁烯化合物、聚对二甲苯类高分子、环氧树脂、焊罩材料或多孔性介电材料其中之一或及其组成。
13.如权利要求10所述的线路组件结构，其特征在于，更包括一第二金属层位在该第一图案化线路层与该第二聚合物层之间，该第二金属层是选自厚度介于400埃至7000埃的钛钨合金层、钛金属层、氮化钛层、钽金属层、氮化钽层、铬金属层、铬铜合金层其中之一或及其组成。
14.如权利要求10所述的线路组件结构，其特征在于，该第一图案化线路层是选自厚度介于1微米至50微米的金层、铜层、银层、镍层其中之一或及其组成。
15.如权利要求10所述的线路组件结构，其特征在于，该第一金属层是选自厚度介于1微米至50微米的金层、铜层、银层、镍层、钯层、铂层其中之一或及其组成。
16.如权利要求10所述的线路组件结构，其特征在于，该第一图案化聚合物层是选自厚度介于2微米至50微米之间的聚醯亚胺化合物、苯基环丁烯化合物、聚对二甲苯类高分子、环氧树脂、焊罩材料或多孔性介电材料其中之一或及其组成。
17.如权利要求10所述的线路组件结构，其特征在于，该第一图案化线路层是选自为金属线圈、连接线路层、重配置线路层其中之一。
18.如权利要求10所述的线路组件结构，其特征在于，该第一线圈是选自厚度介于1微米至50微米的金层、铜层、银层、镍层其中之一或及其组成。
19.一种线路组件结构，其特征在于，包括：
一半导体基底；
一细联机结构，位在该半导体基底上；
一保护层，位在该细联机结构上；
一金属线路层，位在该保护层上，该金属线路层具有一接垫；
一金层，位在该接垫上；以及
利用卷带自动贴合或玻璃覆晶封装或薄膜覆晶封装的技术使该金层接合在一基板上。
20.如权利要求19所述的线路组件结构，其特征在于，该保护层的材质是选自氮硅化合物、磷硅玻璃、氧硅化合物、氮氧硅化合物其中之一或及其组成。
21.如权利要求19所述的线路组件结构，其特征在于，更包括一第二聚合物层位在该保护层与该金属线路层之间，该第二聚合物层的材质是选自厚度介于2微米至50微米的聚醯亚胺化合物、苯基环丁烯化合物、聚对二甲苯类高分子、环氧树脂、焊罩材料或多孔性介电材料其中之一或及其组成。。
22.如权利要求19所述的线路组件结构，其特征在于，更包括一第二金属层位在该金属线路层与该第二聚合物层之间，该第二金属层是选自厚度介于400埃至7000埃的钛钨合金层、钛金属层、氮化钛层、钽金属层、氮化钽层、铬金属层、铬铜合金层其中之一或及其组成。
23.如权利要求19所述的线路组件结构，其特征在于，该金属线路层是选自厚度介于1微米至50微米的金层、铜层、银层、镍层其中之一或及其组成。
24.如权利要求19所述的线路组件结构，其特征在于，该金层为厚度介于0.1微米至50微米之间。
25.如权利要求19所述的线路组件结构，其特征在于，更包括一第一聚合物层位在该软性基板与该金属线路层之间，用以包覆该金层与该基板的接合处，该第一聚合物层的材质是选自聚醯亚胺化合物、苯基环丁烯化合物、聚对二甲苯类高分子、环氧树脂、焊罩材料或多孔性介电材料其中之一或及其组成。
26.如权利要求19所述的线路组件结构，其特征在于，该金属线路层是选自为金属线圈、连接线路层、重配置线路层其中之一或及其组成。
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US7960269B2 (en) 2011-06-14
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