CN1892998A - 形成半导体结构或元件的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 88
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000000137 annealing Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 90
- 239000011435 rock Substances 0.000 claims description 68
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 230000008569 process Effects 0.000 claims description 28
- 238000002425 crystallisation Methods 0.000 claims description 21
- 230000008025 crystallization Effects 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 230000002285 radioactive effect Effects 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 230000037230 mobility Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 206010050031 Muscle strain Diseases 0.000 description 2
- 208000010040 Sprains and Strains Diseases 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 229910052704 radon Inorganic materials 0.000 description 2
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 2
- 230000007115 recruitment Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- MQTVGBAYEOULPQ-UHFFFAOYSA-N [Xe].[Xe] Chemical compound [Xe].[Xe] MQTVGBAYEOULPQ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/8232—Field-effect technology
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- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
本发明提供一种形成半导体结构或元件的方法。先提供一基底。一栅电极接着形成于该基底上。一源/漏极区形成于该基底。一非晶区形成于该栅电极与该源/漏极区的一上部分。一应力盖层形成于该非晶区上。对该非晶区进行极速退火,并使该非晶区结晶。该应力盖层大致全部移除。本发明所述形成半导体结构或元件的方法,可提供金属氧化物半导体元件的沟道区适当的应力。
Description
技术领域
本发明是大致关于金属氧化物半导体(metal-oxide-semiconductor,MOS)元件,尤指具有应力的沟道区的MOS元件与其相关制程。
背景技术
VLSI电路的缩小化是一个半导体业界不断追求的目标。当电路变的更小更快,元件的驱动电流的改善也更显的重要。元件电流大致上跟栅极的长度、栅极电容、还有载流子移动率(carriermobility)相关。较短的多晶硅栅极长度、较大的栅极电容、与较高的载流子移动率等都可以改善元件电流的表现。栅极长度的缩短可以透过元件尺寸的缩小而达成,这是业界持续努力的目标。栅极电容的增大也会随着栅介电层的变薄、栅介电常数的增加等来达成。为了改善元件电流的表现,也有许多的方法来增加载流子移动率。
在各种增加载流子移动率的方法当中,有一种已知的方法是形成一带有应力(strain or stress)的硅沟道。应力可以增强电子或是空穴的移动率。所以,MOS元件的特性就可以透过带有应力的沟道来改善。这样的技术,就可以在固定栅极长度的条件下,同时也没有增加电路设计的复杂度下,改善元件的特性。
当硅被施加压应力时,常温下、共平面(in-phase)的电子移动率就可以显著的增加。一种提供这样应力的方法是透过生长一比例渐进的SiGe外延层来达成。这样的比例渐进的SiGe外延层可以是一无应力的(relaxed)SiGe层。一层硅层接着形成在此无应力的SiGe层上。这样,此硅层中就会有应力,然后,MOS元件才形成在此硅层上。因为SiGe的晶格常数(lattice constant)大于硅的晶格常数,所以此硅层就会有双轴应力(biaxial tension),而其中的载流子就可以呈现出在应力下时的移动率来。
应力在一个元件中,可以依照方向的不同,有三个部分:平行于MOS元件沟道长度的部分,平行于MOS元件沟道宽度的部分,以及垂直于沟道平面的部分。如果应力的方向是平行沟道长度或是宽度,这样的应力称为“共平面”应力。研究有发现,属于共平面张(tensile)应力的双轴应力可以改善NMOS的效能,而平行于沟道方向的压(compressive)应力可以改善PMOS的效能。
应力也可以透过在MOS元件上形成一应力盖层(strainedcapping layer)来实现。譬如说,一接触蚀刻停止(contact etchstop,CES)层就可以当这样的应力盖层。当一应力盖层沉积时,因为应力盖层跟底下的物质之间晶格间隔距离的差异,为了要尝试去拉齐彼此的晶格,共平面应力就会因而产生。图1显示了具有一应力沟道区的一传统MOS元件。应力盖层,如同栅侧壁子9与CES层14所示,可以对源/漏极区12(包含LDD区15)引入应力,而这样的应力可以导入沟道区11中。所以沟道区11中的载流子移动率就可以改善。
传统形成应力盖层的方法有不少的缺点,而且,其效果也受限于应力盖层本身的特性。譬如说,应力盖层的厚度不可以太厚,否则将增大后续填缝技术的困难度。因此,应力盖层所可以提供的应力就相当的有限。此外,一旦应力盖层移除了,所提供的应力往往就跟着消失了。
因此,要如何提供MOS元件的沟道区适当的应力,就成了一个迫切祈求的目标。
发明内容
为解决现有技术中的上述问题,本发明提供一种形成半导体结构的方法。先提供一基底。一栅电极接着形成于该基底上。一源/漏极区形成于该基底。一非晶(amorphous)区形成于该栅电极与该源/漏极区的一上部分。一应力盖层形成于该非晶区上。对该非晶区进行极速退火(super annealing),并使该非晶区结晶。该应力盖层大致全部移除。
本发明所述的形成半导体结构的方法,该非晶区是形成于该源/漏极区中。
本发明所述的形成半导体结构的方法,形成该源/漏极区的步骤是以一离子注入制程进行,且该离子注入制程形成该非晶区。
本发明所述的形成半导体结构的方法,形成该非晶区的步骤是包含有一预非晶化注入。
本发明所述的形成半导体结构的方法,该栅电极包含有硅,且该非晶区是位于该栅电极中。
本发明所述的形成半导体结构的方法,于移除全部的该应力盖层的步骤前,另包含有一额外的退火步骤。
本发明所述的形成半导体结构的方法,另包含有:形成一栅侧壁子于该栅电极的一侧壁;形成一金属硅化物区于该源/漏极区;形成一接触蚀刻停止层于该源/漏极区与该栅电极上;以及形成一层间介电(inter layer dielectric,ILD)层于该接触蚀刻停止层上。
本发明亦提供一种形成一半导体元件的方法。先提供一基底,具有一第一元件区。对该第一元件区中的一源/漏极区进行离子注入。形成一应力盖层于该源/漏极区上。对该源/漏极区进行极速退火(super annealing),并使该源/漏极区结晶。最后,大致移除全部的该应力盖层。
本发明所述的形成半导体元件的方法,该极速退火是以一高能量的放射源对该基底曝照。
本发明所述的形成半导体元件的方法,该极速退火的处理时间是介于约1皮秒到约1秒之间。
本发明所述的形成半导体元件的方法,另包含有预非晶化该源/漏极区的一上部分。
本发明所述的形成半导体元件的方法,于移除全部的该应力盖层的步骤前,另包含有一额外的退火步骤。
本发明所述的形成半导体元件的方法,另包含有:形成一多晶硅栅电极层于该第一元件区;预非晶化该多晶硅栅电极层的一上部分;形成该应力盖层于该多晶硅栅电极层上;对该多晶硅栅电极层进行极速退火,并使该多晶硅栅电极层结晶;以及于大致移除全部的该应力盖层的步骤后,图案化该多晶硅栅电极层,以形成一栅电极。
本发明所述的形成半导体元件的方法,另包含有:形成一多晶硅栅电极层于该第一元件区;图案化该多晶硅栅电极层,以形成一栅电极;预非晶化该栅电极的一上部分;形成该应力盖层于该栅电极上;于大致移除全部的该应力盖层的步骤前,对该栅电极进行极速退火,并使该栅电极结晶。
本发明所述的形成半导体元件的方法,于大致移除全部的该应力盖层的步骤后,另包含有:形成一栅侧壁子于该栅电极的一侧壁。
本发明所述的形成半导体元件的方法,于大致移除全部的该应力盖层的步骤前,另包含有:形成一栅侧壁子于该栅电极的一侧壁。
本发明所述的形成半导体元件的方法,该基底另包含有一第二元件区,且该第二元件区于该源/漏极区进行该离子注入步骤、以及该极速退火与重结晶步骤时,该第二元件区是被遮住。
本发明还提供一种形成半导体结构的方法。先提供一基底,具有一第一以及一第二元件区。形成一第一栅介电层于该第一元件区的该基底上,并形成一第一栅电极于该第一栅介电层上。形成一第二栅介电层于该第二元件区的该基底上,并形成一第二栅电极于该第二栅介电层上。形成一第一源/漏极区于该第一元件区。形成一第二源/漏极区于该第二元件区。预非晶化(pre-amorphizating)该第一源/漏极区以及该第一栅电极。形成一第一应力盖层于该第一源/漏极区以及该第一栅电极上。对该第一源/漏极区以及该第一栅电极进行极速退火(super annealing),并使该第一源/漏极区以及该第一栅电极结晶。并移除该第一应力盖层。
本发明所述的形成半导体结构的方法,于对该第一源/漏极区以及该第一栅电极进行该极速退火以及该结晶之前,另包含有一步骤,遮住该第二元件区。
本发明所述的形成半导体结构的方法,另包含有:预非晶化该第二源/漏极区以及该第二栅电极;形成一第二应力盖层于该第二源/漏极区以及该第二栅电极上,其中,该第二应力盖层与该第一应力盖层的应力不同;对该第二源/漏极区以及该第二栅电极进行极速退火,并使该第二源/漏极区以及该第二栅电极结晶;以及移除该第二应力盖层。
本发明所述形成半导体结构或元件的方法,可提供MOS元件的沟道区适当的应力。
附图说明
图1显示了具有一应力沟道区的一传统MOS元件;
图2显示将实施本发明的一基底与其上的栅极结构;
图3显示栅侧壁子(gate spacer)106与206的形成;
图4显示源/漏极区108与208的形成;
图5A显示一掩膜层222形成,盖在第二元件区200上;
图5B显示第二元件区200中,曝露的基底40的上部分220跟栅电极204的上部分224变成非晶的状态;
图6显示了应力盖层126的形成;
图7表示一极速退火制程;
图8显示应力盖层126的移除后的结构图;
图9显示了在金属硅化物区146与246、接触蚀刻停止层148、以及层间介电层150形成之后的结构;
图10显示一种在多晶硅沉积之后到图案化之前形成应力的实施例;
图11显示应力形成在第一栅结构102图案化之后,但是在栅侧壁子形成之前;
图12显示应力是产生并存放在栅侧壁子106形成之后。
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:
本发明的实施例显示于图2到图9中。图10到图12也讨论了许多实施例的变化。在这些不同的图与实施例当中,一样的符号将用在一样的零件上。
请看图2,其中有显示了一基底40。基底40可以用一般熟知的基底材料,譬如说硅、SiGe、长在SiGe上带有应力的硅、绝缘层上覆硅(silicon on insulator,SOI)、绝缘层上覆硅锗(silicongermanium on insulator,SGOI)、绝缘层上覆锗(germanium oninsulator,SGOI)等等。这样的基底40可以带有第一元件区100跟第二元件区200,用来形成不一样的逻辑元件。于一实施例中,元件区100跟200的其中之一用来形成PMOS;另一个用来形成NMOS。于其他一实施例中,元件区100跟200的其中之一是核心区(core region),用来形成核心元件(core device);另一个是周边(periphery)区,用来形成输入/输出(Input/output)元件。
第一元件区100中形成了一第一栅结构102,具有一栅介电层103以及一栅电极104。第二元件区200中形成了一第二栅结构202,具有一栅介电层203以及一栅电极204。如同一般所熟知的,为了要形成这些栅结构,一栅介电层先形成在基底40上,然后一栅电极层接着形成在栅介电层上。在较佳的实施例中,栅电极层是多晶硅。在其他的实施例中,也可以使用其他的导电物,像是金属、或是金属硅化物等。栅介电层跟栅电极层接着可以被图案化,来形成栅电极104与204、跟栅介电层103与203。轻掺杂源/漏极(lightly-doped source/drain,LDD)区105跟205可以接着用注入适当的杂质而形成。
图3显示栅侧壁子(gate spacer)106与206的形成。为了要形成这样的栅侧壁子,一般是先全面的沉积一侧壁子层在先前所形成的结构上。这侧壁子层可的材料可以是SiN、SiC、氮氧化硅(oxynitride)、氧化硅(oxide)等等,而且可以用传统的沉积方法形成,譬如等离子辅助化学气相沉积(plasma enhanced chemicalvapor deposition,PECVD),或是溅镀(sputter)的方法等。侧壁子的成形,可以用非等向性蚀刻,移除掉在垂直表面上的侧壁子层。
图4显示源/漏极区108与208的形成。源/漏极区108与208的表面可能比基底40的表面低或是高,低的话可以用蚀刻的技术,高的话可以用外延成长的技术,相对应后续形成的应力层也会变低或是变高。在一例子中,源/漏极区108与208是以离子注入的方式,将杂质注入基底40中而形成。栅侧壁子106以及206用来当作掩膜,所以源/漏极区108与208的边缘会跟栅侧壁子106以及206大致切齐。栅电极104与204最好也一起被离子注入,用以降低其电阻。这样的离子注入过程会导致源/漏极区108与208的晶格结构遭受破坏,所以会形成一非晶硅(amorphous)结构。
一掩膜层222接着形成,盖在第二元件区200上,如同图5A所示。在较佳实施例中,掩膜层222可以是一光致抗蚀剂层。在其他可能的实施例中,掩膜层222可能是一光致抗蚀剂层、一抗反射(anti-reflect coating,ARC)层、一硬掩膜层或者上述的组合层。
接着实施一预非晶化注入(pre-amorphizationimplantation,PAI)步骤,以箭头125表示。在较佳实施例中,注入物可以是硅或是锗。在其他的实施例中,惰性气体,像是氖(neon)、氩(argon)、氙(xenon)、以及氡(radon)等都可以使用。这样的PAI可以破坏基底40的晶格结构,同时预防后续的注入杂质因为沟道(channeling)效应而穿过晶格中的间隙跑到太深的地方。至少,被PAI后,曝露的基底40的上部分120跟栅电极104的上部分124会变成非晶硅(amorphous)的状态。此非晶化注入可选择做或是不做,其目的在于增加非晶化的程度以加强后续应力调变的效果,若之前的离子注入步骤已能达到足够的非晶化,那么此步骤可不用做。上部分120的深度最好大于20纳米(nm)。然后,掩膜层222可以去除。
在另一个实施例中,如同图5B所示,掩膜层222并没有形成,所以,在第二元件区200中,曝露的基底40的上部分220跟栅电极204的上部分224会变成非晶硅(amorphous)的状态。
图6显示了应力盖层126的形成。取决于所要形成的MOS元件的种类,可以选用适当的材料,来提供张应力或是压应力给元件中的沟道区。这样的材料可以是SiN、氮氧化硅(oxynitride)、氧化硅(oxide)、SiGe、SiC、或是以上材料的组合等等。在应力盖层跟基底40之间可以形成一缓冲(buffer)层(未显示)。缓冲层可以是一氧化硅层,当稍后去除应力盖层时,可以作为蚀刻停止层。譬如说,当应力盖层是SiN时,之后可以用H3PO4去除,氧化硅的缓冲层就可以保护硅基底免于侵蚀的损害。
在较佳实施例中,应力盖层126可以是单一的一层。在其他实施例中,可以是有多层组合在一起的复合夹层结构。在更其他实施例中,应力盖层126可以有一第一部分1261在第一元件区100中,有第二部分1262在第二元件区200中,且第一部分1261跟第二部分1262所用的材料或形成的方法不一样,所以具有不同的内在应力。
请见图7,其中的箭头127代表了一极速退火制程。处理方式可以是以一高能量的放射源,譬如激光或是闪光灯,在很短的时间内,来对基底40曝照。基底40上的物品,将会因为温度的急速上升,而被热退火处理。该放射源的波长可以介于一纳米(nm)到一毫米(mm)之间。透过波长的选取,就可以控制基底40被热退火处理的深度。一般而言,波长越长,被热退火处理的深度越深。被热退火处理的深度最好大约大于200nm,而且,最好是比被预非晶化的上部分120、124的厚度来的大。热退火处理时间最好介于约1皮秒(pico-second)到约1秒(second)之间。热退火处理温度最好大约高于1000℃,可以透过调整高能量的放射源的能量来控制。在其他实施例中,此极速退火制程包含有一快速退火(flashanneal)。
一掩膜层229可以选择性地形成,把第二元件区200遮住,所以就仅有第一元件区100被极速退火制程处理。极速退火制程的能量会被掩膜层229所反射或是吸收,所以第二元件区200就免于极速退火制程处理。
极速退火制程可以用来调整应力盖层126中的内在应力。一般来说,当应力盖层126被极速退火制程热处理后,其中的应力应该会往张应力(tensile)方向变大。实验显示了应力的增加量跟极速退火制程的能量基本上是呈现正相关:能量越高,应力增加量越大。因此,可以通过不同能量的极速退火制程,来调整应力盖层126其中的内在应力,以得到不同的值。
极速退火制程也使被预非晶化的材料得以重新结晶。当被预非晶硅(amorphous)的上部分120、124重新结晶时,周遭的环境将会影响其结晶结构。譬如说,被预非晶硅(amorphous)的上部分120在重新结晶后的结晶结构,将会受到应力盖层126、栅侧壁子106以及基底40上的其它零件所影响。
在应力盖层126具有不同的区域1261跟1262(其中具有不同的内在应力)时,当应力盖层126移除后,在源/漏极区108与208中以及在栅电极104与204中的应力将会不同。所以,在第一元件区100跟第二元件区200中的MOS元件的沟道区,也会产生不同的应力。
较佳实施例可以另外包含一些退火制程,像是炉管退火(furnace anneal)、快速退火(rapid thermal anneal,RTA)、峰值退火(spike anneal)、等等。额外的退火制程可以让被预非晶化的上部分120、124重新结晶的更完整。
内含有应力的应力盖层126接着就移除,如图8所示。去除的方法可以用干蚀刻或是湿蚀刻。因为,被预非晶硅(amorphous)的上部分120、124已经重新结晶了,至少部分的应力盖层126中之内在应力就可以被“存储”起来,所以,原本应力盖层126给予MOS元件的沟道区的应力也还是会留下一些。这样应力会遗留下来的一种可能的原因是因为,上部分120、124中的应力依然受到尚未移除的环境所影响。
较佳实施例中,应力盖层126大致上被完全移除。在其他的实施例中,一小部分的应力盖层126被遗留下来而没有去除。譬如说,被留下来的应力盖层126可以用来当作金属硅化防护层。金属硅化防护层可以把基底40的部分区域跟后续的金属硅化制程相隔绝,而不要形成金属硅化物于其上。
图9显示了在金属硅化物区146与246、接触蚀刻停止(contactetch stop,CES)层148、以及层间介电(interlayer dielectric,ILD)层150形成之后的结构。如同业界所熟知的,金属硅化物区146与246可以用自行校准硅化(Salicide)制程形成在源/漏极区108与208中。为了形成一金属硅化物,一薄薄的金属层,像是钴(cobalt)、镍(nickel)、钛(Titanium)等,先形成在元件上。然后,进行一退火制程,使得金属层跟底下相接触的硅产生反应,形成一金属硅化物在其间。没有起反应,多余的金属可以去除。
在较佳实施例中,CES层148先整面的沉积上去,用的物质可以提供第一元件区100中的MOS元件所希望的应力。CES层148可以有SiN、氮氧化硅(oxynitride)、氧化硅(oxide)、等。然后,ILD层150就沉积在整个CES层148之上。
在先前所讨论的实施例中,不同的应力可以施加到不同的MOS元件的沟道区。譬如说,一第一MOS元件160是形成在第一元件区100中,而一第二MOS元件260是形成在第二元件区200中。而CES层148提供了第一应力给第二MOS元件260的沟道区252。透过多晶硅区104以及源/漏极区108的预非晶化跟极速退火,一第二应力可以产生且存放在第一MOS元件160的沟道区152中。
这样的应力可以通过在较佳实施例中的制程流程中的不同阶段来产生并存放。图10显示一种在多晶硅沉积之后到图案化之前形成应力的实施例。在基底40上形成多晶硅栅电极层180之后,进行一预非晶化制程,产生一非晶硅层162。一应力盖层164接着形成在非晶硅层162上。然后,对非晶硅层162进行一极速退火制程,使其结晶。当应力盖层164移除后,栅电极层180的上部分162就会保有一部分应力,而且就算是栅电极层180被图案化成为栅电极之后,这样的应力也将继续维持着。
一些较佳实施例的变化显示在图11与图12。在第一栅结构102图案化之后,但是在栅侧壁子形成之前,应力可以透过下列步骤产生:预非晶化栅电极104的一上部分167以及源/漏极区要形成的区域;放上应力层168;以及对于上部分167进行一极速退火制程。另一个较佳实施例的变化显示在图12,其中,应力是产生并存放在栅侧壁子106形成之后。在两个实施例中,结晶都可以透更多的退火步骤来达成。之后,应力层168都可以去除。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
栅侧壁子:9、106、206
沟道区:11、152、252
CES层:14、148
源/漏极区:12、108、208
LDD区:15、105、205
基底:40
第一元件区:100
第一栅结构:102
栅介电层:103、203
栅电极:104、204
上部分:120、124、167、220、224
预非晶化注入:125
应力盖层:126、1261、1262、164
极速退火制程:127
金属硅化物区:146、246
ILD层:150
第一MOS元件:160
非晶硅层:162
应力层:168
栅电极层:180
第二元件区:200
第二栅结构:202
掩膜层:222、229
第二MOS元件:260
Claims (20)
1.一种形成半导体结构的方法,其特征在于,所述形成半导体结构的方法包含有:
提供一基底;
形成一栅电极于该基底上;
形成一源/漏极区于该基底;
形成一非晶区于该栅电极与该源/漏极区的一上部分;
形成一应力盖层于该非晶区上;
对该非晶区进行极速退火,并使该非晶区结晶;以及
大致移除全部的该应力盖层。
2.根据权利要求1所述的形成半导体结构的方法,其特征在于,该非晶区是形成于该源/漏极区中。
3.根据权利要求2所述的形成半导体结构的方法,其特征在于,形成该源/漏极区的步骤是以一离子注入制程进行,且该离子注入制程形成该非晶区。
4.根据权利要求2所述的形成半导体结构的方法,其特征在于,形成该非晶区的步骤是包含有一预非晶化注入。
5.根据权利要求1所述的形成半导体结构的方法,其特征在于,该栅电极包含有硅,且该非晶区是位于该栅电极中。
6.根据权利要求1所述的形成半导体结构的方法,其特征在于,于移除全部的该应力盖层的步骤前,另包含有一额外的退火步骤。
7.根据权利要求1所述的形成半导体结构的方法,其特征在于,另包含有:
形成一栅侧壁子于该栅电极的一侧壁;
形成一金属硅化物区于该源/漏极区;
形成一接触蚀刻停止层于该源/漏极区与该栅电极上;以及
形成一层间介电层于该接触蚀刻停止层上。
8.一种形成半导体元件的方法,其特征在于,所述形成一半导体元件的方法包含有:
提供一基底,具有一第一元件区;
对该第一元件区中的一源/漏极区进行离子注入;
形成一应力盖层于该源/漏极区上;
对该源/漏极区进行极速退火,并使该源/漏极区结晶;以及
大致移除全部的该应力盖层。
9.根据权利要求8所述的形成半导体元件的方法,其特征在于,该极速退火是以一高能量的放射源对该基底曝照。
10.根据权利要求8所述的形成半导体元件的方法,其特征在于,该极速退火的处理时间是介于约1皮秒到约1秒之间。
11.根据权利要求8所述的形成半导体元件的方法,其特征在于,另包含有预非晶化该源/漏极区的一上部分。
12.根据权利要求8所述的形成半导体元件的方法,其特征在于,于移除全部的该应力盖层的步骤前,另包含有一额外的退火步骤。
13.根据权利要求8所述的形成半导体元件的方法,其特征在于,另包含有:
形成一多晶硅栅电极层于该第一元件区;
预非晶化该多晶硅栅电极层的一上部分;
形成该应力盖层于该多晶硅栅电极层上;
对该多晶硅栅电极层进行极速退火,并使该多晶硅栅电极层结晶;以及
于大致移除全部的该应力盖层的步骤后,图案化该多晶硅栅电极层,以形成一栅电极。
14.根据权利要求8所述的形成半导体元件的方法,其特征在于,另包含有:
形成一多晶硅栅电极层于该第一元件区;
图案化该多晶硅栅电极层,以形成一栅电极;
预非晶化该栅电极的一上部分;
形成该应力盖层于该栅电极上;
于大致移除全部的该应力盖层的步骤前,对该栅电极进行极速退火,并使该栅电极结晶。
15.根据权利要求14所述的形成半导体元件的方法,其特征在于,于大致移除全部的该应力盖层的步骤后,另包含有:
形成一栅侧壁子于该栅电极的一侧壁。
16.根据权利要求14所述的形成半导体元件的方法,其特征在于,于大致移除全部的该应力盖层的步骤前,另包含有:
形成一栅侧壁子于该栅电极的一侧壁。
17.根据权利要求8所述的形成半导体元件的方法,其特征在于,该基底另包含有一第二元件区,且该第二元件区于该源/漏极区进行该离子注入步骤、以及该极速退火与重结晶步骤时,该第二元件区是被遮住。
18.一种形成半导体结构的方法,其特征在于,所述形成半导体结构的方法包含有:
提供一基底,具有一第一以及一第二元件区;
形成一第一栅介电层于该第一元件区的该基底上,并形成一第一栅电极于该第一栅介电层上;
形成一第二栅介电层于该第二元件区的该基底上,并形成一第二栅电极于该第二栅介电层上;
形成一第一源/漏极区于该第一元件区;
形成一第二源/漏极区于该第二元件区;
预非晶化该第一源/漏极区以及该第一栅电极;
形成一第一应力盖层于该第一源/漏极区以及该第一栅电极上;
对该第一源/漏极区以及该第一栅电极进行极速退火,并使该第一源/漏极区以及该第一栅电极结晶;以及
移除该第一应力盖层。
19.根据权利要求18所述的形成半导体结构的方法,其特征在于,于对该第一源/漏极区以及该第一栅电极进行该极速退火以及该结晶之前,另包含有一步骤,遮住该第二元件区。
20.根据权利要求18所述的形成半导体结构的方法,其特征在于,另包含有:
预非晶化该第二源/漏极区以及该第二栅电极;
形成一第二应力盖层于该第二源/漏极区以及该第二栅电极上,其中,该第二应力盖层与该第一应力盖层的应力不同;
对该第二源/漏极区以及该第二栅电极进行极速退火,并使该第二源/漏极区以及该第二栅电极结晶;以及
移除该第二应力盖层。
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