CN1881563A - 半导体结构以及形成半导体晶体管的方法 - Google Patents

半导体结构以及形成半导体晶体管的方法 Download PDF

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CN1881563A
CN1881563A CNA2005101240431A CN200510124043A CN1881563A CN 1881563 A CN1881563 A CN 1881563A CN A2005101240431 A CNA2005101240431 A CN A2005101240431A CN 200510124043 A CN200510124043 A CN 200510124043A CN 1881563 A CN1881563 A CN 1881563A
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stressor layers
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梁孟松
陈建豪
聂俊峰
蔡邦彦
李资良
陈世昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体结构以及形成半导体晶体管的方法，该半导体结构包含有一基底、以及一应力层。该基底具有一第一元件区与一第二元件区。该应力层于该第一元件区与该第二元件区上。该应力层在该第一元件区内有一第一部分，具有一第一应力。该应力层在该第二元件区内有一第二部分，具有一第二应力。该第一跟该第二应力大致上不同。该第一跟该第二应力其中之一是由被一极速退火制程所产生，且该极速退火制程的热处理时间少于一秒。本发明所述的半导体结构以及形成半导体晶体管的方法，利用对于不同元件进行极速退火制程，就可以依照元件的需求，给予不同的应力。而且，以低温形成的侧壁子所带有的缺点也被克服了。

Description

半导体结构以及形成半导体晶体管的方法
技术领域
本发明是金属氧化物半导体(metal-oxide-semiconductor，MOS)元件，尤指是具有应力的沟道区的MOS元件与其相关制程。
背景技术
VLSI电路的缩小化是一个半导体业界不断追求的目标。当电路变的更小更快，元件的驱动电流的改善也更显得重要。元件电流大致上跟栅极的长度、栅极电容、还有载流子移动率(carriermobility)相关。较短的多晶硅栅极长度、较大的栅极电容、与较高的载流子移动率等都可以改善元件电流的表现。栅极长度的缩短可以透过元件尺寸的缩小而达成，这是业界持续努力的目标。栅极电容的增大也会随着栅介电层的变薄、栅介电常数的增加等来达成。为了改善元件电流的表现，也有许多的方法来增加载流子移动率。
在各种增加载流子移动率的方法当中，有一种已知的方法是形成一带有应力(strain or stress)的硅沟道。应力可以增强电子或是空穴的移动率。所以，MOS元件的特性就可以透过带有应力的沟道来改善。这样的技术，就可以在固定栅极长度的条件下，同时也没有增加电路设计的复杂度下，改善元件的特性。
当硅被施加压应力时，常温下、共平面(in-phase)的电子移动率就可以显著的增加。一种提供这样应力的方法是透过生长一比例渐进的SiGe外延层来达成。这样的比例渐进的SiGe外延层可以是一无应力的(relaxed)SiGe层。一层硅层接着形成在此无应力的SiGe层上。这样，此硅层中就会有应力，然后，MOS元件才形成在此硅层上。因为SiGe的晶格常数(lattice constant)大于硅的晶格常数，所以此硅层就会有双轴应力(biaxial tension)，而其中的载流子就可以呈现出在应力下时的移动率来。
应力在一个元件中，可以依照方向的不同，有三个部分：平行于MOS元件沟道长度的部分，平行于MOS元件沟道宽度的部分，以及垂直于沟道平面的部分。如果应力的方向是平行沟道长度或是宽度，这样的应力称为“共平面”应力。研究有发现，属于共平面张(tensile)应力的双轴应力可以改善NMOS的效能，而平行于沟道方向的压(compressive)应力可以改善PMOS的效能。
应力也可以透过在MOS元件上形成一应力盖层(strainedcapping layer)来实现。譬如说，一接触蚀刻停止(contact etchstop，CES)层就可以当这样的应力盖层。当一应力盖层沉积时，因为应力盖层跟底下的物质之间晶格间隔距离的差异，为了要尝试去拉齐对齐彼此的晶格，共平面应力就会因而产生。图1显示了具有一应力沟道区的一传统MOS元件。应力盖层，如同侧壁子9与CES层14所示，可以对源/漏极区12(包含LDD区15)引入应力，而这样的应力可以导入沟道区11中。所以沟道区11中的载流子移动率就可以改善。
传统形成应力盖层的方法有不少的缺点，而且，其效果也受限于应力盖层本身的特性。譬如说，应力盖层的厚度不可以太厚，否则将增大后续填缝技术的困难度。因此，应力盖层所可以提供的应力就相当的有限。此外，要形成一个应力盖层来同时符合不同元件(譬如NMOS与PMOS)所要求的不同需求，往往是非常的复杂而且成本非常的高。这样制程所产生的应力是可以明显的影响晶体管元件的效能。目前，为了更好的效能，已经有许多的局部的机械应力控制技术被发展来增强载流子的移动率。譬如说，具有高应力的氮化硅层已经有被拿来当作CES层或是侧壁子，同时对于晶体管的沟道区提供强而有力的应力。然而，这些方法都受限于这些应力层的特性。而且，要沉积一高品质、具有高应力的应力层，也是一件困难的事。
因此，要如何改善一盖层，来提供MOS元件的沟道区适当的应力，并同时在没有增加太多的制程复杂度的条件之下，就成了一个迫切祈求的目标。
发明内容
本发明提供一种形成一半导体结构的方法。首先提供一基底，该基底包含有一第一元件区。接着形成一应力层于该基底上。然后，以一高能量的放射源对该基底曝照，且对于该第一元件区上的该应力层进行热退火处理，处理时间少于1秒。
本发明亦提供一种形成半导体晶体管的方法：提供一基底，包含有一主动区；形成一第一栅极于该主动区上；形成一应力层，该应力层具有一第一部分覆盖于该第一栅极上；以及，以一高能量的放射源对该基底曝照，且对于该应力层的该第一部分进行一第一热退火处理，处理时间少于1秒。
本发明所述的形成半导体晶体管的方法，该处理时间是介于约1皮秒(pico-second)到约1毫秒(milli-second)之间。
本发明所述的形成半导体晶体管的方法，其中，该放射源是为一激光或是一闪光灯。
本发明所述的形成半导体晶体管的方法，该放射源具有一波长，介于一纳米(nm)到一毫米(mm)之间。
本发明所述的形成半导体晶体管的方法，当进行该第一热退火处理时，该应力层的该第一部分所承受的温度是大约高于1000℃。
本发明所述的形成半导体晶体管的方法，形成该应力层的步骤包含有：形成一栅侧壁子层；以及于进行该第一热退火处理之前，蚀刻该栅侧壁子层，以形成一栅侧壁子。
本发明所述的形成半导体晶体管的方法，形成该应力层的步骤包含有：形成一栅侧壁子层；以及于进行该第一热退火处理之后，蚀刻该栅侧壁子层，以形成一栅侧壁子。
本发明所述的形成半导体晶体管的方法，形成该应力层的步骤包含有：形成一第二栅极于该基底上；其中，该应力层的一第二部分是覆盖于该第二栅极上，且于进行该第一热退火处理时，该应力层的该第二部分并没有被退火。
本发明的亦提供一半导体结构。该半导体结构包含有一基底、以及一应力层。该基底具有一第一元件区与一第二元件区。该应力层于该第一元件区与该第二元件区上。该应力层在该第一元件区内有一第一部分，具有一第一应力。该应力层在该第二元件区内有一第二部分，具有一第二应力。该第一跟该第二应力大致上不同。该第一跟该第二应力其中之一是由被一极速退火制程所产生，且该极速退火制程的热处理时间少于一秒。
本发明所述的半导体结构，该应力层包含一栅侧壁子。
本发明所述的半导体结构，该应力层包含一盖层。
本发明所述的半导体结构，该第一应力是为压应力，该第二应力是为张应力，其中，一NMOS元件是形成于该第一元件区，一PMOS元件形成于该第二元件区。
本发明所述的半导体结构以及半导体晶体管的形成方法，使MOS元件上的侧壁子、CES层、以及ILD层的应力都可以被调整，所以MOS元件中的沟道区的应力也跟着改善。此外，侧壁子的致密度改善了。利用对于不同元件进行极速退火制程，就可以依照元件的需求，给予不同的应力。而且，以低温形成的侧壁子所带有的缺点也被克服了。
附图说明
图1显示了具有一应力沟道区的一传统MOS元件；
图2到图10显示在不同制程步骤时，调整应力层的应力的方法所使用的晶圆剖面图。
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合所附图式，作详细说明如下：
一种在形成应力层之后，调整其应力的方法显示于图2到图10的图示中。在这些不同的图与实施例当中，一样的符号将用在一样的零件上。
请看图2，其中有显示了一基底40。基底40可以用一般熟知的基底材料，譬如说硅、SiGe、长在SiGe上带有应力的硅、绝缘层上覆硅(silicon on insulator，SOI)、绝缘层上覆硅锗(silicongermanium on insulator，SGOI)、绝缘层上覆锗(germaniumon insulator，GOI)等等。这样的基底40可以带有第一元件区100跟第二元件区200，用来形成不一样的逻辑元件。于一实施例中，元件区100跟200的其中之一用来形成PMOS；另一个用来形成NMOS。于其他一实施例中，元件区100跟200的其中之一是核心区(core region)，用来形成核心元件(core device)；另一个是周边(periphery)区，用来形成像输入输出(Input/output)元件。于其他一实施例中，元件区100跟200的其中之一是逻辑区(logic region)，具有一逻辑电路；另一个是存储区(memory)，具有存储元件(memory cell)，譬如说，静态随机存取存储器(SRAM)或是动态随机存取存储器(DRAM)。
第一元件区100中形成了一第一栅结构，具有一栅介电层124以及一栅电极126。第二元件区200中形成了一第二栅结构，具有一栅介电层224以及一栅电极226。如同一般所熟知的，为了要形成这些栅结构，一栅介电层先形成在基底40上。这样的栅介电层最好是高介电常数(High K)的材料。一栅电极层，可以是多晶硅、金属、或是金属硅化物等，接着形成在栅介电层上。栅介电层跟栅电极层接着可以被图案化，来形成栅电极126与226、跟栅介电层124与224。可以接着在第一元件区100与第二元件区200中，注入适当的杂质来形成轻掺杂源/漏极区(lightly-dopedsource/drain region)128跟228。
图3显示了一栅侧壁子层42沉积在先前所完成的结构上。在此说明书中，栅侧壁子层42有时也会是一应力层。但是应力层也可能是、或是包含有其他层，譬如说后续形成的CES层或是层间介电(inter layer dielectric，ILD)层。而对于任何一应力层所使用的极速退火制程也可以适用到其他层。
在此实施例中，栅侧壁子层42为单一的一层，覆盖在第一元件区100跟第二元件区200上：在第一元件区100的栅侧壁子层标示为421，在第二元件区200的栅侧壁子层标示为422。栅侧壁子层42的材料可以是SiN、氮氧化硅(oxynitride)、氧化硅(oxide)等等，而且可以用传统的沉积方法形成，譬如等离子辅助化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)、低压化学气相沉积(low pressure chemical vapordeposition，LP CVD)、快速热退火化学气相沉积(rapid thermalchemical vapor deposition，RTCVD)、原子层沉积(atomic layerdeposition，ALD)、物理气相沉积(physical vapor deposition，PVD)等。如同业界所知的，栅侧壁子层42的应力可以透过适当的材质选取以及形成的方法来调整。形成的方法中，可以调整的制程参数有温度、沉积速度、功率等等。本领域技术人员可以透过实验，发现这些制程参数跟一沉积层的应力的关系。在沉积之后，栅侧壁子层42具有一第一内在应力。
一掩膜层130接着覆盖在第一元件区100上，如同图4所示。在一实施例中，掩膜层130可以是一光致抗蚀剂层。掩膜层130可能是一光致抗蚀剂层、一抗反射层(anti-reflect coating，ARC)、一硬掩膜层、或者上述的组合层。
接着用一极速退火(super anneal)制程对于栅侧壁子层42进行热退火处理。处理方式可以是以一高能量的放射源，譬如激光或是闪光灯，在很短的时间内，来对基底40曝照。掩膜层130可以吸收或是反射放射源所放射出来的能量，借以保护其下的栅侧壁子层421，免于受到极速退火。因为温度的极速上升，暴露的栅侧壁子层422将会被热退火处理。该放射源的波长可以介于一纳米(nm)到一毫米(mm)之间。透过波长的选取，就可以控制基底40被热退火处理的深度。一般而言，波长越长，被热退火处理的深度越深。热退火处理时间最好少于1秒。在另一个实施例中，热退火处理时间介于约1皮秒(pico-second)到约1毫秒(milli-second)之间。热退火处理温度最好大约高于1000℃，可以透过调整高能量的放射源的能量来控制。在其他实施例中，此极速退火制程包含有一快速退火(flash anneal)。掩膜层130可以在极速退火制程后去除。
在栅侧壁子层422中的应力会受到极速退火制程的影响而调整。一般来说，当一层被极速退火制程热处理后，其中的应力应该会往张应力(tensile)方向变大。譬如说，如果压应力(compressive strain)是用负值表示，而张应力是用正值表示的话，那经过极速退火制程热处理后，那一层的应力的值就应该是增加的。实验显示了应力的增加量跟极速退火制程的能量基本上是呈现正相关：能量越高，应力增加量越大。因此，可以通过不同能量的极速退火制程，来调整一应力层其中的应力。
在极速退火制程后，栅侧壁子层422具有一第二内在应力。因为被遮住的栅侧壁子层421还是停留在有第一内在应力的状况下，所以，之后在第一元件区100跟第二元件区200中形成的侧壁子就会有不同的应力。譬如说，栅侧壁子层421可能有压应力，而因为被极速退火制程所影响，栅侧壁子层422具有张应力。在另一个实施例中，栅侧壁子层421与422都是有张应力，只是栅侧壁子层422中的张应力比较高。
图4显示仅仅有部分的应力层(譬如栅侧壁子层422)被热退火处理。这是一个非常有用的特征。因为不同的元件(譬如NMOS跟PMOS)所需要的应力，就可以分别的调整，而不会影响到其他的元件所要的应力。所以，本发明的实施例提供了一个非常具有弹性的方式来调整应力。
在第二元件区200被热处理后，也可以选择性的把第二元件区200遮住，对于栅侧壁子层421进行热处理(未显示)。然而，如果都是进行极速退火制程，这两个极速退火制程的制程参数，像是波长、能量等，最好是不一样。这样，栅侧壁子层421与422的内在应力才会不一样。
栅侧壁子层422最后会用来形成侧壁子。而栅侧壁子层422的密度会因为极速退火制程的影响，而变的比较致密。一般来说，在侧壁子形成之后到源/漏极区完成之前都会经历一些浸湿制程(wet dip process)，像是一些清洗制程(cleaning process)。而这些浸湿制程的副作用，往往就是蚀刻到侧壁子。所以，往往导致了侧壁子的厚度上的控制问题，尤其是当对侧壁子的蚀刻率非常高的时候。变的比较致密的侧壁子可以降低后续浸湿制程所造成的影响，所以侧壁子的制作也会变的比较好控制。此外，因为极速退火制程是一个非常非常短时间的制程，尽管在对于栅侧壁子层42进行热处理时，底下的LDD区128跟228也很有可能会被同时热处理，LDD区128跟228中的杂质扩散应该是可以控制的很好。
在一实施例中，掩膜层130并没有形成。透过使用可以集中控制其放射线的放射源，譬如说光束大小范围可以调整的激光，就可以选择第一元件区100或是第二元件区200，来各别进行极速退火制程。
图5显示了侧壁子132跟232的形成，一般是经历了非等向性蚀刻。譬如说，反应离子蚀刻(reactive ion etching，RIE)可以移除在垂直表面上的栅侧壁子层42。所形成的侧壁子132、232就会有不同的内在应力，就可以分别对于其附近MOS元件的沟道区施以相对应的不同应力。
跟图5类似的结构也可以用不一样的制程流程来制作，如同图6与图7所示。图6显示图3中的结构在一后续步骤中的剖面图。在尚未经历极速退火制程之前，栅侧壁子层42就先蚀刻，所以侧壁子132与232有一样的内在应力。在图7中，一掩膜层140形成在基底40上，用来保护侧壁子132，而极速退火制程就只有对于侧壁子232进行热处理。掩膜层140最好跟图3中的掩膜层130类似。掩膜层140可以在稍候的制程去除。
图8显示了源/漏极区144与244以及金属硅化物层146与246的形成。源/漏极区144与244的表面可能比基底40的表面低或是高，低的话可以用蚀刻的技术，高的话可以用外延成长，相对应的后续形成的应力层也会变低或是变高。在一例子中，源/漏极区144与244是以离子注入的方式，将杂质注入基底40中而形成。侧壁子132以及232用来当作掩膜，所以源/漏极区144与244的边缘会跟侧壁子132以及232大致切齐。栅电极126与226最好也一起被离子注入，用以降低其电阻。
金属硅化物层146与246可以用自行校准硅化(Salicide)制程形成在源/漏极区144与244中。为了形成一金属硅化物，一薄薄的金属层，像是钴(cobalt)、镍(nickel)、钛(Titanium)等，先形成在元件上。然后，进行一退火制程，使得金属层跟底下相接触的硅产生反应，形成一金属硅化物在其间。没有起反应，多余的金属可以去除。
图9为接触蚀刻停止(contact etch stop，CES)层148形成之后的结构图。CES层148有第一部分1481与第二部分1482。CES层148可以有SiN、氮氧化硅(oxynitride)、氧化硅(oxide)等。在一实施例中，CES层148先整面的沉积上去，用的物质可以提供第一元件区100中的MOS元件所希望的应力。透过一掩膜层149的协助，在第二元件区200中的CES层1482可以用极速退火制程进行热处理，所以产生了适当的应力。在另一个实施例中，CES层1481经历了热处理，但是CES层1482被一掩膜层遮住。在另一个实施例中，CES层1481跟1482被不同的极速退火制程所处里，但是两个极速退火制程的制程参数不同。在极速退火制程之后，掩膜层149可以去除。
接着，如同图10所示，一层间介电(inter-layer dielectric，ILD)层150沉积在CES层148的表面上。ILD层150有第一部分1501与第二部分1502。类似先前的制程，一掩膜层152接着形成，用来覆盖第一元件区100。一极速退火制程接着进行，用来改变ILD层1502中的应力。
在前述的实施例中，应力层，包含有侧壁子232、CES层148跟ILD层150，是在不同的步骤中经历了极速退火制程。然而，极速退火制程是可以紧接着在侧壁子232、CES层148跟ILD层150各别完成之后就进行，或是两层、三层完成之后才进行。这样复合带有应力的侧壁子/CES层/ILD层的结构可以形成在不同的元件区域上，某些部分带有张应力，而某些部分，因为极速退火制程的影响，所带的应力会变成压应力。譬如说，第一元件区100中有一PMOS元件，第二元件区200中有一NMOS元件。在第一元件区100中的应力层，像是CES层1482跟/或ILD层1502，会有压应力。所以相对的PMOS沟道区就会有压应力。在第二元件区200中的应力层被极速退火制程所影响，所以产生了张应力。所以，所以相对的NMOS沟道区就会有张应力。
极速退火制程可以对整个晶圆进行，或是对晶圆上的特定部分进行。可以依照元件种类不同而进行，譬如说分成NMOS元件、PMOS元件、双极性互补MOS(bipolar complementary MOS，Bi-CMOS)元件、双极性面结型晶体管(bipolar junctiontransistor，BJT)、电容等等。也可以依照电路种类不同而进行，譬如说分成逻辑电路、高效能电路、低功率电路、SRAM、内建RAM、BJT、Bi-CMOS、射频(radio frequency，RF)电路、混合模式(mix-mode)电路等等。
以上的实施例有许多的好处。MOS元件上的侧壁子、CES层、以及ILD层的应力都可以被调整，所以MOS元件中的沟道区的应力也跟着改善。此外，侧壁子的致密度改善了。利用对于不同元件进行极速退火制程，就可以依照元件的需求，给予不同的应力。而且，以低温形成的侧壁子所带有的缺点也被克服了。
虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下：
侧壁子：9
源/漏极区：12
CES层：14
LDD区：15
基底：40
栅侧壁子层：42、421、422
第一元件区：100
第二元件区：200
栅介电层：124、224
栅电极：126、226
轻掺杂源/漏极区：128、228
掩膜层：130、140、149、152
侧壁子：132、232
源/漏极区：144、244
金属硅化物层：146、246
CES层：148、1481、1482
ILD层：150、1501、1502

Claims (12)

1.一种形成半导体晶体管的方法，其特征在于，该方法包含有：
提供一基底，包含有一主动区；
形成一第一栅极于该主动区上；
形成一应力层，该应力层具有一第一部分覆盖于该第一栅极上；以及
以一高能量的放射源对该基底曝照，且对于该应力层的该第一部分进行一第一热退火处理，处理时间少于1秒。
2.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，该处理时间是介于1皮秒到1毫秒之间。
3.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，该放射源是为一激光或是一闪光灯。
4.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，该放射源具有一波长，介于一纳米到一毫米之间。
5.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，当进行该第一热退火处理时，该应力层的该第一部分所承受的温度是高于1000℃。
6.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，形成该应力层的步骤包含有：
形成一栅侧壁子层；以及
于进行该第一热退火处理之前，蚀刻该栅侧壁子层，以形成一栅侧壁子。
7.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，形成该应力层的步骤包含有：
形成一栅侧壁子层；以及
于进行该第一热退火处理之后，蚀刻该栅侧壁子层，以形成一栅侧壁子。
8.根据权利要求1所述的形成半导体晶体管的方法，其特征在于，形成该应力层的步骤包含有：
形成一第二栅极于该基底上；
其中，该应力层的一第二部分是覆盖于该第二栅极上，且于进行该第一热退火处理时，该应力层的该第二部分并没有被退火。
9.一半导体结构，其特征在于，该半导体结构包含有：
一基底，具有一第一元件区与一第二元件区；以及
一应力层，于该第一元件区与该第二元件区上；
其中，该应力层在该第一元件区内有一第一部分，具有一第一应力，该应力层在该第二元件区内有一第二部分，具有一第二应力，且该第一跟该第二应力不同；
其中，该第一跟该第二应力其中之一是由被一极速退火制程所产生，且该极速退火制程的热处理时间少于一秒。
10.根据权利要求9所述的半导体结构，其特征在于，该应力层包含一栅侧壁子。
11.根据权利要求9所述的半导体结构，其特征在于，该应力层包含一盖层。
12.根据权利要求9所述的半导体结构，其特征在于，该第一应力是为压应力，该第二应力是为张应力，其中，一N型金属氧化物半导体元件是形成于该第一元件区，一P型金属氧化物半导体元件形成于该第二元件区。
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