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Publication numberCN1624916 A
Publication typeApplication
Application numberCN 200410010418
Publication date8 Jun 2005
Filing date8 Nov 2004
Priority date6 Nov 2003
Also published asCN100495703C, DE602004014331D1, EP1530226A2, EP1530226A3, EP1530226B1, US7807337, US20050116317, US20080102409
Publication number200410010418.7, CN 1624916 A, CN 1624916A, CN 200410010418, CN-A-1624916, CN1624916 A, CN1624916A, CN200410010418, CN200410010418.7
Inventors孙洪成, 李孝钟, 李义亨, 河商录, 金一龙, 金二权
Applicant三星电子株式会社
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Inductor for a system-on-a-chip and method for manufacturing the same
CN 1624916 A
Abstract  translated from Chinese
本发明公开了一种用于芯片上系统的电感器及制造该电感器的方法。 The present invention discloses an inductor and a method for manufacturing the on-chip system inductor. 该电感器包括通过连接多个导电图案形成导线,其中该导电图案从在下布线上形成的籽层生长。 The inductor comprises a wire formed by connecting a plurality of conductive patterns, wherein the seed layer is formed from the conductive pattern on the lower wiring growth. 该方法包括使用电解镀层工艺或非电镀层工艺从籽层生长多个相邻的导电图案,直到它们彼此连接。 The method comprises using an electrolytic plating process or plating process a plurality of adjacent conductive patterns grown from the seed layer until they are connected to each other. 该方法还能够将导线的高度和宽度调节到所需值。 The method is also able to adjust the height and width of the wires to the desired value.
Claims(58)  translated from Chinese
1.一种电感器,包括:一籽层,形成在一基板上;和一导线,形成在所述籽层上,其中所述导线通过连接从所述籽层生长的多个导电图案形成。 An inductor, comprising: a seed layer formed on a substrate; and a conductor, is formed on the seed layer, wherein said wire is formed from the seed layer by a plurality of conductive patterns grown connection.
2.如权利要求1所述的电感器,其中进一步包括:一防扩散层,形成在所述基板和所述籽层之间。 2. The inductor of claim 1, wherein further comprising: a diffusion preventing layer, formed between the substrate and the seed layer.
3.如权利要求1所述的电感器,其中进一步包括:一保护层,形成在所述导线上。 Inductor according to claim, wherein further comprising: a protective layer formed on the wire.
4.如权利要求3所述的电感器,其中所述保护层包括碳化硅或氮化硅。 4. The inductor according to claim 3, wherein said protective layer comprises silicon carbide or silicon nitride.
5.如权利要求3所述的电感器,其中所述保护层具有大约100到1000埃的厚度。 5. The inductor of claim 3, wherein the protective layer has a thickness of about 100 to 1000 Angstroms.
6.如权利要求1所述的电感器,其中进一步包括:一模层,所述模层包括由所述多个导电图案中的一个分别填充的孔阵列。 6. The inductor of claim 1, wherein further comprising: a mold layer, said mold layer comprising an array of apertures from said plurality of conductive patterns, respectively, in a fill.
7.如权利要求6所述的电感器,其中填充孔阵列的所述多个导电图案在所述模层上彼此连接以形成所述导线。 7. The inductor of claim 6, wherein said plurality of conductive patterns filling the hole arrays in the mold connected to each other to form a layer on the wire.
8.如权利要求6所述的电感器,其中所述模层包括氧化物或光刻胶。 8. The inductor as claimed in claim 6, wherein the mold layer comprises oxide or photoresist.
9.如权利要求6所述的电感器,其中所述模层具有大约500到30000埃的一厚度。 9. The inductor of claim 6, wherein the mold layer having a thickness of about 500 to 30,000 Angstroms.
10.如权利要求6所述的电感器,其中所述孔阵列的每个具有大约500到30000埃的一深度。 10. The inductor of claim 6, wherein each said array of holes having a depth of about 500 to 30,000 Angstroms.
11.如权利要求1所述的电感器,其中进一步包括:一模层,所述模层包括由所述多个导电图案中的一个分别填充的沟道。 11. The inductor of claim 1, wherein further comprising: a mold layer, said mold layer comprises a plurality of conductive patterns were each filled in a channel.
12.如权利要求11所述的电感器,其中填充所述沟道的所述多个导电图案在所述模层上彼此连接以形成所述导线。 12. The inductor of claim 11, wherein the filling channel of the plurality of conductive patterns on the mold layer connected to each other to form the wire.
13.如权利要求11所述的电感器,其中所述模层包括氧化物或光刻胶。 13. The inductor of claim 11, wherein the mold layer comprises oxide or photoresist.
14.如权利要求11所述的电感器,其中所述模层具有大约500到30000埃的一厚度。 14. The inductor of claim 11, wherein the mold layer having a thickness of about 500 to 30,000 Angstroms.
15.如权利要求11所述的电感器,其中所述沟道的每个具有大约500到30000埃的一深度。 15. The inductor of claim 11, each having a depth of about 500 to 30,000 wherein the channel.
16.如权利要求1所述的电感器,其中所述导线具有一圆形上部。 16. The inductor of claim 1, wherein said wire has a circular upper portion.
17.一种电感器,包括:一基板,包括一导电结构;一籽层,形成在所述基板上;一模层,形成在所述籽层上,其中所述模层包括暴露出所述籽层的孔阵列;以及一导线,形成在所述籽层上,其中所述导线电连接到所述导电结构上,并由多个连接的从所述籽层生长的导电图案形成。 17. An inductor, comprising: a substrate comprising a conductive structure; a seed layer formed on said substrate; a mold layer formed on the seed layer, wherein the layer comprises exposing said mold aperture array seed layer; and a conductor, is formed on the seed layer, wherein said conductor is electrically connected to the conductive structure by a plurality of said seed layer is grown from the conductive pattern connected.
18.如权利要求17所述的电感器,其中进一步包括:在所述基板和所述籽层之间形成的一防扩散层。 18. The inductor of claim 17, wherein further comprising: a diffusion preventing layer between the substrate and the seed layer is formed.
19.如权利要求17所述的电感器,其中进一步包括:一保护层,形成在所述导线上。 19. The inductor of claim 17, wherein further comprising: a protective layer formed on the wire.
20.如权利要求17所述的电感器,其中所述导线具有一蘑菇状结构的一上部。 20. The inductor according to claim 17, wherein said wire has an upper portion of a mushroom-shaped structure.
21.一种电感器,包括:一基板,包括一导电结构;一模层,形成在所述基板上,其中所述模层包括具有内表面的孔阵列;一籽层,形成在所述孔阵列的内表面上;以及一导线,形成在所述籽层上,其中所述导线电连接到所述导电结构并由从所述籽层生长的多个连接的导电图案形成。 21. An inductor, comprising: a substrate comprising a conductive structure; a mold layer formed on the substrate, wherein the mold layer comprises an array of apertures having an inner surface; a seed layer, is formed in the hole on the inner surface of the array; and a conductor, is formed on the seed layer, wherein said conductor is electrically connected to the conductive structure is formed from the seed layer by a plurality of conductive patterns grown connections.
22.如权利要求21所述的电感器,其中进一步包括:一防扩散层,形成在所述籽层和包括所述导电结构的所述基板之间。 21 22. The inductor according to claim, wherein further comprising: a diffusion preventing layer, is formed between the substrate and the seed layer comprises the conductive structure.
23.如权利要求21所述的电感器,其中进一步包括:一保护层,形成在所述导线上。 21 23. The inductor according to claim, wherein further comprising: a protective layer formed on the wire.
24.如权利要求21所述的电感器,其中所述导线具有一圆形上部。 24. The inductor according to claim 21, wherein said wire has a circular upper portion.
25.一种电感器,包括:一基板,包括一导电结构;一模层,形成在所述基板上,其中所述模层包括具有内表面的孔阵列;一籽层,形成在所述孔阵列的所述内表面上;以及一导线,形成在所述籽层上,其中所述导线电连接到所述导电结构上并由多个连接的从所述籽层生长的导电图案形成。 25. An inductor, comprising: a substrate comprising a conductive structure; a mold layer formed on the substrate, wherein the mold layer comprises an array of apertures having an inner surface; a seed layer, is formed in the hole On the inner surface of said array; and a conductor, is formed on the seed layer, wherein said conductor is electrically connected to the conductive structure by a plurality of said seed layer is grown from the conductive pattern connected.
26.如权利要求25所述的电感器,其中进一步包括:一防扩散层,形成在所述籽层和包括所述导电结构的所述基板之间。 25 26. The inductor according to claim, wherein further comprising: a diffusion preventing layer, is formed between the substrate and the seed layer comprises the conductive structure.
27.如权利要求25所述的电感器,其中进一步包括:一保护层,形成在所述导线上。 27. The inductor according to claim 25, wherein further comprising: a protective layer formed on the wire.
28.如权利要求25所述的电感器,其中所述导线具有一圆形上部。 28. The inductor according to claim 25, wherein the wire has a circular upper portion.
29.一种电感器,包括:一基板,包括一导电结构;一模层,形成在所述基板上,其中所述模层包括具有内表面的孔阵列;一第一籽层,形成在所述孔阵列的所述内表面上和在所述模层上;一帽盖层,形成在所述第一籽层上;一第二籽层,形成在位于所述孔阵列中的所述帽盖层的部分上;以及一导线,形成在所述第二籽层上,其中所述导线电连接到所述导电结构上并由多个连接的从所述第二籽层生长的导电图案而形成。 29. An inductor, comprising: a substrate comprising a conductive structure; a mold layer formed on the substrate, wherein the mold layer comprises an array of apertures having an inner surface; a first seed layer formed on the the cap of a second seed layer formed in said aperture array; the array of holes of said inner surface and on the mold layer; a cap layer formed on the first seed layer a cap portion; and a wire, formed on said second seed layer, wherein said conductor is electrically connected to the conductive structure by a plurality of second seed layer is grown from the conductive pattern and connected formation.
30.如权利要求29所述的电感器,其中进一步包括:一防扩散层,形成在所述第一籽层和包括所述导电结构的所述基板之间以及所述第一籽层和所述模层之间。 30. The inductor of claim 29, wherein further comprising: a diffusion preventing layer, is formed between the first seed layer and the substrate and the electrically conductive structure comprises the first seed layer and described mold layer.
31.如权利要求29所述的电感器,其中所述第一籽层包括选自铜、铂、钯、镍、银、金及其合金所构成的组中的一成分。 31. The inductor according to claim 29, wherein the first seed layer is selected from the group comprising copper, platinum, palladium, nickel, silver, gold, and alloys composed of one component.
32.如权利要求29所述的电感器,其中所述帽盖层包括铝(Al)。 32. The inductor of claim 29, wherein the capping layer comprises aluminum (Al).
33.如权利要求32所述的电感器,其中所述帽盖层具有大约100到500埃的一厚度。 33. The inductor according to claim 32, wherein the capping layer has a thickness of about 100-500 angstroms.
34.如权利要求29所述的电感器,其中所述第二籽层包括选自铜、铂、钯、镍、银、金及其合金所构成的组中的一成分。 34. The inductor according to claim 29, wherein said second seed layer selected from the group comprising copper, platinum, palladium, nickel, silver, gold, and alloys composed of one component.
35.如权利要求29所述的电感器,其中进一步包括:一保护层,形成在所述导线上。 35. The inductor according to claim 29, wherein further comprising: a protective layer formed on the wire.
36.如权利要求29所述的电感器,其中所述导线具有一圆形上部。 36. The inductor according to claim 29, wherein the wire has a circular upper portion.
37.一种制造电感器的方法,包括以下步骤:在一籽层上形成一模层,其中所述模层包括暴露出所述籽层的孔阵列;从所述籽层在所述模层上形成一导电图案以填充所述孔阵列;以及通过在所述模层上生长所述导电图案并连接所述导电图案在所述模层上形成一导线。 37. A method of manufacturing an inductor, comprising the steps of: forming a mold layer on a seed layer, wherein the mold layer comprises hole arrays exposing the seed layer; layer from the seed layer in the mold a conductive pattern formed to fill the hole arrays; and by growth on the mold layer and the conductive pattern connecting the conductive pattern forming a conductor layer on the mold.
38.如权利要求37所述的方法,其中形成所述模层的步骤包括:在所述籽层上形成一光刻胶膜;以及通过对所述光刻胶膜构图在所述籽层上形成一光刻胶图案,其中所述光刻胶图案包括暴露出所述籽层的所述孔阵列。 And by patterning the photoresist film on the seed layer; on the seed layer a photoresist film is formed: 38. The method of claim 37, wherein the step of forming the mold layer comprises forming a photoresist pattern, wherein the photoresist pattern includes the hole arrays exposing the seed layer.
39.如权利要求38所述的方法,其中形成所述光刻胶图案包括:在所述光刻胶膜上放置一掩模,所述掩模包括具有基本平行设置的孔阵列的一图案;以及使用所述掩模对所述光刻胶膜曝光。 39. The method of claim 38, wherein forming the photoresist pattern comprises: placing a mask on the photoresist film, the mask comprising a pattern having a set of substantially parallel array of holes; and using the mask of the photoresist film is exposed.
40.如权利要求38所述的方法,其中进一步包括:在所述光刻胶膜上形成一防反射层。 40. The method of claim 38, wherein further comprising: an anti-reflection layer is formed on the photoresist film.
41.如权利要求40所述的方法,其中进一步包括:在形成所述导线之后除去所述光刻胶图案和所述防反射层。 41. The method of claim 40, wherein further comprising: removing the wire after forming the photoresist pattern and the anti-reflection layer.
42.如权利要求41所述的方法,其中使用一有机去除剂、含有相对高浓度的臭氧的溶液或含有二氧化碳的标准清洁溶液除去所述光刻胶图案和所述防反射层。 42. The method of claim 41, wherein an organic remover, a relatively high concentration of ozone-containing solution or a standard cleaning solution containing carbon dioxide removing the photoresist pattern and the anti-reflection layer.
43.如权利要求37所述的方法,其中形成所述模层的步骤包括:在所述籽层上形成一氧化物层;在所述氧化物层上形成一光刻胶膜;通过对所述光刻胶膜构图在所述氧化物层上形成一光刻胶图案;以及通过使用所述光刻胶图案作为一蚀刻掩模,蚀刻所述模层形成穿过所述模层的孔阵列。 43. The method of claim 37, wherein the step of forming the mold layer comprises: forming an oxide layer on the seed layer; a photoresist film is formed on the oxide layer; by the patterning said photoresist film is formed on said oxide layer a photoresist pattern; and by using the photoresist pattern as an etch mask, the array of apertures through said mold layer etching the mold layer is formed .
44.如权利要求37所述的方法,其中进一步包括:在所述籽层和底层结构之间形成一防扩散层。 44. The method of claim 37, wherein further comprising: between the seed layer and the underlying structure to form a diffusion preventing layer.
45.如权利要求44所述的方法,其中进一步包括:在形成所述导线之后,部分地除去所述籽层和所述防扩散层,位于导线下面的所述籽层和所述防扩散层的部分除外。 45. The method of claim 44, wherein further comprising: after forming the conductor, partially removing the seed layer and the diffusion preventing layer, located below the wire seed layer and the diffusion preventing layer with the exception of parts.
46.如权利要求45所述的方法,其中使用含有氟化氢溶液和过氧化氢或氟化氢溶液和硝酸的溶液部分去除所述籽层和所述防扩散层。 46. The method of claim 45, wherein the solution containing hydrogen fluoride and hydrogen through partial oxidation of a solution or a solution of hydrogen fluoride and nitric acid to remove the seed layer and the diffusion preventing layer.
47.如权利要求37所述的方法,其中进一步包括:在所述导线上形成一保护层。 47. The method of claim 37, wherein further comprising: a protective layer formed on said conductor.
48.如权利要求37所述的方法,其中通过电解镀层工艺或非电镀层工艺形成所述导线。 48. The method of claim 37, wherein said conductor is formed by electrolytic plating or electroless plating layer process technology.
49.如权利要求48所述的方法,其中使用包括硫酸铜溶液、硫酸溶液以及包括氯离子的溶液的镀层溶液并采用大约20到40mA/cm2的电流密度来进行电解镀层工艺。 49. The method of claim 48, wherein the use comprises a copper sulfate solution, a sulfuric acid solution and the coating solution comprises a solution of chloride ions and the use of about 20 to 40mA / cm2 current density for the electrolytic plating process.
50.一种制造电感器的方法,包括以下步骤:在一籽层上形成一模层,其中所述模层包括暴露出所述籽层的沟道;从所述籽层在所述模层上形成一导电图案以填充沟道;以及通过在所述模层上生长所述导电图案并连接所述导电图案,在所述模层上形成一导线。 50. A method of manufacturing an inductor, comprising the steps of: forming a mold layer on a seed layer, wherein said mold comprises a channel layer to expose the seed layer; layer from the seed layer in the mold a conductive pattern formed to fill the trench; and on the mold layer by growing the conductive pattern and connected to the conductive pattern, forming a conductor layer on the mold.
51.如权利要求50所述的方法,其中形成所述模层步骤包括:在所述籽层上形成一光刻胶膜;通过对所述光刻胶膜构图在所述籽层层上形成一光刻胶图案,其中所述光刻胶图案包括暴露出所述籽层的沟道。 51. The method of claim 50, wherein forming the mold layer comprises: forming a photoresist film on the seed layer; by the patterned photoresist film is formed on the seed layer a photoresist pattern, wherein the photoresist pattern includes a channel exposing the seed layer.
52.如权利要求51所述的方法,其中形成所述光刻胶图案的步骤包括:在所述光刻胶膜上放置一掩模,所述掩模包括具有基本平行沟道的一图案;以及使用所述掩模对所述光刻胶膜曝光。 52. The method of claim 51, wherein the step of forming the photoresist pattern comprises: placing a mask on the photoresist film, the mask comprising a channel having a substantially parallel pattern; and using the mask of the photoresist film is exposed.
53.一种制造电感器的方法,包括以下步骤:在包括一导电结构的一基板上形成一模层,其中所述模层包括具有内表面的孔阵列;在所述孔阵列的所述内表面上和在所述模层上形成一防扩散层;在位于所述孔阵列中的所述防扩散层的部分上形成籽层图案;从所述籽层图案形成导电图案以填充所述孔阵列;通过在所述模层上生长所述导电图案和通过连接所述导电图案在所述模层上形成一导线;以及在所述导线上形成一保护层。 53. A method for manufacturing an inductor, comprising the steps of: forming a mold layer on a substrate comprising a conductive structure, wherein the mold layer comprises an inner surface having an array of holes; said bore in said array upper surface and a diffusion preventing layer is formed on the mold layer; patterned seed layer is formed on the portion of the diffusion preventing layer is located in the aperture array; the holes are filled with a conductive pattern formed from the seed layer patterns array; by growth on the mold layer and the conductive pattern connecting the conductive pattern by forming a conductor layer on the mold; and a protective layer formed on said conductor.
54.如权利要求53所述的方法,其中形成所述籽层图案的步骤包括:在所述防扩散层上形成一籽层;以及除去位于所述模层上的所述籽层的部分。 And removing said seed layer is located on the portion of the mold layer; forming a seed layer on said diffusion preventing layer: 54. The method of claim 53, wherein the step of forming the patterned seed layer comprises.
55.如权利要求54所述的方法,其中通过化学机械抛光工艺、内蚀刻工艺、或者化学机械抛光工艺和内蚀刻工艺的组合来进行除去所述籽层的所述部分。 55. Claim for the portion of the seed layer removing method according to claim 54, wherein the chemical mechanical polishing process, the etching process, or a combination of chemical mechanical polishing process and the etching process.
56.如权利要求53所述的方法,其中通过电解镀层工艺或非电镀层工艺形成所述导线。 56. The method of claim 53, wherein said conductor is formed by electrolytic plating or electroless plating layer process technology.
57.一种制造电感器的方法,包括以下步骤:在包括一导电结构的一基板上形成一模层,其中所述模层包括具有内表面的孔阵列;在所述孔阵列的内表面上和在所述模层上形成一防扩散层;在所述防扩散层上形成一第一籽层;在所述第一籽层上形成一帽盖层;在位于孔阵列中的所述帽盖层的部分上形成一第二籽层图案;从所述第二籽层图案形成导电图案以填充孔阵列;通过在所述模层上生长导电图案并连接所述导电图案而在所述模层上形成一导线;以及在所述导线上形成一保护层。 57. A method for manufacturing an inductor, comprising the steps of: forming a mold layer on a substrate comprising a conductive structure, wherein the mold layer comprises an inner surface having an array of apertures; on the inner surface of the hole array and a layer formed on said mold a diffusion preventing layer; a first seed layer is formed on the diffusion preventing layer; forming a cap layer on the first seed layer; said cap aperture array located forming a cap layer on a second portion of the seed layer pattern; conductive pattern to fill the array of holes are formed from the second seed layer pattern; by growing the conductive patterns on the mold layer and connecting the conductive pattern in the mold forming a conductor layer; and a protective layer formed on said conductor.
58.如权利要求57所述的方法,其中形成所述第二籽层图案的步骤包括:在所述帽盖层上形成一第二籽层;以及除去位于所述模层上的所述第二籽层的部分。 58. The method of claim 57, wherein said step of forming second seed layer patterns comprises: forming a second seed layer on the capping layer; and removing the first layer is on the mold Part two seed layer.
Description  translated from Chinese
用于芯片上系统的电感器及其制造方法 System and method for manufacturing the inductor chip for

技术领域 FIELD

本发明一般涉及一种电感器及制造该电感器的方法。 The present invention relates generally to a method of manufacturing the inductor and the inductor. 更具体地,本发明涉及一种用于芯片上系统(system-on-a-chip,SOC)的射频(RF)器件的电感器以及制造该电感器的方法。 More particularly, the present invention relates to an on-chip inductor system (system-on-a-chip, SOC) for radio frequency (RF) device, and a method of manufacturing the inductor.

要求享受于2003年11月6日提交的韩国专利申请No.2003-78195的优先权,该专利申请的全部公开内容在此引用作参考。 Claims the benefit of Korean Patent November 6, 2003, filed No.2003-78195 filed, the entire disclosure of this patent application is hereby incorporated by reference.

背景技术 BACKGROUND

SOC包括与系统所有元件一起集成的单个微芯片。 SOC include an integrated system with all components single microchip. 该系统的元件一般包括独立工作的半导体器件或电路。 Elements of the system typically comprises a semiconductor device or circuit to work independently. 例如,用于无线通讯的SOC一般包括微处理器、数字信号处理器(DSP)、随机存储器(RAM)器件和只读存储器(ROM)。 For example, SOC for wireless communications typically includes a microprocessor, a digital signal processor (DSP), a random access memory (RAM) devices and Read Only Memory (ROM). 通常,SOC元件集成在大规模集成(LSI)电路或集成电路(IC)上。 Typically, SOC components into large scale integration (LSI) circuit or an integrated circuit (IC) on.

在用于RF通讯的SOC中,半导体器件和RF电路通常集成在单个芯片上。 In the SOC for RF communication, semiconductor devices and RF circuits are generally integrated on a single chip. 在集成电路形成在半导体基板上之后,电感器一般形成在SOC的集成电路上。 After the integrated circuit is formed on a semiconductor substrate, the inductor is generally formed on the SOC of the integrated circuit. 具有螺旋或螺线管结构的薄膜型电感器通常使用在SOC中,因为它易于与集成电路结合。 Helical structure having a thin film or a solenoid type inductors typically used in the SOC, because it is easy to combine with the IC. 另外,薄膜型电感器用于各种器件,例如电压控制振荡器(VCO)、滤波器或逆变器。 In addition, the thin film inductor used in various devices, such as a voltage controlled oscillator (VCO), a filter or inverter.

传统的薄膜型电感器被公开在各种国家专利出版物中,例如包括韩国专利申请公开No.2003-20603,韩国专利No.348250和日本专利申请公开No.1998-241983。 Conventional film type inductor is disclosed in various national patent publications, for example, Korean Patent Application Publication No.2003-20603, Korean Patent No.348250 and Japanese Patent Application Publication No.1998-241983.

图1A到1C是示出在上面提到的韩国专利申请公开中公开的制造常规电感器的方法的横截面图。 1A to 1C is shown in the above-mentioned Korean patent application cross-sectional views showing a manufacturing method of a conventional inductor disclosed in the Publication.

参考图1A,软磁薄膜15形成在基板10上,该基板形成在硅晶片上。 1A, a soft magnetic thin film 15 formed on the substrate 10, the substrate is formed on a silicon wafer. 软磁薄膜15具有包括氮化铁钽(FeTaN)层和钛(Ti)层的双层结构。 Soft magnetic thin film 15 has a two-layer structure including iron tantalum nitride (FeTaN) layer and a titanium (Ti) layer.

氧化硅绝缘膜20形成在软磁薄膜15上,用于电镀工艺的籽层(seedlayer)25形成在绝缘膜20上。 Silicon oxide insulating film 20 is formed on the soft magnetic thin film 15, the seed layer (seedlayer) 25 for the plating process is formed on the insulating film 20. 籽层25具有包括铜(Cu)层和铬(Cr)层的双层结构。 Seed layer 25 has a two-layer structure including copper (Cu) layer and a chromium (Cr) layer.

光敏膜30沉积在籽层25上,然后掩模35形成在光敏膜30上。 The photosensitive film 30 is deposited on the seed layer 25, then a mask 35 is formed on the photosensitive film 30. 通过掩模35的图案将光敏膜30曝光。 Through a mask pattern 35 of the light sensitive film 30 exposed. 掩模35的图案限定了具有线圈结构的电感器。 The mask pattern 35 defines an inductor having a coil structure.

参考图1B,通过对光敏膜30的曝光部分显影,穿过光敏膜30形成多个孔。 1B, the photosensitive film 30 by developing the exposed portion, the photosensitive film 30 is formed through the plurality of holes. 这些孔使位于光敏膜30下面的籽层25暴露出。 These holes are located in the light-sensitive membrane so that the seed layer 30 exposed below 25. 电感器的线圈40从籽层25形成以填充这些孔。 The inductor coil 40 is formed to fill the holes from the seed layer 25. 线圈40通过使用包含铜的镀液的电镀工艺形成。 Coil 40 is formed by using an electroplating process comprising copper plating solution.

参考图1C,除去光敏膜30并使用湿蚀刻工艺蚀刻掉线圈40的环之间暴露出的籽层25的部分以在绝缘膜20上完成线圈40。 With reference to Figure 1C, a photosensitive film 30 is removed using a wet etching process and the coil is etched away to expose portions of the seed layer 25 between the rings 40 to complete the coil 20 on the insulating film 40. 使用环氧树脂粘结膜45将线圈40贴附到上部磁膜50上,以在基板10上形成电感器。 An epoxy resin adhesive film 45 is attached to the coil 40 on the upper magnetic film 50, to form the inductor on the substrate 10.

在上述制造常规电感器的方法中,线圈40从籽层25填充光敏膜30中的孔的生长速率随孔尺寸的增加而显著下降。 In the method of manufacturing a conventional inductor, the coil 40 from the growth rate of the seed layer 25 is filled in the hole the light sensitive film 30 increases with the pore size decreased significantly. 随电感器宽度和高度的增加,线圈生长速率相应减慢,因此电感器及相关RF器件的制造时间和成本提高。 With the increase of the width and height of the inductor, the rate of coil growth slows accordingly, so the manufacturing time and cost inductors and associated RF devices increase. 然而,电感器具有足够的宽度和高度以确保电感器的所需电特性是重要的。 However, the inductor has a sufficient width and height to ensure the desired electrical characteristics of the inductor is important.

发明内容 SUMMARY

本发明提供了一种根据简化工艺制造的用于SOC的电感器。 The present invention provides a simplified manufacturing process for the SOC of the inductor. 本发明也提供了一种使用简化的工艺制造用于SOC的电感器的低成本方法。 The present invention also provides a low cost method of using a simplified manufacturing process for the SOC of the inductor.

根据本发明的一个方案,一种电感器,包括形成在基板上的籽层和形成在籽层上的导线。 According to one aspect of the present invention, a inductor, comprising forming a seed layer on a substrate and forming a conductor on the seed layer. 导线通过连接多个从籽层生长的导电图案形成。 Wires formed from the seed layer is grown by connecting a plurality of conductive patterns. 优选在基板和籽层之间形成防扩散层,并优选在导线上形成保护层。 Preferably the seed layer between the substrate and the diffusion preventing layer is formed, and a protective layer is preferably formed on the wire. 另外,优选采用各自的导电图案填充包括孔阵列的模层。 In addition, preferred to use their own mold layer includes a conductive pattern fills the hole array.

根据本发明的另一个方案,一种电感器,包括:包含导电结构的基板、形成在基板上的籽层、形成在籽层上的模层以及形成在籽层上的导线。 According to another aspect of the invention, an inductor, comprising: a substrate comprising a conductive structure, forming a seed layer on the substrate, the seed layer is formed on the mold layer and forming a conductor on the seed layer. 模层包括暴露出籽层的孔阵列,导线电连接到导电结构。 The mold layer includes hole arrays exposing the seed layer, the wire is electrically connected to the conductive structure. 通过连接多个从籽层生长的导电图案而形成导线。 By connecting a plurality of the growth from the seed layer and a conductive pattern formed wire. 优选在导线上形成保护层。 The protective layer is preferably formed on the wire.

根据本发明的又一个方案,一种电感器,包括:包含导电结构的基板、包含具有形成在基板上的内表面上的孔阵列的模层、在孔阵内表面上形成的籽层以及在籽层形成的导线。 According to another aspect of the invention, a inductor, comprising: a substrate comprising a conductive structure, comprising an array of holes having a mold layer on the inner surface is formed on a substrate, the seed layer is formed on the inner surface of the hole array and in wire seed layer is formed. 导线电连接到导电结构并通过连接多个从籽层生长的导电图案而形成。 Leads electrically connected to the conductive structure and is formed by connecting a plurality of the growth from the seed layer conductive pattern.

根据本发明的又一个方案,一种电感器,包括:包含导电结构的基板、包含具有在基板上形成的内表面的孔阵列的模层、在孔阵列内表面上和在模层上形成的第一籽层、在第一籽层上形成的帽盖层、在位于孔阵列中的部分帽盖层上形成的第二籽层以及在第二籽层形成的导线。 According to another aspect of the invention, a inductor, comprising: a substrate comprising a conductive structure, having an inner surface comprising an array of holes in a mold formed on the substrate layer, and an array of apertures formed in the upper surface layer in the mold The first seed layer, a first capping layer on the seed layer, a second seed layer on the array of holes located in the portion of the cap layer and a conductor formed in the second seed layer is formed. 导线电连接到导电结构并通过连接多个从第二籽层生长的导电图案而形成。 Leads electrically connected to the conductive structure and is formed by connecting a plurality of the second seed layer is grown from the conductive pattern.

根据本发明的又一个方案,提供一种制造电感器的方法。 According to still another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包括在籽层上形成模层,其中模层包括暴露出籽层的孔阵列。 The method comprises forming a mold layer on a seed layer, wherein the mold layer includes hole arrays exposing the seed layer. 该方法进一步包括从籽层在模层上形成导电图案以填充孔阵列。 The method further comprises a conductive pattern to fill the hole arrays from the seed layer is formed on the mold layer. 该方法进一步包括通过在模层上生长导电图案并连接导电图案而在模层上形成导线。 The method further includes the growth of conductive patterns and connected by a conductive pattern on the mold layer is formed on the mold layer wire. 优选该方法进一步包括在模层上形成防反射层并在导线上形成保护层。 Preferably the method further comprises anti-reflection layer is formed on the mold layer and a protective layer formed on the conductor.

根据本发明的又一个方案,提供一种制造电感器的方法。 According to still another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包括在包括导电结构的基板上形成包括具有内表面的孔阵列的模层并且在孔阵列的内表面上和在模层上形成防扩散层。 The method includes forming an array of apertures comprising a mold having an inner surface layer on the substrate including the conductive structure and the diffusion preventing layer on the inner surface of the hole pattern formed on the mold layer. 该方法进一步包括在位于孔阵列中的部分防扩散层上形成籽层图案,并从籽层图案形成导电图案以填充孔阵列。 The method further comprises forming seed layer patterns on a portion located in the aperture array diffusion preventing layer, and the conductive pattern to fill the hole arrays formed from the seed layer patterns. 该方法还进一步包括通过在模层上生长导电图案和通过连接导电图案而在模层上形成导线并在导线上形成保护层。 The method further comprises by growing a conductive pattern on the mold layer and by connecting the conductive patterns on the mold to form a conductor layer and a protective layer formed on the conductor.

仍然根据本发明的另一个方案,提供一种制造电感器的方法。 According to still another aspect of the present invention, there is provided a method of manufacturing an inductor. 该方法包括在包括导电结构的基板上形成包括孔阵列的模层并且在孔阵列的内表面上和在模层上形成防扩散层。 The method comprises a mold layer comprising hole arrays and on the inner surface of the hole arrays and on the mold layer diffusion preventing layer is formed on the substrate comprises forming a conductive structure. 该方法进一步包括在防扩散层上形成第一籽层,并在第一籽层上形成帽盖层,并在位于孔阵列中的部分帽盖层上形成第二籽层。 The method further comprises forming a first diffusion preventing layer on the seed layer, and forming a capping layer on the first seed layer, and the second seed layer is formed on the array of holes located in the portion of the cap seal. 该方法还进一步包括从第二籽层图案形成导电图案以填充孔阵,在模层上生长导电图案并连接导电图案,由此在模层上形成导线,并在导线上形成保护层。 The method further comprises forming conductive patterns from the second seed layer patterns to fill the hole arrays, the mold layer is grown on the conductive pattern and connecting conductive patterns, thereby forming a wire on the mold layer, and a protective layer formed on the conductor.

根据本发明,通过使用电解工艺或非电镀层工艺,可以以相对低的成本很容易地制造包括螺旋导线的电感器。 According to the present invention, by using an electrolytic plating process or processes, may be relatively low cost easily manufactured comprises helix inductor. 通过使用电解工艺或非电镀层工艺(electroless plating process),调节导电图案的生长速率,将导线的宽度和高度调节到所需值。 By using the electrolytic plating process or process (electroless plating process), regulating the growth rate of the conductive pattern, the width and height of the wires adjusted to a desired value. 与传统的电感器的高度相比,导线的所需高度经常相对的高。 Compared with the conventional level of the inductor, the desired height of the wire is often relatively high. 调节导线的高度使得由本发明形成的电感器具有在基板上的相对高的螺旋结构。 Adjusting the height of the wire such that the inductor formed by the invention has a relatively high spiral structure on the substrate.

与形成电感器有关的制造时间和成本由于显著的裕度而潜在地降低,因为不需要用于将电感器与形成在基板上的下布线结构电连接的额外工艺。 And an inductor-related manufacturing time and cost due to the significant margin and potentially reduced, because the inductor is not required for the craft with an additional structure is formed on a lower wiring electrically connected to a substrate. 因此,优选电感器直接形成在常规基板上而没有任何另外的工艺,由此使用传统的制造电感器的制造装置,易于以低成本在基板上形成具有相对高的螺旋结构的电感器。 Thus, preferably the inductor is formed directly on a conventional substrate without any additional process, thereby using the conventional manufacturing apparatus for manufacturing an inductor, easy to be formed at low cost having a relatively high spiral structure on the substrate inductor.

附图说明 Brief Description

附图示出本发明几个选择的实施例。 The drawings illustrate embodiments of the present invention, several selected. 在图中:图1A到图1C是示出制造常规电感器的方法的横截面图;图2是示出根据本发明一个方案形成的典型电感器的平面图;图3A到图3E是沿图2的I到I'线切割的图2中所示的电感器的横截面图;图3A到图3E示出图2中所示电感器的制造方法;图4A是进一步示出图3B所示的掩模元件的平面图;图4B是进一步示出用于形成根据本发明的一个方案的导电图案的掩模的平面图;图5A是示出图3C中的导电图案的横截面的电子显微图;图5B是示出图3E中电感器平面图的电子显微图;图6是示出根据本发明的另一个方案的典型电感器的横截面图;图7A到图7E是示出图6中典型电感器的制造方法的横截面图;图8是示出图7C中的导电图案的横截面的电子显微图;图9A到图9E是示出根据本发明的另一个方案的电感器的制造方法的横截面图;图10A和图10B是示出图9D中的导电图案的横截面的电子显微图;图11是示出仍根据本发明的另一个方案的典型电感器的平面图;图12是沿II到II'线切割的图11中所示的电感器部分的横截面图;以及,图13A到图13D是示出图12中电感器的制造方法的横截面图。 In the drawings: FIG 1A to FIG 1C is a cross-sectional view illustrating a method of manufacturing a conventional inductor; FIG. 2 is a diagram showing a typical inductor formed in accordance with one aspect of the present invention, a plan view; FIGS. 3A to 3E is along 2 the I to I 'line of FIG cutting inductor shown in cross section in Fig. 2; Figs. 3A to 3E illustrate a method of manufacturing the inductor shown in FIG. 2; FIG. 4A is further illustrated in FIG. 3B a plan view of a mask element; Fig. 4B is a plan view further illustrating the conductive pattern according to an aspect of the present invention is used to form a mask; FIG. 5A is a diagram showing the cross-section of the conductive pattern 3C electron micrographs; 5B is a plan view illustrating the inductor electron micrograph of FIG. 3E; FIG. 6 is a cross sectional view of another typical inductor aspect of the present invention according to FIG.; FIG. 7A to FIG. 7E is a diagram showing a typical 6 a cross-sectional view of a manufacturing method of an inductor; FIG. 8 is a diagram showing a cross-sectional electron micrographs 7C in the conductive pattern; FIG. 9A to FIG. 9E is a diagram showing another aspect of the inductor of the present invention for producing a cross-sectional view of the method; Figs. 10A and 10B are diagrams showing a cross-sectional electron micrograph of Fig. 9D conductive pattern; FIG. 11 is a typical plan view illustrating still another aspect of the inductor according to the present invention; FIG. 12 is taken along line II to II 'line cross-sectional view cut FIG inductor portion 11 shown; and, FIG. 13A to FIG. 13D is a cross-sectional view illustrating a method of manufacturing the inductor 12 of FIG.

具体实施方式 DETAILED DESCRIPTION

现在参考附图更详尽地描述本发明,在附图中示出了本发明的几个实施例。 Several now be described in more detail with reference to the drawings the present invention, is shown in the drawings embodiments of the present invention. 在图中,为了清楚起见,层和区的厚度被放大,且全文中相同的附图标记表示相同的元件。 In the drawings, for clarity, the thickness of layers and regions are enlarged, and the full text of the same reference numerals denote the same elements. 可以理解当元件如层、区和基板被称作在另一元件“上”或“之上”时,该层即可直接在另一元件之上,也可具有插入元件。 Be understood that when an element such as a layer, region and the substrate is referred to as being "on" another element or being "on", the layer can be directly on the other element, or may have intervening elements present.

图2是示出根据本发明的一个方面的电感器的平面图。 Figure 2 is a plan view illustrating an inductor aspect of the present invention. 在图2中,电感器200包括螺旋导线190。 In Figure 2, an inductor 200 includes a helix 190. 螺旋导线190电连接到作为在基板上形成的下布线元件一部分形成的触头160。 Spiral electrical lead 190 is connected to the contact portion 160 is formed as a lower wiring element formed on a substrate. 所以,螺旋导线190位于包括触头160的下布线之上并以螺旋结构形成。 So, the helix is located includes over 190 contacts and 160 under the wire to form a spiral structure. 导线190优选通过连接从籽层(未示出)生长出的多个导电图案而形成。 By connecting wires 190 preferably from seed layer (not shown) is grown to form a plurality of conductive patterns.

电感器200一般包括在基板上形成的籽层。 Inductor 200 typically includes the seed layer formed on the substrate. 包括绝缘隔层或导电层的多层结构通常形成在基板和籽层之间。 Or a conductive layer including an insulating barrier multilayer structure is typically formed between the substrate and the seed layer.

图3A到图3E为沿图2中从I到I'延伸的线截取的横截面图。 3A to 3E is along 2 from I to I 'line extending in a cross-sectional view taken. 图3A到图3E示出图2电感器的制造方法。 Figures 3A to 3E illustrate a method of manufacturing an inductor of FIG. 2.

参考图3A,绝缘层150形成在包括下导电结构的基板(未示出)上。 3A, the insulating layer 150 is formed under the conductive structure comprises a substrate (not shown). 通过使用光刻工艺部分蚀刻绝缘层150,穿过绝缘层150形成开口155。 Partially etched by a photolithography process using the insulating layer 150, an opening 150 is formed through the insulating layer 155. 下导电结构一般包括字线、位线、导电图案和焊盘(pad)。 The lower conductive structure typically includes word lines, bit lines, the conductive pattern and the pad (pad). 开口155暴露出电连接到下导电结构的下布线(未示出)的一部分。 Exposing a portion of the opening 155 is electrically connected to the lower wiring (not shown) of the lower conductive structure.

导电层形成在绝缘层150上以填充开口155。 Conductive layer is formed on the insulating layer 150 to fill the opening 155. 导电层通常使用如金属或掺杂的多晶硅的导电材料形成。 The conductive layer is typically used such as metal or doped polysilicon is formed of a conductive material. 通过化学机械抛光(CMP)工艺、内蚀刻工艺(etch back process)、CMP工艺和内蚀刻工艺的组合、或者光刻工艺来部分地去除导电层,直到暴露出绝缘层150。 By chemical mechanical polishing (CMP) process, the etching process (etch back process), a combination of a CMP process and the etching process, or photolithography process to the conductive layer is partially removed until the insulating layer 150 is exposed. 作为部分去除导电层的结果,电连接到下布线的触头160形成在开口155中。 As a result of the removal of part of the conductive layer, a wiring electrically connected to the lower contact 160 is formed in the opening 155. 包括触头160的下布线电连接到位于基板上的下导电结构。 Lower wiring including the contact 160 is electrically connected to the lower conductive structure located on the substrate.

防扩散层165形成在触头160和绝缘层150上。 Diffusion preventing layer 165 is formed on the contact 160 and the insulating layer 150. 防扩散层165通常具有单层结构和多层结构。 Nonproliferation layer 165 typically has a single layer structure and a multilayer structure. 单层结构通常使用钽(Ta)、氮化钽(TaN)、氮化铝钽(TaAlN)、硅化钽(TaSi2)、钛(Ti)、氮化钛(TiN)、氮化硅钛(TiSiN)或氮化钨(WN)。 Single-layer structure typically use a tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN) or tungsten nitride (WN). 多层结构通常使用包括由钽(Ta)、氮化钽(TaN)、氮化铝钽(TaAlN)、硅化钽(TaSi2)、钛(Ti)、氮化钛(TiN)、氮化硅钛(TiSiN)和氮化钨(WN)构成的一组之中的的至少两种元素的混合物。 Typically by using a multilayer structure comprising tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium silicon nitride ( mixture TiSiN), and tungsten nitride (WN) among a group of at least two elements of the. 防扩散层165通常具有50到1000埃的厚度。 Diffusion prevention layer 165 typically has a thickness of from 50 to 1000 angstroms. 防扩散层165防止包含在导电图案185(参见图3C)中的铜扩散到下部结构。 Diffusion preventing layer 165 prevents the conductive pattern 185 comprises (see Fig. 3C) in the diffusion of copper into the substructure.

籽层170形成在防扩散层165上。 Seed layer 170 is formed on the non-proliferation layer 165. 籽层170通常由化学汽相沉积(CVD)工艺或如溅射工艺或真空蒸发工艺的物理汽相沉积(PVD)工艺形成。 Seed layer 170 is usually formed by a chemical vapor deposition (CVD) process or a physical vapor deposition such as a sputtering process or a vacuum evaporation process (PVD) process. 籽层170优选由PVD工艺形成,并具有大约100到5000埃的厚度。 Seed layer 170 is preferably formed of a PVD process and has a thickness of about 100 to 5000 Angstroms. 作为选择,籽层170使用导电材料形成,该导电材料基本上防止了诸如氧化膜或氮化膜的表面绝缘膜的形成。 Alternatively, the seed layer 170 is formed using a conductive material, the conductive material substantially prevents the formation of a surface insulation film such as an oxide film or nitride film. 例如,籽层170使用铂(Pt)、钯(Pd)、镍(Ni)、银(Ag)、金(Au)或其合金形成。 For example, the seed layer 170 using platinum (Pt), palladium (Pd), nickel (Ni), silver (Ag), gold (Au) or an alloy thereof.

光刻胶膜涂在籽层170上。 Photoresist film coated on the seed layer 170. 通过具有如图3B所示的多个孔的掩模220将光刻胶膜曝光。 Through a mask 220 having a plurality of holes as shown in FIG. 3B, the photoresist film is exposed. 光刻胶膜用作模层(mold layer)来形成导线190,如图3D所示。 The photoresist film used as a mold releasing layer (mold layer) to form a conductor 190, shown in Figure 3D. 光刻胶膜通常具有大约500到30000埃的厚度以充分长出导电图案185(参见图3C)。 Photoresist film typically has a thickness of about 500 to 30,000 angstroms to grow sufficiently conductive pattern 185 (see FIG. 3C).

图4A是进一步示出图3B中的掩模220的平面图。 4A is further illustrated in Figure 3B is a plan view of the mask 220.

参考图3B和4A,掩模220包括图案215,该图案具有以螺旋形设置的多个孔阵列,以形成具有导线190的电感器200。 With reference to FIG. 3B and 4A, the mask 220 includes a pattern 215, the pattern array having a plurality of holes arranged in a spiral to form a wire 190 having an inductor 200. 当使用掩模220对光刻胶膜曝光时,光刻胶膜按照掩模220的螺旋形形成多个孔阵列。 When using the mask 220 exposing the photoresist film, the photoresist film according to the mask 220 to form a plurality of spiral-shaped hole pattern. 在曝光的光刻胶膜显影之后,包括多个按照掩模220的螺旋形设置的沟道(trench)或孔阵列180的光刻胶图案175形成在籽层170上。 After the exposed photoresist film is developed, the photoresist pattern 180 includes a plurality of mask 220 in accordance with a spiral channel set (trench) or an array of holes 175 are formed on the seed layer 170.

虽然图4示出形成在掩模220中的一对螺旋形孔阵,但是孔阵的数量和尺寸是可以变化的,它根据电感器200的尺寸和结构变化。 Although Figure 4 shows mask 220 is formed in a pair of spiral-shaped hole arrays, but the number and size of aperture arrays may be varied, which changes the size and structure of the inductor 200.

图4B是显示用于形成根据本发明的一个具体实施例的导线的掩模230的平面图。 4B is a mask for forming the wire 230 in accordance with an example of a plan view of a specific embodiment of the present invention.

参考图4B,掩模230包括具有多个根据电感器结构螺旋设置的沟道的图案225。 4B, the mask 230 includes a plurality of spiral inductor structure according to the channel set pattern 225. 沟道的尺寸和数量根据电感器的尺寸和结构变化。 Size and number of the channel changes according to the size and structure of the inductor.

现在参考图3B,使用掩模220对光刻胶膜曝光和显影,结果,具有孔阵列180的光刻胶图案175形成在籽层170上。 Referring now to Figure 3B, the photoresist film using the mask 220 exposing and developing, the results, having an array of apertures 180 of the photoresist pattern 175 is formed on the seed layer 170. 沟道或孔阵列180部分地暴露出籽层170。 Channel or hole arrays 180 partially expose seed layer 170. 沟道或孔阵180优选具有大约500到30000埃的深度。 Channel or hole arrays 180 preferably have a depth of about 500 to 30,000 Angstroms.

根据本发明的一个方面,防反射层(ARL)形成在光刻胶膜上以保证光刻工艺的工艺裕度(process margin)。 According to one aspect of the invention, the antireflection layer (ARL) is formed on the photoresist film in order to ensure a process margin of a photolithography process (process margin). 通过使用ARL作为蚀刻掩模对光刻胶膜构图,然后在籽层170上形成光刻胶图案175。 By using the ARL as an etching mask for patterning the photoresist film, the photoresist pattern 175 is then formed on the seed layer 170. ARL一般具有大约50到1000埃的厚度。 ARL typically has a thickness of about 50 to 1000 Angstroms.

在本发明的另一个方面中,考虑到连续的蚀刻工艺,在籽层170上形成蚀刻阻止层。 In another aspect of the present invention, taking into account the continuous etching process, the etching stop layer 170 is formed on the seed layer. 然后在蚀刻阻止层上形成光刻胶图案175。 Photoresist pattern 175 is then formed on the etching stop layer. 蚀刻阻止层通常使用氮化物,例如氮化硅,形成。 The etching stop layer is generally a nitride, such as silicon nitride, is formed.

参考图3C,通过电解镀层工艺(electrolytic plating process)从籽层170将多个导电图案185形成在光刻胶图案175上,以填充沟道或孔阵列180。 3C, the electrolytic plating process (electrolytic plating process) from the seed layer 170. The plurality of conductive patterns 185 is formed on the photoresist pattern 175, to fill the trench or hole arrays 180. 通常采用大约20到40mA/cm2的电流密度并使用包括硫酸铜(CuSO4)溶液、硫酸(H2SO4)溶液以及包括氯离子(Cl-)的溶液的镀液进行电解镀层工艺。 Usually about 20 to 40mA / cm2 current density and electrolytic plating process includes copper sulfate (CuSO4) solution, sulfuric acid (H2SO4) solution, and include chloride (Cl-) of the solution and the bath was. 导电图案185按照图3C中箭头所示的方向从籽层170生长,使得在光刻胶图案175上形成导电图案185的上部。 Conductive pattern 185 in the direction shown by the arrow in FIG. 3C grown from the seed layer 170, so that the upper conductive pattern 185 is formed on the photoresist pattern 175. 当导电图案185从籽层170在孔阵列180中生长时,在相对于基板的垂直方向上在孔阵列180中的生长加快,而沿相对于基板的水平方向在孔阵列180中的生长受到限。 When the conductive pattern 185 when the seed layer 170 is grown in the hole arrays 180 from the vertical direction with respect to the growth substrate in an array of apertures 180 in the accelerated along the horizontal direction with respect to the growth substrate in an array of apertures 180 is limited . 一旦导电图案185充满孔阵列180,则导电图案185的上部在光刻胶图案175上形成凸起。 Once the conductive patterns 185 fill the pores of the array 180, the upper conductive pattern 185 of the photoresist pattern 175 is formed on the projection.

参考图3D,用于形成图3C的导电图案185的电解镀层工艺被延续以在光刻胶图案175上形成导线190。 With reference to FIG. 3D, the conductive pattern 185 of FIG. 3C electrolytic plating process is used to form a continuation of the photoresist pattern 175 is formed on the conductor 190. 换句话说,在光刻胶图案175上导电图案185垂直和水平生长,直到导电图案185彼此连接,由此在光刻胶图案175上形成导线190。 In other words, the photoresist pattern 175 on the conductive patterns 185 grow vertically and horizontally, until the conductive pattern 185 connected to each other, thereby forming a conductor 190 on the photoresist pattern 175. 当由延续电解镀层工艺形成导线190时,导线190的上部通常具有蘑菇状。 When formed by a continuation of the electroless plating process leads 190, 190 of the upper wire usually has a mushroom shape.

现在给出用于形成导线190的工艺概要,它包括一些额外的细节。 Forming process will now be given of the outline of the wire 190, including some additional details. 导电图案185从籽层170垂直生长。 Conductive pattern 185 vertical growth from the seed layer 170. 接下来,导电图案185在光刻胶图案175上水平和垂直生长,如图3C和图3D所示。 Next, a conductive pattern 185 on the photoresist pattern 175 in the horizontal and vertical growth, as shown in FIGS. 3C and 3D. 然后根据它们的垂直和水平生长,邻近的导电图案185在光刻胶图案175上彼此连接,导致导线190的形成。 Then according to their vertical and horizontal growth, the adjacent conductive pattern 185 on the photoresist pattern 175 is connected to each other, resulting in the formation of the wire 190. 通过调节导电图案185的垂直和水平生长,将导线190的宽度和厚度调整到所需值。 By adjusting the conductive pattern 185 of the vertical and horizontal growth, will adjust the width and thickness of the wire 190 to the desired value. 为了获得此结果,一旦它们已经充满孔阵列180时,延续执行电解镀层工艺以进一步使导电图案185生长。 To obtain this result, once they have been filled with an array of holes 180, and continued to perform an electroless plating process to further the growth of the conductive pattern 185. 进一步的生长使得邻近的导电图案185彼此连接,由此在光刻胶图案175上形成导线190。 Further growth such that adjacent conductive pattern 185 connected to each other, thereby forming a conductor 190 on the photoresist pattern 175. 为了使导线190形成具有所需的宽度和厚度,在充满孔阵列180后对导电图案185的生长进行有利地调节。 In order to make the wire 190 is formed having the desired width and thickness, and after full array of holes 180 on the growth of the conductive pattern 185 will be advantageously adjusted. 导线190优选具有约1000到100000埃的厚度。 Wire 190 preferably has a thickness of about 1000 to 100,000 Angstroms. 通常导线190在光刻胶图案175上具有足够的厚度,因为导电图案185的水平生长在孔阵列180是受限制的。 Typically wire 190 has a sufficient thickness on the photoresist pattern 175, since the horizontal growth of the conductive pattern 185 in an array of apertures 180 is restricted.

参考图3E,除了位于导线190下面的一部分光刻胶图案175,光刻胶图案175被部分去除。 Referring to FIG. 3E, in addition to the wire 190 is located in the following part of the photoresist pattern 175, the photoresist pattern 175 is partially removed. 当光刻胶图案175被部分去除时,籽层170被部分暴露出。 When the photoresist pattern 175 is partially removed, the seed layer 170 is partially exposed. 部分除去暴露出的籽层170和防扩散层165以完成成具有螺旋结构的导线190。 Partially removing the seed layer 170 and diffusion prevention layer 165 is exposed to complete a wire 190 having a spiral structure. 通过湿蚀刻工艺,部分除去光刻胶图案175、籽层170和防扩散层165。 By a wet etching process, part of the photoresist pattern 175 is removed, seed layer 170 and the diffusion preventing layer 165. 使用有机剥离剂(stripper)、包括浓度相当高的臭氧(O3)的溶液、或包括二氧化碳(CO2)的标准清洁(SC)溶液进行湿蚀刻工艺。 An organic release agent (stripper), including a relatively high concentration of ozone (O3) solution, or comprise carbon dioxide (CO2) in the standard cleaning (SC) solution of a wet etching process. 作为选择,光刻胶图案175可以通过抛光工艺或剥离(stripping)工艺部分去除。 Alternatively, the photoresist pattern 175 may (stripping) process is partially removed by polishing process or peeling. 在本发明的一个实施例中,可以使用氟化氢(HF)溶液和过氧化氢(H2O2)溶液的混合物或氟化氢(HF)溶液和硝酸(HNO3)溶液的混合物部分去除籽层170和防扩散层165。 In one embodiment of the present invention may be used hydrogen fluoride (HF) solution and hydrogen peroxide (H2O2) solution or a mixture of hydrogen fluoride (HF) solution and a nitric acid (HNO3) solution of a mixture of partially removing the seed layer 170 and diffusion prevention layer 165 . 当在光刻胶图案175上形成ARL时,同时去除ARL和光刻胶图案175。 When forming a photoresist pattern on the 175 ARL, ARL and simultaneous removal of the photoresist pattern 175.

形成保护层195以包围导线190,由此完成电感器200,其优选包括多个导线190。 The protective layer 195 is formed to surround the lead 190, thereby completing the inductor 200, which preferably comprises a plurality of wires 190. 电感器200具有由多个导线190形成的螺旋结构。 Inductor 200 has a spiral structure formed by a plurality of wires 190. 一般使用碳化硅(SiC)或氮化硅(SiN)形成保护层195。 Typically silicon carbide (SiC) or silicon nitride (SiN) protective layer 195 is formed. 作为选择,保护层195具有包括碳化硅、氮化硅和碳氧化硅的至少两层膜的多层结构。 Alternatively, the protective layer 195 has a multilayer structure comprising silicon carbide, silicon nitride and silicon oxycarbide of at least two films. 保护层195优选具有约100到1000埃的厚度。 The protective layer 195 preferably has a thickness of about 100 to 1000 Angstroms. 保护层195形成在防扩散层165的剩余部分的侧壁上、籽层170的剩余部分的侧壁上、光刻胶图案175的剩余部分的侧壁上,以及形成在螺旋结构的导线190上。 The protective layer 195 is formed on the remaining portion of the sidewall of the diffusion preventing layer 165, the remaining portion of the sidewall seed layer 170, the sidewalls of the remaining portion of the photoresist pattern 175, is formed on the conductor 190 and the helical structure .

图5A是显示图3C中的导电图案的横截面的电子显微照片;图5B是显示图3E中电感器平面图的电子显微照片;参考图5A和图5B,通过上述电解镀层工艺导电图案185垂直和水平生长,以在光刻胶图案175上形成包括螺旋导线190的电感器200。 Figure 5A is an electron photomicrograph of a cross-section of FIG. 3C conductive pattern; FIG. 5B is a plan view of the inductor in FIG. 3E electron micrograph; 5A and 5B, the electroless plating process by the above-mentioned conductive pattern 185 vertical and horizontal growth, to form a helix 190 comprising an inductor 200 on the photoresist pattern 175. 每个导电图案185具有蘑菇状的上部。 Each of the conductive pattern 185 having a mushroom-shaped upper portion.

图6是显示根据本发明的一个方面的电感器的横截面图。 Figure 6 is a cross-sectional view of the inductor of one aspect of the present invention. 根据该方面,导线的制造方法包括与参考图3A到图3D描述的工艺相同的工艺。 According to this aspect, a method of manufacturing the wire includes reference to Figures 3A to 3D describe the same process technology.

参考图6描述电感器300的制造方法。 Figure 6 depicts the manufacturing method with reference to the inductor 300. 在具有绝缘层250的基板上制造电感器300,如以上所述那样该绝缘层具有穿过它的触头260。 Manufacturing inductor on a substrate 300 having an insulating layer 250, as described above, as the insulating layer having a contact 260 therethrough. 完全除去用于形成导线290的光刻胶图案,部分除去籽层270和防扩散层265。 Wire 290 is completely removed for forming a resist pattern, removing the seed layer portions 270 and the diffusion preventing layer 265. 于是暴露出导线290的下部。 Thus exposing lower wires 290.

保护层295形成在绝缘层250上、暴露出的籽层270和防扩散层265上、以及导线290上。 The protective layer 295 is formed on the insulating layer 250, the seed layer 270 and the diffusion preventing layer 265 exposed, and the wires 290. 保护层295通常具有由碳化硅、碳氧化硅或氮化硅构成的单层结构,或具有从碳化硅、碳氧化硅或氮化硅构成的组中选择的若干层的多层结构。 The protective layer 295 typically has a single layer structure made of silicon carbide, silicon oxycarbide or silicon nitride, or with a group from silicon carbide, silicon oxide or silicon nitride is selected from a plurality of layers of the multilayer structure. 从导线290的上部到绝缘层265形成保护层295,借此完全包围导线290。 265 protective layer 295 is formed from the upper wire to the insulating layer 290, thereby completely surrounds the wires 290.

图7A到图7E是显示图6中电感器的制造方法的横截面图。 7A to 7E is a cross-sectional view of a method of manufacturing the inductor of FIG. 6. 在图7A到图7E中,未示出包括具有字线、位线和焊盘的下导电结构的基板。 In Figures 7A-7E, the substrate comprises a not shown word lines, bit lines and pads of the lower conductive structure.

参考图7A,绝缘层350形成在基板上。 With reference to FIG. 7A, the insulating layer 350 is formed on the substrate. 部分蚀刻绝缘层350以形成暴露出电连接到下导电结构的下布线的开口355。 Partially etched to expose the insulating layer 350 to form a lower wiring electrically connected to the lower conductive structure opening 355.

在绝缘层350上形成导电层以填充开口355。 Forming a conductive layer on the insulating layer 350 to fill the opening 355. 导电层可以使用金属或掺杂的多晶硅形成。 The conductive layer may be a metal or doped polysilicon. 然后通过CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合部分去除导电层。 Then by a CMP process, etching process or a combination portion of the inner CMP process and an etching process to remove the conductive layer. 部分去除导电层直到暴露出绝缘层350。 Removing the exposed portion of the conductive layer until the insulating layer 350. 于是,在开口355中形成电连接到下布线的触头360。 Thus, the wiring electrically connected to the lower contact 360 is formed in the opening 355. 包括触头360的下布线电连接到在基板上形成的下导电结构。 Lower wiring including the contact 360 is electrically connected to the lower conductive structure formed on the substrate.

在绝缘层350和触头360上形成模层365。 Formed on the insulating layer 350 and the contact layer 360 mold 365. 模层365可以使用氧化物或光刻胶形成。 Mold layer 365 may be used to form an oxide or a photoresist. 部分蚀刻模层365以形成多个暴露出如上所述的触头360的沟道或孔阵列370。 Partially etching the mold layer 365 to form a channel or a plurality of holes 360 exposes an array of contacts 370 as described above. 模层365通常具有约500到30000埃的厚度,从而容易形成导线400(参见图7D)并使下导电结构与导线400充分绝缘。 The mold layer 365 typically has a thickness of from about 500 to 30,000 Angstroms, thereby easily forming a conductor 400 (see FIG. 7D) and the lower conductive structure 400 fully insulated wires.

当使用氧化物形成模层365时,在模层365上另外形成光刻胶膜。 When the mold layer 365 is formed using oxide, the mold layer 365 in addition to form a photoresist film. 使用如图4A或图4B所示的掩模将光刻胶膜曝光,以形成包括多个孔阵列或沟道的光刻胶图案。 Using the mask shown in FIG. 4A or 4B, the resist film is exposed, to form a photoresist pattern including a plurality of apertures or an array channel. 在光刻胶膜上另外形成约50到1000埃厚的ARL后,在模层365上形成光刻胶图案。 After the addition is formed on the photoresist film from about 50 to 1000 angstroms thick ARL, the mold layer 365 is formed on the photoresist pattern. 接着,使用光刻胶图案作为掩模蚀刻模层365,由此形成具有深度为500到1000埃并穿过模层365的沟道或孔阵列370。 Next, using the photoresist pattern as a mask mold layer 365 is etched, thereby forming a depth of 500 to 1,000 angstroms and a channel or hole passing through the mold layer 365 in the array 370.

当使用光刻胶形成模层365时,优选使用图4A或图4B中的掩模直接曝光模层365,从而形成穿过模层365的沟道或孔阵列370,其中沟道或孔阵列370具有内表面。 When using the photoresist layer 365 during molding, preferably using a mask in FIG. 4B or FIG. 4A directly exposing the mold layer 365, thereby forming the mold layer 365 through the channel or hole arrays 370, wherein the channel or hole arrays 370 having an inner surface.

参考图7B,防扩散层375形成在模层365上、触头360上以及沟道或孔阵列370的内表面上。 With reference to FIG. 7B, the diffusion preventing layer 375 is formed on the mold layer 365, the upper contact 360 and the inner surface of the channel or bore 370 of the array. 防扩散层375具有约50到1000埃的厚度。 Nonproliferation layer 375 has a thickness of about 50 to 1000 Angstroms. 防扩散层375通常具有单层结构或多层结构。 Diffusion prevention layer 375 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛以及其合金构成的组中的至少两种成分(element)。 Multilayer structure typically includes at least two the group consisting of tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium, and alloys thereof consisting of component (element).

通过CVD工艺或如溅射工艺或真空蒸发工艺的PVD工艺,第一籽层380形成在防扩散层375上。 By a CVD process or PVD processes such as sputtering or vacuum evaporation process, the first seed layer 380 is formed on the non-proliferation layer 375. 第一籽层380具有大约100到5000埃的厚度。 The first seed layer 380 has a thickness of about 100 to 5000 Angstroms. 第一籽层380优选使用铜、铂、钯、镍、银、金或其合金形成。 The first seed layer 380 is preferably formed using copper, platinum, palladium, nickel, silver, gold or an alloy thereof.

使用如铝的金属在第一籽层380上形成帽盖层385。 Using a metal such as aluminum capping layer 385 is formed on the first seed layer 380. 帽盖层385具有约100到500埃的厚度。 Cap layer 385 having a thickness of about 100 to 500 . 当除去在模层365上的部分籽层390时,作为帽盖层385中金属氧化的结果,在帽盖层385上形成金属氧化膜。 When the mold layer 365 is removed in the portion of the seed layer 390, the capping layer 385 as a result of oxidation of the metal, the cap layer 385 on the metal oxide film is formed. 即,除了形成在孔阵列370中的帽盖层385的其它部分,帽盖层385的上部转换成金属氧化物绝缘膜,使得帽盖层385可以选择性地限制导电图案395的生长。 That is, in addition to other portions are formed in an array of apertures 370 in the cap layer 385, an upper capping layer 385 is converted into a metal oxide insulating film, so that the capping layer 385 may selectively limit the growth of the conductive pattern 395. (参见图7C)。 (See Fig. 7C). 所以,导电图案395可以在孔阵列370中快速生长,而导电图案395可以在帽盖层385的金属氧化膜上缓慢生长。 Therefore, the conductive patterns 395 may rapidly grow in the hole arrays 370, whereas the conductive patterns 395 may slowly grow on the metal oxide film cap layer 385. 使用铜、铂、钯、镍、银、金或其合金在帽盖层385上形成第二籽层390。 The second seed layer 390 is formed on the capping layer 385 using copper, platinum, palladium, nickel, silver, gold or an alloy thereof.

参考图7C,为了进行选择性的电解镀层工艺,通过CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合除去一部分位于模层365上的第二籽层390。 With reference to Figure 7C, in order to carry out selective electroless plating process, by a CMP process, etching process or a combination of the CMP process and the etching process of removing a portion located on the mold layer 365 on the second seed layer 390. 结果,第二籽层图案393形成在孔阵列370的内表面上。 As a result, the second seed layer pattern 393 is formed on the inner surface of the array of holes 370. 在孔阵列370的内表面上依次形成防扩散层375、第一籽层380、帽盖层385和第二籽层图案393,而在模层365上不形成第二籽层图案393。 On the inner surface of the aperture array 370 are sequentially formed diffusion preventing layer 375, a first seed layer 380, cap layer 385 and the second seed layer patterns 393, and on the mold layer 365 is not formed a second seed layer patterns 393.

通过使用选择性电解镀层工艺,导电图案395从第二籽层图案393选择性地并垂直地生长,以填充孔阵列370。 By using the selective electroless plating process, conductive patterns 395 and vertically grown from the second seed layer 393 is selectively patterned to fill the hole arrays 370. 使用约20到40mA/cm2的电流密度和使用包括硫酸铜溶液、硫酸溶液以及包含氯离子的电镀溶液进行电解镀层工艺。 Using about 20 to 40mA / cm2 current density and the use of a solution comprising copper sulfate, sulfuric acid solution and the plating solution contains chloride ions in an electrolytic plating process. 如上所述,由于导电图案395的水平生长被限制在孔阵列370中,所以导电图案395在孔阵列370中从第二籽层图案393垂直生长。 As described above, since the horizontal growth of the conductive patterns 395 is limited in the hole arrays 370, so that the conductive pattern 395 in the array of apertures 370 in the vertical growth from the second seed layer patterns 393. 当连续地进行选择性的电解镀层工艺时,填充孔阵列370的导电图案395在模层365上水平地和垂直地生长。 When the continuous selective electroless plating process, conductive patterns 370 filling the hole arrays 395 on the mold layer 365 horizontally and vertically grow. 包含金属氧化膜的帽盖层385限制在孔阵列370中的导电图案395的水平生长。 Cap layer 385 comprises a metal oxide film is limited to an array of apertures 370 in the conductive pattern 395 of the horizontal growth. 然而,因为由于帽盖层385在孔阵列370的上部形成瓶颈结构,所以在用导电图案395充满孔阵列370之后,导电图案395水平和垂直生长。 However, because the capping layer 385 due to an array of apertures 370 in the upper structure forming a bottleneck, so after the conductive pattern 395 is filled with an array of apertures 370, the conductive patterns 395 grow horizontally and vertically. 充满孔阵列370的导电图案395在如箭头所指示的水平和垂直方向上连续地生长,使得相邻的导电图案395彼此连接,形成具有所需宽度和高度的导线400。 Full aperture array 370 conductive pattern 395 in the horizontal and vertical directions as indicated by the arrow to grow continuously, so that adjacent conductive patterns 395 connected to each other to form a wire 400 having a desired width and height.

图8是示出图7C中的导电图案的横截面的电子显微图。 Figure 8 is an electron micrograph shown in Fig. 7C is a cross-section of the conductive pattern.

如图7C和图8所示,虽然导电图案395的水平生长在孔阵列370中受到限制,但在充满孔阵列370之后导电图案395仍然在垂直和水平方向都生长。 Fig. 7C and 8, although the horizontal growth of the conductive patterns 395 is limited in the hole arrays 370, but after the full array of holes 370 conductive pattern 395 is still in the vertical and horizontal directions are grown. 结果,相邻的导电图案395彼此连接,从而形成导线400。 As a result, adjacent conductive patterns 395 connected to each other, thereby forming wire 400.

参考图7D,具有所需宽度和高度的导线400通过连接相邻的导电图案395自第二籽层图案393形成在模层365上。 With reference to FIG. 7D, having the desired width and height of the wire 400 by connecting adjacent conductive patterns 395 from the second seed layer pattern 393 is formed on the mold layer 365. 导电图案395通过连续进行电解镀层工艺被连接。 The conductive pattern 395 is connected by a continuous electrolytic plating process. 在导电图案395充满孔阵列370后,可以有利地调节导电图案395的生长速率,以形成具有大约1000到100000埃高度的导线400。 After the conductive patterns 395 fill the pores of the array 370, can advantageously be adjusted growth rate of conductive patterns 395, to form a wire having a height of about 400 angstroms 1000-100000.

参考图7E,除了被导线400覆盖的部分,部分地除去帽盖层385、第一籽层380和防扩散层375。 Referring to FIG. 7E, in addition to part of the wire 400 is covered partially removed the cap layer 385, the first seed layer 380 and the non-proliferation layer 375. 形成保护层405以覆盖导线400,由此形成具有包括多个导线400的螺旋结构的电感器430。 The protective layer 405 is formed to cover the conductor 400, thereby forming an inductor having a spiral structure comprising a plurality of conductors 400 430. 可以使用氟化氢溶液和过氧化氢溶液的混合物或氟化氢溶液和硝酸溶液的混合物部分地去除帽盖层385、第一籽层380和防扩散层375。 You can use the hydrogen fluoride solution and hydrogen peroxide solution or a mixture of hydrogen fluoride solution and nitric acid solution of a mixture of partially removing the cap layer 385, a first seed layer 380 and the diffusion preventing layer 375.

在本发明的一个实施例中,在去除模层365后,在导线400上形成保护层405。 In one embodiment of the present invention, after removal of the mold layer 365, protective layer 400 on the conductor 405 is formed. 当使用光刻胶形成模层365时,优选使用有机去除剂、包含相当高浓度的臭氧的溶液、或包含二氧化碳的SC溶液除去模层365。 When using the photoresist layer 365 during molding, preferably a solution comprising carbon dioxide removed SC mold layer 365 is removed using an organic agent, containing a fairly high concentration ozone solution, or. 当使用氧化物形成模层365时,优选通过使用硫酸溶液的湿蚀刻工艺或如活性离子蚀刻工艺或等离子体蚀刻工艺的干蚀刻工艺除去模层365。 When the mold layer 365 is formed using an oxide, it is preferable to use a wet etching process through a sulfuric acid solution or a dry etching process such as reactive ion etching process or a plasma etching process for removing the mold layer 365.

参考图7E,优选使用碳化硅或氮化硅形成保护层405。 With reference to Figure 7E, the protective layer 405 is preferably formed using silicon carbide or silicon nitride. 保护层405具有约100到1000埃的厚度。 The protective layer 405 having a thickness of about 100 to 1000 Angstroms. 保护层405覆盖暴露出的导线400下面的帽盖层385、第一籽层380和防扩散层375的侧壁。 A protective layer covering the exposed wire 405 400 below the cap layer 385, the first seed layer 380 and the sidewall diffusion barrier 375.

在本发明的一个实施例中,保护层405具有包括由碳化硅、氮化硅和碳氧化硅构成的组中的至少一种成分的多层结构。 In one embodiment of the present invention, the protective layer 405 having a multilayer structure comprising the group consisting of silicon carbide, silicon nitride and silicon oxycarbide consisting of at least one component.

图9A到图9E是示出根据本发明的一个方案的电感器的制造方法的横截面图。 Figures 9A-9E is a cross-sectional view illustrating a method of manufacturing an inductor of the present invention.

参考图9A,绝缘层450形成在包括下导电结构的基板上。 With reference to FIG. 9A, the insulating layer 450 is formed on a substrate including a lower conductive structure. 绝缘层450优选使用氧化物或氮化物形成。 Insulating layer 450 is preferably formed using oxide or nitride. 通过光刻工艺部分蚀刻绝缘层450,然后穿过绝缘层450形成开口455。 Partially etched through a photolithography process the insulating layer 450, and then through the insulating layer 450 is formed an opening 455. 下导电结构一般包括字线(word line)、位线(bitline)和焊盘。 The lower conductive structure typically includes word lines (word line), a bit line (bitline) and the pad. 开口455暴露出电连接到下导电结构的下布线。 455 exposes a lower wiring electrically connected to the opening of the lower conductive structure.

金属或掺杂多晶硅的导电层形成在绝缘层450上以填充开口455。 Metal or doped polysilicon conductive layer is formed on the insulating layer 450 to fill the opening 455. 通过CMP工艺、内蚀刻工艺、CMP工艺和内蚀刻工艺的组合来部分去除导电层,从而在开口455中形成触头460。 By a CMP process, a combination of the etching process, CMP process and the etching process to the conductive layer is partially removed, thereby forming a contact 460 in the opening 455. 触头460电连接到下布线。 Contact 460 is electrically connected to the lower wiring. 因此,包括触头460的下布线电连接到下导电结构。 Therefore, the lower wiring including the contact 460 is electrically connected to the lower conductive structure.

具有约500到30000埃厚度的模层465形成在绝缘层450和触头460上。 Having a thickness of from about 500 to 30,000 angstroms of the mold layer 465 is formed on the insulating layer 450 and the contact 460. 可以使用氧化物或光刻胶形成模层465。 You can use the mold to form an oxide or a photoresist layer 465. 部分蚀刻模层465以形成暴露出如上所述的触头460的多个沟道或孔阵列470。 Partially etching the mold layer 465 to form a plurality of channels, or an array of apertures 470 to expose contacts 460 as described above. 沟道或孔阵列470具有1000到30000埃的深度。 Channel or hole arrays 470 having depth of 1000 to 30000 angstroms.

当使用氧化物形成模层465时,在模层465上另外形成光刻胶膜。 When the mold layer 465 is formed using oxide, the mold layer 465 in addition to form a photoresist film. 使用如图4A和图4B所示的一种掩模将光刻胶膜曝光,以形成包括多个孔阵列或沟道的光刻胶图案。 Using a mask as shown in FIG. 4A and 4B the resist film is exposed, to form a photoresist pattern including a plurality of apertures or an array channel. 在光刻胶膜上通常也形成约50到1000埃厚的ARL,然后在模层465上形成光刻胶图案。 Is also formed on the photoresist film is generally from about 50 to 1000 angstroms thick ARL, and then forming a resist pattern on the mold layer 465. 接着,使用光刻胶图案作为蚀刻掩模蚀刻模层465,由此形成穿过模层465的沟道或孔阵列470。 Next, using the photoresist pattern as an etch mask layer 465 is etched mold, thereby forming the mold layer 465 through the channel or hole arrays 470.

当使用光刻胶形成模层465时,优选使用图4A或图4B中的一种掩模直接曝光模层465而不形成另外的光刻胶膜,由此形成穿过模层465的沟道或孔阵列470,其中沟道或孔阵列470具有内表面。 When using the photoresist layer 465 during molding, preferably using a mask in FIG. 4A or FIG. 4B without directly exposing the mold layer 465 to form additional photoresist film, thereby forming a channel through the mold layer 465 or aperture array 470, wherein the channel or hole arrays 470 having an inner surface. 优选在模层465上形成另外的ARL以保证光刻工艺的工艺裕度。 Additional ARL is preferably formed on the mold layer 465 to ensure a process margin in a photolithography process.

参考图9B,具有约50到1000埃厚度的防扩散层475形成在模层465上、触头460上以及孔阵列470的内表面上。 Referring to FIG. 9B, with a thickness of about 50 to 1000 nonproliferation layer 475 is formed on the mold layer 465, on the inner surface of the contact holes 460 and 470 of the array. 防扩散层475通常具有单层结构或多层结构。 Diffusion prevention layer 475 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛以及其合金构成的组的至少两种成分。 Multilayer structure generally includes a group consisting of tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium, and alloys composed of at least two components .

通过CVD工艺或如溅射工艺或真空蒸发工艺的PVD工艺,具有大约100到5000埃的厚度的籽层480形成在防扩散层475上。 By a CVD process or a PVD process such as a sputtering process or a vacuum evaporation process, a seed layer having a thickness of about 100 to 5000 angstroms 480 is formed on the diffusion preventing layer 475. 籽层480优选使用铜、铂、钯、镍、银、金或其合金形成。 Seed layer 480 is preferably formed using copper, platinum, palladium, nickel, silver, gold or an alloy thereof.

参考图9C,在触头460上和在位于孔阵列470内表面的防扩散层475上形成籽层图案483以实现选择性非电镀层工艺。 Referring to FIG. 9C, the contacts 460 and 483 to form a patterned seed layer to achieve a non-selective plating process on an array of holes located on the inner surface of the non-proliferation layer 470 475. 通过使用CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合部分除去籽层480直到暴露出防扩散层475来形成籽层图案483。 By using a CMP process, etching process or a combination of the inner part of the CMP process and the etching process is removed to expose the seed layer 480 until the diffusion prevention layer 475 to form patterned seed layer 483. 结果,防扩散层475和籽层图案483被定位在孔阵列470的内表面上,而只有防扩散层475位于模层465上。 As a result, the diffusion preventing layer 475 and the seed layer patterns 483 are positioned on the inner surface of the hole arrays 470, whereas only the diffusion preventing layer 475 is located on the mold layer 465.

参考图9D,使用选择性非电镀层工艺,从籽层图案483形成导电图案485,以填充孔阵列470。 Referring to FIG. 9D, the use of non-selective plating process, from the seed layer is patterned to form a conductive pattern 483 485 470 to fill the hole array. 使用包含如甲醛或联氨的还原剂的硫酸铜溶液进行非电镀层工艺。 Using copper sulfate solution containing a reducing agent such as formaldehyde or hydrazine of the non-plating process. 如上所述,因为在孔阵列470中导电图案485的水平生长受到限制,导电图案485在孔阵列470中从籽层图案483垂直生长。 As described above, since the horizontal holes 470 in the array 485 of the conductive pattern growth is restricted, the conductive pattern 485 in the hole arrays 470 from the seed layer patterns 483 grow vertically. 当继续进行非电镀层工艺时,导电图案485充满孔阵列470,然后在模层465上水平和垂直生长。 When a non-plating process continues, the conductive pattern 485 full array of holes 470, and then the horizontal and vertical growth in the mold layer 465. 充满孔阵列470的导电图案485在如箭头所示的水平和垂直方向上继续生长,由此相邻的导电图案485彼此连接,形成具有所需宽度和高度的导线490。 Full array of holes 485 of the conductive pattern 470 in the horizontal and vertical directions as indicated by arrows continue to grow, whereby adjacent conductive pattern 485 connected to each other to form a wire having a desired width and height of 490.

图10A和图10B是示出图9D中的导电图案485的横截面的电子显微图。 10A and 10B are diagrams illustrating the conductive pattern 9D electron micrograph of a cross-section 485.

参考图9D、图10A和图10B,随着非电镀层工艺的进行,导电图案485从籽层图案483垂直生长以填充孔阵列470。 With reference to FIG. 9D, 10A and 10B, as the non-plating process, the conductive patterns 485 grow vertically from the seed layer patterns 483 to fill the hole arrays 470. 然后,导电图案485在模层465上垂直和水平生长。 Then, the conductive pattern 465 on the mold layer 485 in vertical and horizontal growth. 在本实施例中,导电图案485由非电镀层工艺形成,使得导电图案485具有相对密集的结构。 In the present embodiment, the conductive pattern 485 is formed of a non-plating process, so that the conductive pattern 485 has a relatively dense structure.

参考图9E,继续进行非电镀层工艺以连接从籽层图案483生长的邻近的导电图案485。 With reference to FIG. 9E, the non-plating process to proceed to connect the seed layer patterns 483 grown from the adjacent conductive pattern 485. 在模层465上导电图案485在垂直和水平方向连续生长,结果邻近的导电图案485在模层465上彼此连接。 In the mold layer 465 on the conductive pattern 485 continuously grow in the vertical and horizontal directions, the results of the adjacent conductive pattern 485 on the mold layer 465 connected to each other. 如图9D、10A和10B所示,在导电图案485从籽层图案483以垂直方向生长后,它们在模层465上在垂直和水平方向上生长。 FIG. 9D, 10A and 10B, after the conductive pattern 485 from the seed layer patterns 483 in the vertical direction grow, they grow vertically and horizontally on the mold layer 465. 导线490通过连接导电图案485形成。 Conductor 490 by connecting the conductive pattern 485 is formed. 通常在导电图案485充满孔阵列470后调节导电图案485的生长速率,以形成所需宽度和高度的导线490。 In the conductive pattern 485 is typically filled with an array of apertures 470 after adjusting the growth rate of the conductive patterns 485, to form the desired width and height of the wires 490.

参考图9E,具有约100到1000埃的厚度的保护层495形成在模层465上以覆盖导线490。 With reference to FIG. 9E, the protective layer having a thickness of about 100 to 1000 angstroms is formed on the mold layer 495 to cover the wires 465 490. 可以使用碳化硅或氮化硅形成保护层495。 Silicon carbide or silicon nitride can be used to form a protective layer 495.

除去位于模层465上的部分保护层495以完成覆盖导线490的保护层495。 Remove mold layer located on part of the protective layer 465 495 490 to complete the protective layer covering the wires 495. 结果,在基板上形成了具有螺旋导线490的电感器500。 As a result, formed on a substrate 490 having a helix inductor 500.

在本发明的一个实施例中,在除去模层465后,形成保护层495以覆盖导线490。 In one embodiment of the present invention, after removal of the mold layer 465, protective layer 495 is formed to cover the wires 490. 由于未除去位于导线490之下的防扩散层475,所以防扩散层475的侧壁也被保护层495覆盖。 Not removed due to non-proliferation layer 475 is located under the wire 490, so the sidewall diffusion barrier 475 is also covered with a protective layer 495.

图11是示出根据本发明一个实施例的电感器的平面图,图12是沿从II到II'延伸的线切割的图11中电感器部分的横截面图。 FIG 11 is a plan view illustrating an inductor embodiment of the present invention, FIG. 12 along line II to II 'line extending cut cross-sectional view in FIG inductor portion 11.

参考图11和图12,电感器600包括直接连接到下布线560的螺旋导线590,该下布线560包括用于电信号输入输出的焊盘570。 With reference to FIGS. 11 and 12, an inductor 600 includes a direct connection to the lower wiring 560 of the helix 590, the lower wiring 560 including pads 570 for input and output of electrical signals. 换句话说,在电感器600中,螺旋导线590直接连接到下布线560的端部(焊盘570)而没有另外的电触头将它连接到下布线560。 In other words, in the inductor 600, the helix 590 is directly connected to the lower end portion of the wiring 560 (pad 570) without the additional electrical contact connecting it to the lower wiring 560. 另外的电触头的省略有助于更简单、更低成本的制造工艺,因为它省去了触头形成工艺。 Additional electrical contacts omitted contribute to a more simple and less costly manufacturing process, because it eliminates the need for the contact formation process.

穿过下布线560的一部分而形成开口515,在下布线560中螺旋导线590是从开口515通过,以便防止螺旋导线590连接到下布线560。 560 wiring through the lower part of the formation of the opening 515, the next spiral wire cabling from the opening 590 is 515 by 560, 590 in order to prevent the spiral wire connected to the wiring 560. 螺旋导线590直接连接到下布线560的端部(焊盘570),而因为开口515是穿过部分下布线560形成的,所以螺旋导线590不与下布线560接触。 Helix 590 is directly connected to the lower end portion of the wiring 560 (pad 570), and because the opening 515 is formed through the part of the lower wiring 560, so the helix 590 is not in contact with the lower wires 560.

图13A到图13D是示出图12中电感器的制造方法的横截面图。 13A to 13D are cross-sectional views illustrating a method of manufacturing the inductor 12 of FIG.

参考图13A,绝缘层550形成在包括下导电结构的基板上。 With reference to FIG. 13A, the insulating layer 550 is formed on a substrate including a lower conductive structure. 通常使用氧化物或氮化物形成绝缘层550。 Typically formed using an oxide or nitride insulating layer 550.

使用金属或掺杂的多晶硅在绝缘层550上形成导电层,以在绝缘层550上形成下布线560。 Using a metal or polysilicon doped conductive layer is formed on the insulating layer 550 to the insulating layer 550 is formed on the lower wiring 560. 如图11所示,对导电层构图以形成下布线560,其电连接到下导电结构。 As shown in Figure 11, the conductive layer is patterned to form the lower wiring 560 electrically connected to the lower conductive structure. 同时穿过下布线560的一部分形成具有预定宽度的开口515,在下布线560中螺旋导线590(参见图13C)是从开口515通过。 While passing through a portion of lower wiring 560 is formed an opening 515 having a predetermined width, the lower wiring 560, the helix 590 (see FIG. 13C) from the opening 515 through. 优选开口515具有稍微大于螺旋导线590的宽度的宽度。 Preferred opening 515 has a width slightly greater than the helix 590.

参考图13B,具有约500到30000埃的厚度的模层565形成在下布线560上以填充开口515。 With reference to FIG. 13B, having a thickness of from about 500 to 30,000 Angstroms mold layer 565 is formed on the lower wiring 560 to fill the opening 515. 模层565可以使用氧化物或光刻胶形成。 Mold layer 565 may be used to form an oxide or a photoresist. 部分蚀刻模层565以形成多个通过开口515同时暴露出下布线560的端部(即焊盘)和绝缘层550的一部分的孔。 Partially etching the mold layer 565 to form a plurality of end portions of the hole portion 515 through the opening at the same time exposing the wiring 560 (i.e., pads) and an insulating layer 550. 通过模层565形成的每个孔具有约500到30000埃的深度。 Each hole is formed through the mold layer 565 having a depth of about 500 to 30,000 Angstroms. 如上所述,当使用氧化物形成模层565时,在模层565上另外形成光刻胶膜。 As described above, when the mold layer 565 is formed using oxide, the mold layer 565 on the photoresist film is additionally formed. 使用基本和图4A或4B相同的掩模使光刻胶膜曝光,以形成包括多个孔的光刻胶图案。 Use the same basic and 4A or 4B so that the mask exposing the photoresist film to form a photoresist pattern including a plurality of apertures. 具有大约50到1000埃厚度的ARL通常另外形成在光刻胶膜上。 ARL having a thickness of about 50 to 1000 typically additionally formed on the photoresist film. 然后使用光刻胶图案作为蚀刻掩模来蚀刻模层565,从而形成穿过模层565的孔。 Then using the photoresist pattern as an etch mask to etch mold layer 565, thereby forming holes through the mold layer 565. 当使用光刻胶形成模层565时,可以使用基本和图4A或图4B相同的掩模对模层565直接曝光,而不用形成另外的光刻胶膜,由此形成穿过模层565的孔,其中该孔具有内表面。 When the mold layer 565 is formed using photoresist, can use a base and 4A or 4B, the same mask for exposing the mold layer 565 directly, without additional photoresist film is formed, whereby through the mold layer 565 is formed hole, wherein the bore has an inner surface. 可以在模层565上直接形成另外的ARL以保证光刻工艺的工艺裕度。 Additional ARL may be directly formed on the mold layer 565 to ensure a process margin in a photolithography process.

具有大约50到1000埃厚度的防扩散层575形成在下布线560的暴露出的端部上、绝缘层550的暴露出的端部上、孔的内表面上和模层565上。 The ends of the diffusion preventing layer has a thickness of about 50 to 1000 angstroms 575 formed on the lower wiring 560 exposed, on the end portion of the insulating layer 550 exposed on the inner surface of the hole and on the mold layer 565. 防扩散层575通常具有单层结构或多层结构。 Diffusion prevention layer 575 typically has a single layer structure or a multilayer structure. 单层结构通常包括钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛或其合金。 Single-layer structure typically includes tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium or alloys thereof. 多层结构通常包括由钽、氮化钽、氮化铝钽、氮化硅钽、硅化钽、钛、氮化钛、氮化钨、氮化硅钛以及其合金构成的组中的至少两种成分。 Multilayer structure typically includes at least two the group consisting of tantalum, tantalum nitride, aluminum nitride, tantalum, tantalum silicon nitride, tantalum silicide, titanium, titanium nitride, tungsten nitride, silicon nitride, titanium, and alloys thereof consisting of ingredients.

通过CVD工艺或PVD工艺,在防扩散层575上形成具有大约100到5000埃厚度的籽层。 By a CVD process or PVD process, the diffusion preventing layer 575 on the seed layer has a thickness of about 100 to 5000 angstroms is formed. 籽层优选使用铜、铂、钯、镍、银、金或其合金形成。 Seed layer is preferably formed using copper, platinum, palladium, nickel, silver, gold or an alloy thereof.

为了实现选择性电解镀层工艺或非电镀层工艺,在孔的内表面和下布线560的端部上通过除去位于模层565上的部分籽层而形成籽层图案580。 In order to achieve the selective electroless plating process or electroless plating layer process, on the inner surface of the hole and the lower end portion of the wiring 560 is located partially removing the seed layer and the mold layer 565 is formed on the seed layer 580 by patterning. 可以通过使用CMP工艺、内蚀刻工艺或CMP工艺和内蚀刻工艺的组合形成籽层图案580。 By using a CMP process, etching process or a combination of the CMP process and the etching process of forming the seed layer patterns 580. 在此不蚀刻位于模层565上的防扩散层575。 This is not etched in nonproliferation layer 575 is located on the mold layer 565. 所以,籽层图案580和防扩散层575位于孔的内表面上,而只有防扩散层575位于模层565上。 So, on the inner surface of the hole 575 located seed layer pattern layer 580 and non-proliferation, and only non-proliferation layer 575 is located on the mold layer 565.

通过选择性电解或非电镀层工艺,从籽层图案580形成导电图案585以填充孔。 Electrolytic or electroless plating layer by selective process, the seed layer pattern 580 is formed from the conductive pattern 585 to fill the hole. 优选采用大约20到40mA/cm2的电流密度,并使用包括硫酸铜溶液、硫酸溶液以及包括氯离子的溶液的镀层溶液进行电解镀层工艺。 Preferably used from about 20 to 40mA / cm2 current density, and an electroless plating process using a solution comprising copper sulfate, sulfuric acid solution and the coating solution comprises a solution of chloride ions were. 优选使用包含如甲醛或联氨的还原剂的硫酸铜溶液进行选择性非电镀层工艺。 Preferably as a copper sulfate solution containing formaldehyde or hydrazine reducing agent selective electroless plating layer process.

因为可以限制导电图案585在孔中的水平生长,导电图案585在孔中从籽层图案580垂直生长。 Since the conductive pattern 585 can limit the level of growth in the wells, the conductive pattern 585 in the vertical bore 580 grown from the seed layer patterns. 当继续进行选择性电解镀层工艺或非电镀层工艺直到导电图案585充满孔时,然后继续进行以使导电图案585在模层565上水平和垂直生长。 When proceed selective electroless plating process or plating process until the hole is filled when the conductive pattern 585, and then proceed to the conductive pattern on the mold layer 585 horizontal and 565 vertical growth. 导电图案585在如箭头所示的水平和垂直方向继续生长,由此相邻的导电图案585彼此连接。 Conductive patterns 585 in horizontal and vertical directions as shown by the arrows continue to grow, whereby adjacent conductive pattern 585 connected to each other.

导电图案585电连接到下布线560的端部,而由于开口515导电图案585与下布线560的另一部分分开。 Conductive patterns 585 electrically connected to the lower end portion of the wiring 560, and the conductive pattern 585 since the opening 515 and the lower portion 560 of the other separate wiring. 即除了下布线560的端部,导电图案585与下布线560电绝缘。 I.e., in addition to the lower end portion of the wiring 560, the conductive pattern 585 electrically insulated from the lower wiring 560. 结果,通过省去了另外的涉及将导电图案图585电连接到下布线560的触头形成工艺而可以使电感器600(参见图13C)的制造方法简化并以低成本进行。 As a result, by eliminating the need for additional relates to a conductive pattern 585 connected to the lower view of the electrical contacts of the wiring 560 and can make the process of forming an inductor 600 (see FIG. 13C) manufacturing method to simplify and at a low cost.

参考图13C,随着选择性电解或非电镀层工艺的进行,在导电图案585从籽层图案580垂直生长充满孔之后,导电图案585在模层565上垂直和水平生长。 With reference to Figure 13C, as the selective electrolytic or electroless plating layer process, after the conductive pattern 585 from the seed layer patterns 580 are vertically grown full of holes, a conductive pattern 585 on the mold layer 565 in vertical and horizontal growth. 结果,通过连接导电图案585从籽层图案580在模层565上形成具有所需宽度和高度的导线590。 As a result, by connecting the conductive pattern 585 from the seed layer patterns 580 formed wire 590 having a desired width and height on the mold layer 565. 当导电图案585由非电镀层工艺形成时,导电图案585可以具有相对密集的结构。 When the conductive pattern 585 is formed of a non-plating process, the conductive pattern 585 may have a relatively dense structure. 具体而言,导电图案585在垂直和水平方向在模层565上连续生长,使得相邻的导电图案585在模层565上彼此连接。 Specifically, the conductive pattern 585 in the vertical and horizontal direction of the continuous layer 565 is grown on the die, so that adjacent conductive patterns 585 on the mold layer 565 connected to each other. 在导电图案585从籽层图案580垂直生长后,它们在模层565垂直和水平生长。 After the conductive pattern 585 vertical growth from the seed layer pattern 580, they grow mold layer 565 in the vertical and horizontal. 通过导电图案585的水平和垂直生长形成导线590。 Growth conductive pattern formed by the wire 590 horizontal and 585 vertical. 优选在导电图案585孔后对导电图案585的生长速率进行调节以使导线590在模层565上形成具有所需的宽度和高度。 Preferably after the conductive patterns 585 holes on the growth rate of the conductive pattern 585 is adjusted so that the wire 590 is formed having the desired width and height on the mold layer 565.

现在参考图13D,在去除位于模层565上的部分防扩散层575后,在模层565上形成具有约100到1000埃的厚度的保护层595,以覆盖导线590。 Referring now to Figure 13D, after removing the portion located on the diffusion preventing layer 575 on the mold layer 565, the mold layer 565 is formed on the protective layer 595 having a thickness of about 100 to 1000 Angstroms, so as to cover the wires 590. 使用碳化硅、氮化硅形成保护层595。 Silicon carbide, silicon nitride forming the protective layer 595. 所以,在基板上形成具有多个螺旋导线590的电感器600。 Therefore, the wire 590 is formed on a substrate 600 having a plurality of spiral inductors. 在本发明的一个实施例中,在去除模层565后,形成保护层595以完全覆盖导线590。 In one embodiment of the present invention, after removal of the mold layer 565, protective layer 595 is formed to completely cover the wires 590.

总之,根据本发明,包括螺旋导线的电感器可以通过使用电解工艺或非电镀层工艺以相对低的成本而易于制造。 In summary, according to the present invention, including the helix inductor by using an electrolytic plating process or a non-layer process at a relatively low cost and easy to manufacture.

电感器优选包括具有所需宽度和高度的导线,这通过使用电解镀层工艺或非电镀层工艺来调节导电图案的生长速率获得。 Preferably comprises an inductor having a desired width and height of the conductors, which is adjusted to obtain the growth rate of the conductive pattern by electroless plating using the plating process or processes.

因为导线的所需高度通常大于常规电感器,电感器可具有以基板上大的高度为特征的螺旋结构。 Because the desired height of the conductor is typically larger than a conventional inductor, the inductor may have to a large height on a substrate characterized by a helical structure.

因为省去了将电感器电连接到形成在基板上的下布线所通常要求的另外的工艺,因此形成电感器所需的制造时间和成本可以被大大降低。 Because omitted electrically connected to the inductor formed on the substrate additional process of the lower wiring normally required, thereby forming a manufacturing time and cost required for the inductor can be greatly reduced. 可直接在常规的基板上形成电感器而无需任何另外的工艺,由此具有大高度的电感器可以使用制造电感器的常规装置以低成本而易于形成。 May be formed directly on a conventional substrate inductor without any additional process, whereby the height of the conventional apparatus large inductors can be used to manufacture an inductor having a low cost and easily formed.

在附图和相应的文字描述中所公开的优选实施例是讲授的例子。 In the drawings and the corresponding text description of the disclosed preferred embodiments are teaching examples. 本领域的技术人员可以理解,在不脱离本发明的范围的情况下可以对典型实施例在形式和细节上进行各种变化。 Those skilled in the art will appreciate, may be of exemplary embodiments and various changes in form and detail without departing from the scope of the present invention is the case. 本发明的范围由所附的权利要求书限定。 By the scope of the invention defined in the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN105316714A *23 Sep 201310 Feb 2016Tdk株式会社各向异性镀敷方法以及薄膜线圈
Classifications
International ClassificationH01L21/02, H01L27/08, H01F17/00, H01F41/04, H01L23/522, H01L27/04
Cooperative ClassificationH01L27/08, H01L2924/0002, H01L23/5227, H01F41/041, H01L28/10, H01F2017/0046
European ClassificationH01L28/10, H01L23/522L, H01L27/08
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