CN1622341A - 薄膜晶体管 - Google Patents

薄膜晶体管 Download PDF

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CN1622341A
CN1622341A CNA2004101038568A CN200410103856A CN1622341A CN 1622341 A CN1622341 A CN 1622341A CN A2004101038568 A CNA2004101038568 A CN A2004101038568A CN 200410103856 A CN200410103856 A CN 200410103856A CN 1622341 A CN1622341 A CN 1622341A
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film transistor
thin
insulation layer
base map
gate insulation
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黄义勋
李相杰
金得钟
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Samsung SDI Co Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Abstract

本发明的薄膜晶体管可包括栅绝缘层和底图形，底图形位于栅绝缘层下方并与栅绝缘层接触、具有至多约80°的锥角的边缘。采用这种设计，能够提高栅绝缘层的介电强度。底图形可以是栅电极层。

Description

薄膜晶体管
相关申请的相互参考
本申请要求2003年11月28日申请的韩国专利申请No.2003-85848的优先权，这里引入其全部公开内容供参考。
发明背景
1.发明领域
本申请涉及一种薄膜晶体管，更详细地说涉及一种具有改进的栅绝缘层介电强度的薄膜晶体管。
2.相关技术的描述
通常，薄膜晶体管包括半导体层、栅电极、源/漏电极和插入半导体层和栅电极之间的栅绝缘层。对于使用薄膜晶体管的电路，为了进行高速操作，必须减小薄膜晶体管的阈值电压。薄膜晶体管的阈值电压与栅绝缘层的厚度具有密切的关系，因此，应当减薄栅绝缘层以减小阈值电压。
然而，当栅绝缘层变薄时，栅绝缘层的介电强度会退化。栅绝缘层的介电强度指的是栅绝缘层不被击穿而能够承受的最大电场。当栅绝缘层的介电强度低于设计值时，会发生击穿。这会导致薄膜晶体管性能的操作缺陷和使用薄膜晶体管的显示器出现相应的显示缺陷。
为了改进栅绝缘层的介电强度特性，韩国专利申请No.1994-035626公开了一种通过低温CVD淀积氧化层并接着进行热氧化的方法。然而，这种情形中的热氧化需要高温，因此，不利的是需要昂贵的石英衬底。
发明内容
本申请提供一种具有改进的栅绝缘层介电强度的薄膜晶体管。
薄膜晶体管可以包括栅绝缘层，和位于栅绝缘层下部并与其接触、边缘具有80°或更小锥角的底图形。
优选的是，底图形边缘的锥角具有至少30°的角度。更优选的是，底图形边缘的锥角具有60°～75°的角度。
优选的栅绝缘层由氧化硅层制得。而且，优选的栅绝缘层通过等离子体增强化学气相淀积(PECVD)制得。
底图形是半导体层。底图形可以是栅电极。这里，优选栅电极具有约500～约3000的厚度。
附图的简单说明
图1示出典型的顶栅薄膜晶体管的平面图。
图2A和2B分别说明本发明一个实施例的顶栅薄膜晶体管制作时沿图1的线I-I′和II-II′的截面图。
图3是说明本发明另一实施例的底栅薄膜晶体管和其制造方法的截面图。
图4A、5A、6A和7A是分别示出实施例1、2、比较例1和2的薄膜晶体管的半导体层的边缘图。
图4B、5B、6B和7B是分别示出实施例1、2、比较例1和2的薄膜晶体管中栅绝缘层的介电强度特性图。
发明详述
现在参照附图更充分地说明本发明，图中示出了本发明的优选实施例。然而，本发明可以以不同的方式实施，并且不应当解释为受这些实施例限制。在图中，为清楚起见，放大了各层和区域的厚度。整个说明书中相同的数字表示相同的元件。
如图1所示，半导体层120可以沿一个方向放置，与半导体层120交叉的栅电极140放置在半导体层120上。栅绝缘层(未示出)放置在半导体层120和栅电极140之间。源/漏电极160位于半导体层120的两端上。
如图2A和2B所示，提供衬底100，并优选在衬底100上形成缓冲层(未示出)。缓冲层可以保护薄膜晶体管的有源部分，使其避免在后续工艺中从衬底100中发射出的杂质的影响。缓冲层可以由例如氧化硅层、氮化硅层、氮氧化硅层或其叠层形成。优选的是，在缓冲层上形成非晶层之后，通过准分子激光退火(ELA)、连续横向凝固(SLS)、金属诱导结晶(MIC)、金属诱导横向结晶(MILC)等使非晶层结晶。这种方法可以形成多晶硅层。优选的是多晶硅厚约300～约1000之间。
接下来，在多晶硅层上形成光致抗蚀图形，并蚀刻多晶硅层(用光致抗蚀图形作掩模)形成半导体层120。可以使形成的半导体层120具有一锥角边缘，其中，该边缘的锥角具有80°或更小的角度。优选的是，通过干法蚀刻进行多晶硅层的蚀刻，其具有优良的蚀刻均匀性和低刻蚀CD损失。另外，优选使用O2和SF6的混合气体作为蚀刻气体，形成具有锥角边缘的半导体层120。当SF6蚀刻硅时，O2可用于蚀刻光致抗蚀图形的侧面。这可以相应地使半导体层120形成为具有锥形边缘。通过O2和SF6的流速/体积比，能够调节半导体层120的边缘的锥角。
接下来，在半导体层120上形成覆盖半导体层120的栅绝缘层130。栅绝缘层130由例如氧化硅层或氮化硅层形成。然而，由于氧化硅良好的介电强度，优选栅绝缘层130由氧化硅层形成。虽然其它技术也可使用，但优选栅绝缘层130通过低温PECVD形成。
半导体层120被形成为具有80°或更小的锥角边缘。这种锥角的选择有助于防止淀积的栅绝缘层130在半导体层120的侧面变薄的现象。当栅绝缘层130在半导体层120的侧面变薄时，栅绝缘层130在薄处能呈现出介电击穿。因此，半导体层120被形成为具有80°或更小的锥角边缘，栅绝缘层130能够均匀地在半导体层120的上面和侧面形成。因此，可提高栅绝缘层130的介电强度。
半导体层120的边缘的锥角优选约为30°或更大。当锥角小于约30°时，低于30°的薄边缘导致半导体120的电阻增大。这使产生于半导体层120中的沟道电阻增大。更优选地是，为了平衡电阻特性和介电强度特性，半导体120的边缘的锥角可以在约60°～约75°之间。
另外，可以在栅绝缘层130上淀积栅电极材料，并构图，形成栅电极140。然后，使用栅电极140作为掩模，注入杂质到半导体层120。因此，在半导体层120中形成源/漏区120a。位于源/漏区120a之间的区域可限定为沟道区120b。
另外，可以形成覆盖具有栅电极140的衬底整个表面的中间层150，在中间层150中形成各自暴露源/漏区120a之一的源/漏接触孔150a。在形成源/漏接触孔150a处的衬底之上，可以淀积源/漏电极材料。通过这种方式构图，可以形成分别通过源/漏接触孔150a与源/漏区120a接触的源/漏电极160。
图3示出了根据本发明另一实施例的底栅薄膜晶体管和其制造方法的截面图。
提供如图3所示的衬底300。在衬底300上可淀积栅电极材料并在淀积的栅电极材料上形成光致抗蚀图形(未示出)。用光致抗蚀图形作掩模，可以蚀刻栅电极材料，形成栅电极320。栅电极320可形成具有约80°或更小角度的锥角边缘。优选的是通过具有优良的蚀刻均匀性和低蚀刻CD损失的干法蚀刻，蚀刻栅电极材料。而且，优选的是使用O2和SF6的混合气体作为刻蚀气体，形成具有锥角边缘的栅电极320。如上所述，O2可用于蚀刻光致抗蚀图形的侧面。这可使该层具有锥角边缘。通过控制O2和SF6的流速/体积比，调整栅电极320中边缘的锥角。
对于平板显示器来说，当在形成栅电极320同时形成的栅极布线的电阻特性和蚀刻CD损失平衡时，栅电极320厚度介于约500～约3000之间是优选的。
另外，在栅电极320上淀积栅绝缘层330。栅绝缘层330由例如氧化硅层或氮化硅层形成。优选的是，栅绝缘层330利用氧化硅层形成。另外，通过低温PECVD法或其它类似的方法，形成栅绝缘层330是优选的。
形成的栅电极320具有约80°或更小的锥角边缘。这可以减弱栅绝缘层330在栅电极320的边缘变得太薄的问题。当栅绝缘层330在栅电极320的边缘变薄时，在栅绝缘层330的薄处出现介电击穿。因此，栅电极320可具有80°或更小的锥角边缘，以使能够在栅电极320的上面和侧面均匀形成栅绝缘层330。因此，能够提高栅绝缘层330的介电强度。
出于与前边的实施例同样的原因，栅电极320中边缘的锥角具有30°或更大是优选的。
另外，可在栅绝缘层330上依次形成半导体层和欧姆接触层。这里，优选的是，半导体层由非晶硅形成，欧姆接触层可以是非晶硅中掺入杂质的区域。然而，在由非晶硅形成半导体层之后，通过ELA、SLS、MIC、MILC等使其结晶，形成多晶硅层。对欧姆接触层和半导体层依次构图，形成半导体图形340和欧姆接触层图形350。在本实施例中，形成的半导体图形340覆盖栅电极320。
另外，在欧姆接触层图形350上淀积源/漏电极材料，并构图，形成源/漏电极360。在本实施例中，半导体层图形340暴露在源/漏电极360之间。
为了进一步帮助读者理解本发明，下面说明几个实施例。
实施例1
在绝缘衬底上形成非晶硅层，构图，形成厚500的多晶硅层。在多晶硅层上形成光致抗蚀图形。用光致抗蚀图形作掩模，蚀刻多晶硅层，形成半导体层。使用比例为120/180sccm的SF6/O2气体，蚀刻多晶硅，形成半导体层。另外，在半导体层上PECVD淀积1000厚的氧化硅层，形成栅绝缘层。在栅绝缘层上形成栅电极，从而制得本实施例的薄膜晶体管。
实施例2
在本实施例中，除了使用比例为100/200sccm的SF6/O2气体，蚀刻多晶硅层外，用与实施例1中相同的方法，制造薄膜晶体管。
比较例1
除了使用比例为150/150sccm的SF6/O2气体，蚀刻多晶硅层外，用与实施例1中相同的方法，制造薄膜晶体管。
比较例2
除了使用比例为150/50sccm的SF6/O2气体，刻蚀多晶硅层外，用与实施例1中相同的方法，制造薄膜晶体管。
如图4所示，对于实施例1的薄膜晶体管，半导体层中边缘的锥角R具有约78°的角度。如图5A所示，对于实施例2的薄膜晶体管，半导体层中边缘的锥角S具有约60°的角度。如图6A所示，对于比较例1的薄膜晶体管，半导体层中边缘的锥角T具有约82°的角度。如图7A所示，对于比较例2的薄膜晶体管，半导体层中边缘的锥角U具有约90°的角度。
图4B、5B、6B和7B是分别示出实施例1、实施例2、比较例1和比较例2的薄膜晶体管中栅绝缘层的介电强度图。在图中，X轴表示栅电极和半导体层之间的电场(MV/cm)，Y轴表示在栅电极处测得的漏电流(A)。
如图4B和5B所示，对于实施例1和2的薄膜晶体管，直至栅电极和半导体层之间的电场达到约5MV/cm时，漏电流大致保持为定值(约1×10-12A)。因此，提高了实施例1和实施例2的薄膜晶体管中的栅绝缘层的介电强度。
如图6B和7B所示，对于比较例1和2的薄膜晶体管，当栅电极和半导体层之间的电场超过2MV/cm时，栅极漏电流呈现迅速增长。这表示栅绝缘层被介电击穿。这种击穿会导致薄膜晶体管故障。也会导致使用薄膜晶体管的显示器出现缺陷。这种情况下的缺陷包括点缺陷、线缺陷或亮度不均匀。
如上所述，根据本发明，栅绝缘层的底图形可以具有80°或更小的锥角的边缘，从而提高栅绝缘层的介电强度。因此，能够阻止薄膜晶体管的故障和呈现的缺陷(当薄膜晶体管用于显示器时)。

Claims (20)

1.一种薄膜晶体管，其中包括：
栅绝缘层；和
位于下部并与栅绝缘层接触、具有不大于约80°的锥角的边缘的底图形。
2.权利要求1中所述的薄膜晶体管，其中，底图形的边缘的锥角具有至少约30°的角。
3.权利要求1中所述的薄膜晶体管，其中，底图形的边缘的锥角具有约60°～约75°的角。
4.权利要求1中所述的薄膜晶体管，其中，栅绝缘层包括氧化硅层。
5.权利要求1中所述的薄膜晶体管，其中，栅绝缘层通过等离子体增强化学气相淀积形成。
6.权利要求1中所述的薄膜晶体管，其中，底图形包括半导体层。
7.权利要求1中所述的薄膜晶体管，其中，底图形包括栅电极。
8.权利要求7中所述的薄膜晶体管，其中，栅电极厚约500～约3000。
9.一种薄膜晶体管的制造方法，其中包括：
在衬底上淀积底图形；和
在底图形上直接淀积栅绝缘层；
其中，底图形有不大于约80°的锥角的边缘。
10.权利要求9中所述的方法，其中，底图形的边缘的锥角具有至少约30°的角。
11.权利要求9中所述的方法，其中，底图形的边缘的锥角具有约60°～约75°的角。
12.权利要求9中所述的方法，其中，栅绝缘层包括氧化硅层。
13.权利要求9中所述的方法，还包括通过等离子体增强化学气相淀积形成栅绝缘层。
14.权利要求9中所述的方法，其中，底图形包括半导体层。
15.权利要求9中所述的方法，其中，底图形包括栅电极。
16.权利要求15中所述的方法，其中，栅电极厚约500～约3000。
17.一种显示器，其中包括：
多个像素电极的阵列，
该多个像素电极包括薄膜晶体管，和
该薄膜晶体管包括栅绝缘层；和
位于栅绝缘层下部并与其接触、具有不大于约80°的锥角的边缘的底图形。
18.权利要求17中所述的显示器，其中，底图形的边缘的锥角具有至少约30°的角。
19.权利要求17中所述的显示器，其中，底图形的边缘的锥角具有约60°～约75°的角。
20.权利要求17中所述的显示器，其中，底图形包括栅电极。
CNA2004101038568A 2003-11-28 2004-11-26 薄膜晶体管 Pending CN1622341A (zh)

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