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Publication numberCN1622341 A
Publication typeApplication
Application numberCN 200410103856
Publication date1 Jun 2005
Filing date26 Nov 2004
Priority date28 Nov 2003
Also published asEP1536482A1, US20050116305
Publication number200410103856.8, CN 1622341 A, CN 1622341A, CN 200410103856, CN-A-1622341, CN1622341 A, CN1622341A, CN200410103856, CN200410103856.8
Inventors黄义勋, 李相杰, 金得钟
Applicant三星Sdi株式会社
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
薄膜晶体管 Thin film transistor translated from Chinese
CN 1622341 A
Abstract  translated from Chinese
本发明的薄膜晶体管可包括栅绝缘层和底图形,底图形位于栅绝缘层下方并与栅绝缘层接触、具有至多约80的锥角的边缘。 A thin film transistor of the present invention may include a gate insulating layer and a bottom graphics, graphics bottom located under the gate insulating layer and in contact with the gate insulating layer, having an edge of up to about 80 cone angle. 采用这种设计,能够提高栅绝缘层的介电强度。 With this design, the gate insulating layer can be improved dielectric strength. 底图形可以是栅电极层。 End pattern may be a gate electrode layer.
Claims(20)  translated from Chinese
1.一种薄膜晶体管,其中包括:栅绝缘层;和位于下部并与栅绝缘层接触、具有不大于约80的锥角的边缘的底图形。 1. A thin film transistor, including: a gate insulating layer; and in the lower part and in contact with the gate insulating layer, having no more than about 80 cone angle of the bottom edge of the graphics.
2.权利要求1中所述的薄膜晶体管,其中,底图形的边缘的锥角具有至少约30的角。 Thin film transistor according to claim 1, wherein the taper angle of the edge of the bottom pattern having at least about 30 of angle.
3.权利要求1中所述的薄膜晶体管,其中,底图形的边缘的锥角具有约60~约75的角。 Thin film transistor according to claim 1, wherein the taper angle of the edge of the bottom having a pattern angle of about 60 ~ 75 of about.
4.权利要求1中所述的薄膜晶体管,其中,栅绝缘层包括氧化硅层。 4. The thin film transistor according to claim 1, wherein the gate insulating layer comprises a silicon oxide layer.
5.权利要求1中所述的薄膜晶体管,其中,栅绝缘层通过等离子体增强化学气相淀积形成。 5. The thin film transistor according to claim 1, wherein the gate insulating layer is formed by plasma enhanced chemical vapor deposition is formed.
6.权利要求1中所述的薄膜晶体管,其中,底图形包括半导体层。 Thin film transistor according to claim 1, wherein the end pattern comprises a semiconductor layer.
7.权利要求1中所述的薄膜晶体管,其中,底图形包括栅电极。 Thin film transistor according to claim 1, wherein the pattern comprises a bottom gate electrode.
8.权利要求7中所述的薄膜晶体管,其中,栅电极厚约500~约3000。 8. The thin film transistor according to claim 7, wherein the gate electrode thickness 500 ~ about 3000.
9.一种薄膜晶体管的制造方法,其中包括:在衬底上淀积底图形;和在底图形上直接淀积栅绝缘层;其中,底图形有不大于约80的锥角的边缘。 9. A method of manufacturing a thin film transistor, including: depositing a bottom pattern on a substrate; a gate insulating layer and deposited directly on the bottom graph; wherein, the bottom edge of the graphics have not more than about 80 cone angle.
10.权利要求9中所述的方法,其中,底图形的边缘的锥角具有至少约30的角。 10. The method described in claim 9, wherein the taper angle of the edge of the bottom pattern having at least about 30 of angle.
11.权利要求9中所述的方法,其中,底图形的边缘的锥角具有约60~约75的角。 11. The method described in claim 9, wherein the taper angle of the edge of the bottom having a pattern angle of about 60 ~ 75 of about.
12.权利要求9中所述的方法,其中,栅绝缘层包括氧化硅层。 12. The method described in claim 9, wherein the gate insulating layer comprises a silicon oxide layer.
13.权利要求9中所述的方法,还包括通过等离子体增强化学气相淀积形成栅绝缘层。 13. The method according to claim 9, further comprising a plasma enhanced chemical vapor deposition by a gate insulating layer is formed.
14.权利要求9中所述的方法,其中,底图形包括半导体层。 14. The method according to claim 9, wherein the end pattern comprises a semiconductor layer.
15.权利要求9中所述的方法,其中,底图形包括栅电极。 15. The method according to claim 9, wherein the pattern comprises a bottom gate electrode.
16.权利要求15中所述的方法,其中,栅电极厚约500~约3000。 16. The method according to claim 15, wherein the gate electrode thickness 500 ~ about 3000.
17.一种显示器,其中包括:多个像素电极的阵列,该多个像素电极包括薄膜晶体管,和该薄膜晶体管包括栅绝缘层;和位于栅绝缘层下部并与其接触、具有不大于约80的锥角的边缘的底图形。 17. A display, comprising: an array of a plurality of pixel electrodes, the plurality of pixel electrodes comprises a thin film transistor, and the thin film transistor includes a gate insulating layer; and a lower portion located on the gate insulating layer and in contact therewith, having no more than about 80 the bottom edges of the graphic of cone angle.
18.权利要求17中所述的显示器,其中,底图形的边缘的锥角具有至少约30的角。 18. A display according to claim 17, wherein the taper angle of the edge of the bottom pattern having at least about 30 of angle.
19.权利要求17中所述的显示器,其中,底图形的边缘的锥角具有约60~约75的角。 19. A display according to claim 17, wherein the taper angle of the edge of the bottom having a pattern angle of about 60 ~ 75 of about.
20.权利要求17中所述的显示器,其中,底图形包括栅电极。 20. A display according to claim 17, wherein the pattern comprises a bottom gate electrode.
Description  translated from Chinese
薄膜晶体管 Thin film transistor

相关申请的相互参考本申请要求2003年11月28日申请的韩国专利申请No.2003-85848的优先权,这里引入其全部公开内容供参考。 CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the November 28, 2003 to apply for the Korean Patent Application No.2003-85848 priority, the entire disclosure of which is incorporated herein by reference.

发明背景1.发明领域本申请涉及一种薄膜晶体管,更详细地说涉及一种具有改进的栅绝缘层介电强度的薄膜晶体管。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present application relates to a thin film transistor, more particularly relates to an improved thin film transistor gate insulating layer having a dielectric strength.

2.相关技术的描述通常,薄膜晶体管包括半导体层、栅电极、源/漏电极和插入半导体层和栅电极之间的栅绝缘层。 2. Description of Related Art Generally, a thin film transistor including a semiconductor layer, a gate electrode, a source / drain electrode and the gate insulating layer interposed between the semiconductor layer and the gate electrode. 对于使用薄膜晶体管的电路,为了进行高速操作,必须减小薄膜晶体管的阈值电压。 For a thin film transistor circuit, in order to perform high-speed operation, is necessary to reduce the threshold voltage of the thin film transistor. 薄膜晶体管的阈值电压与栅绝缘层的厚度具有密切的关系,因此,应当减薄栅绝缘层以减小阈值电压。 The threshold voltage of the thin film transistor and thickness of the gate insulating layer has a close relationship, therefore, the gate insulating layer should be thinned to reduce the threshold voltage.

然而,当栅绝缘层变薄时,栅绝缘层的介电强度会退化。 However, when a thin gate insulating layer, a gate insulating layer of dielectric strength will be degraded. 栅绝缘层的介电强度指的是栅绝缘层不被击穿而能够承受的最大电场。 Dielectric strength of the gate insulating layer refers to a gate insulating layer does not breakdown and can withstand a maximum electric field. 当栅绝缘层的介电强度低于设计值时,会发生击穿。 When the dielectric strength of the gate insulating layer is less than the design value, breakdown will occur. 这会导致薄膜晶体管性能的操作缺陷和使用薄膜晶体管的显示器出现相应的显示缺陷。 This can lead to defects in the thin film transistor operating performance and the use of thin-film transistor display a corresponding display defects.

为了改进栅绝缘层的介电强度特性,韩国专利申请No.1994-035626公开了一种通过低温CVD淀积氧化层并接着进行热氧化的方法。 In order to improve the gate insulating layer of dielectric strength characteristics, Korean Patent Application No.1994-035626 discloses a low-temperature oxide layer is deposited by CVD and then performing thermal oxidation method. 然而,这种情形中的热氧化需要高温,因此,不利的是需要昂贵的石英衬底。 However, this case requires a high temperature thermal oxidation, and therefore, disadvantageously the need for expensive quartz substrate.

发明内容 SUMMARY

本申请提供一种具有改进的栅绝缘层介电强度的薄膜晶体管。 The present application provides an improved thin film transistor gate insulating layer having a dielectric strength.

薄膜晶体管可以包括栅绝缘层,和位于栅绝缘层下部并与其接触、边缘具有80或更小锥角的底图形。 The thin film transistor may include a gate insulating layer, and is located in the lower portion of the gate insulating layer and in contact with the edge of 80 or less with a taper angle of the bottom graphic.

优选的是,底图形边缘的锥角具有至少30的角度。 Preferably, the taper angle of the bottom edges of the graphic having an angle of at least 30 . 更优选的是,底图形边缘的锥角具有60~75的角度。 More preferably, the taper angle of the bottom edges of the graphic with an angle of 60 ~ 75 .

优选的栅绝缘层由氧化硅层制得。 Preferably the gate insulating layer made from silicon oxide layer system. 而且,优选的栅绝缘层通过等离子体增强化学气相淀积(PECVD)制得。 Moreover, a gate insulating layer is preferably by plasma-enhanced chemical vapor deposition (PECVD) system.

底图形是半导体层。 Bottom graphic is a semiconductor layer. 底图形可以是栅电极。 End pattern may be a gate electrode. 这里,优选栅电极具有约500~约3000的厚度。 Here, the gate electrode preferably has a thickness of from about 500 ~ about 3000.

附图的简单说明图1示出典型的顶栅薄膜晶体管的平面图。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a typical plan view of a top gate thin film transistor.

图2A和2B分别说明本发明一个实施例的顶栅薄膜晶体管制作时沿图1的线II′和II-II′的截面图。 2A and 2B illustrate along the line 1 of II 'and II-II' cross-sectional view when a top gate thin film transistor produced an embodiment of the present invention.

图3是说明本发明另一实施例的底栅薄膜晶体管和其制造方法的截面图。 Figure 3 is a sectional view illustrating a bottom gate thin film transistor of another embodiment of the invention and its manufacturing method.

图4A、5A、6A和7A是分别示出实施例1、2、比较例1和2的薄膜晶体管的半导体层的边缘图。 FIG. 4A, 5A, 6A and 7A are graphs showing 1, Comparative Example 1 and the edge of the semiconductor layer of the thin film transistor of Example 2.

图4B、5B、6B和7B是分别示出实施例1、2、比较例1和2的薄膜晶体管中栅绝缘层的介电强度特性图。 FIG. 4B, 5B, 6B and 7B are graphs showing 1, Comparative Examples 1 and 2 of the thin film transistor gate insulating layer Dielectric strength characteristic diagram of the embodiment.

发明详述现在参照附图更充分地说明本发明,图中示出了本发明的优选实施例。 DETAILED DESCRIPTION The accompanying drawings illustrate the invention more fully, the figure shows a preferred embodiment of the present invention Referring now. 然而,本发明可以以不同的方式实施,并且不应当解释为受这些实施例限制。 However, the present invention can be implemented in different ways, and should not be construed as being limited by the examples. 在图中,为清楚起见,放大了各层和区域的厚度。 In the drawing, for clarity, the thickness of each layer and an enlarged region. 整个说明书中相同的数字表示相同的元件。 Throughout the specification like numerals denote like elements.

如图1所示,半导体层120可以沿一个方向放置,与半导体层120交叉的栅电极140放置在半导体层120上。 As shown in Figure 1, the semiconductor layer 120 may be disposed along one direction, and the semiconductor layer 120 intersecting the gate electrode 140 disposed on the semiconductor layer 120. 栅绝缘层(未示出)放置在半导体层120和栅电极140之间。 A gate insulating layer (not shown) disposed between the semiconductor layer 120 and the gate electrode 140. 源/漏电极160位于半导体层120的两端上。 Source / drain electrode 160 are located on both ends of the semiconductor layer 120.

如图2A和2B所示,提供衬底100,并优选在衬底100上形成缓冲层(未示出)。 And shown in FIG. 2A 2B, providing a substrate 100, and preferably a buffer layer (not shown) formed on the substrate 100. 缓冲层可以保护薄膜晶体管的有源部分,使其避免在后续工艺中从衬底100中发射出的杂质的影响。 The buffer layer may protect the active portion of the thin film transistor to avoid the influence of the subsequent process emitted from the impurities in the substrate 100. 缓冲层可以由例如氧化硅层、氮化硅层、氮氧化硅层或其叠层形成。 The buffer layer may be formed such as a silicon oxide layer, silicon nitride layer, silicon oxynitride layer or a laminate is formed. 优选的是,在缓冲层上形成非晶层之后,通过准分子激光退火(ELA)、连续横向凝固(SLS)、金属诱导结晶(MIC)、金属诱导横向结晶(MILC)等使非晶层结晶。 Preferably, after forming the amorphous layer on the buffer layer by excimer laser annealing (ELA), continuous lateral solidification (SLS), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), etc. so that the amorphous layer is crystallized . 这种方法可以形成多晶硅层。 This method can be forming a polysilicon layer. 优选的是多晶硅厚约300~约1000之间。 Preferably between polysilicon thickness 300 ~ about 1000.

接下来,在多晶硅层上形成光致抗蚀图形,并蚀刻多晶硅层(用光致抗蚀图形作掩模)形成半导体层120。 Next, on the polysilicon layer photoresist pattern, and etching the polysilicon layer (the photoresist pattern as a mask) forming a semiconductor layer 120. 可以使形成的半导体层120具有一锥角边缘,其中,该边缘的锥角具有80或更小的角度。 Of the semiconductor layer 120 is formed having a cone angle edge, wherein the edge having a taper angle 80 or less angle. 优选的是,通过干法蚀刻进行多晶硅层的蚀刻,其具有优良的蚀刻均匀性和低刻蚀CD损失。 Preferably, the polysilicon layer is etched by dry etching, which has excellent etch etch CD uniformity and low loss. 另外,优选使用O2和SF6的混合气体作为蚀刻气体,形成具有锥角边缘的半导体层120。 Further, it is preferable to use a mixed gas of SF6 and O2 as an etching gas, a semiconductor layer 120 having a taper angle edge. 当SF6蚀刻硅时,O2可用于蚀刻光致抗蚀图形的侧面。 When SF6 etching of silicon, O2 can be used for etching the side surface of the photo resist pattern. 这可以相应地使半导体层120形成为具有锥形边缘。 This may accordingly the semiconductor layer 120 is formed to have a tapered edge. 通过O2和SF6的流速/体积比,能够调节半导体层120的边缘的锥角。 By O2 and SF6 flow rate / volume ratio, the taper angle can be adjusted edges of the semiconductor layer 120.

接下来,在半导体层120上形成覆盖半导体层120的栅绝缘层130。 Next, on the semiconductor layer 120 covers the semiconductor layer 120. The gate insulating layer 130 is formed. 栅绝缘层130由例如氧化硅层或氮化硅层形成。 A gate insulating layer 130 is formed of silicon oxide layer or a silicon nitride layer. 然而,由于氧化硅良好的介电强度,优选栅绝缘层130由氧化硅层形成。 However, since the silicon oxide good dielectric strength, the gate insulating layer 130 is preferably formed of a silicon oxide layer. 虽然其它技术也可使用,但优选栅绝缘层130通过低温PECVD形成。 Although other techniques may also be used, but preferably the gate insulating layer 130 is formed by low-temperature PECVD.

半导体层120被形成为具有80或更小的锥角边缘。 The semiconductor layer 120 is formed to have a 80 or smaller cone angle edge. 这种锥角的选择有助于防止淀积的栅绝缘层130在半导体层120的侧面变薄的现象。 This helps prevent selection of the cone angle of the gate insulating layer 130 is deposited on the side surface of the semiconductor layer 120 of the thinning phenomenon. 当栅绝缘层130在半导体层120的侧面变薄时,栅绝缘层130在薄处能呈现出介电击穿。 When the gate insulating layer 130 in the side surface of the semiconductor layer 120 is thin, a gate insulating layer 130 at the thin portions can exhibit dielectric breakdown. 因此,半导体层120被形成为具有80或更小的锥角边缘,栅绝缘层130能够均匀地在半导体层120的上面和侧面形成。 Therefore, the semiconductor layer 120 is formed to have a 80 or smaller cone angle edge, the gate insulating layer 130 can be uniformly at the top and the side surface of the semiconductor layer 120 is formed. 因此,可提高栅绝缘层130的介电强度。 Therefore, to improve the gate dielectric strength of the insulating layer 130.

半导体层120的边缘的锥角优选约为30或更大。 The taper angle is preferably edge semiconductor layer 120 is about 30 or greater. 当锥角小于约30时,低于30的薄边缘导致半导体120的电阻增大。 When the cone angle is less than about 30 , the thin edge of less than 30 results in resistance of the semiconductor 120 is increased. 这使产生于半导体层120中的沟道电阻增大。 This allows to produce the semiconductor layer 120 in the channel resistance increases. 更优选地是,为了平衡电阻特性和介电强度特性,半导体120的边缘的锥角可以在约60~约75之间。 More preferably, in order to balance the resistance characteristics and dielectric strength characteristics of the semiconductor edge 120 of the taper angle may be between about 60 ~ about 75 .

另外,可以在栅绝缘层130上淀积栅电极材料,并构图,形成栅电极140。 Further, may be deposited on the gate insulating layer 130 of the gate electrode material, and patterned to form a gate electrode 140. 然后,使用栅电极140作为掩模,注入杂质到半导体层120。 Then, using the gate electrode 140 as a mask, impurities are injected into the semiconductor layer 120. 因此,在半导体层120中形成源/漏区120a。 Thus, the source / drain region 120a is formed in the semiconductor layer 120. 位于源/漏区120a之间的区域可限定为沟道区120b。 In the source / drain regions 120a may be defined as the region between the channel region 120b.

另外,可以形成覆盖具有栅电极140的衬底整个表面的中间层150,在中间层150中形成各自暴露源/漏区120a之一的源/漏接触孔150a。 Further, an intermediate layer may be formed to cover the gate electrode 140 of the entire substrate surface 150, form respective exposed source / drain regions 120a, one of the source / drain contact hole 150a in the intermediate layer 150. 在形成源/漏接触孔150a处的衬底之上,可以淀积源/漏电极材料。 Is formed on top of the source / drain contact holes 150a of a substrate, may be deposited source / drain electrode material. 通过这种方式构图,可以形成分别通过源/漏接触孔150a与源/漏区120a接触的源/漏电极160。 In this way patterning, respectively source may be formed by contacting the source / drain hole 150a and the source / drain regions 120a of the contact / drain electrode 160.

图3示出了根据本发明另一实施例的底栅薄膜晶体管和其制造方法的截面图。 Figure 3 shows a sectional view of a bottom gate thin film transistor according to another embodiment of the present invention and its manufacturing method.

提供如图3所示的衬底300。 Providing a substrate 300 shown in FIG. 3. 在衬底300上可淀积栅电极材料并在淀积的栅电极材料上形成光致抗蚀图形(未示出)。 May be deposited on the substrate 300 and the gate electrode material on the gate electrode material is deposited to form a photoresist pattern (not shown). 用光致抗蚀图形作掩模,可以蚀刻栅电极材料,形成栅电极320。 The photoresist pattern as a mask, etching the gate electrode material may be, to form the gate electrode 320. 栅电极320可形成具有约80或更小角度的锥角边缘。 The gate electrode 320 may be formed of about 80 or more edges of a small angle cone angle. 优选的是通过具有优良的蚀刻均匀性和低蚀刻CD损失的干法蚀刻,蚀刻栅电极材料。 Preferably by dry etching excellent in etch uniformity and low CD loss etching, the etching the gate electrode material. 而且,优选的是使用O2和SF6的混合气体作为刻蚀气体,形成具有锥角边缘的栅电极320。 Moreover, it is preferred to use a mixed gas of SF6 and O2 as an etching gas, to form a gate electrode 320 having a taper angle edge. 如上所述,O2可用于蚀刻光致抗蚀图形的侧面。 As described above, O2 can be used for etching the side surface of the photo resist pattern. 这可使该层具有锥角边缘。 This allows the layer has a taper angle of an edge. 通过控制O2和SF6的流速/体积比,调整栅电极320中边缘的锥角。 By controlling the flow rate of O2 and SF6 / volume ratio, adjust the taper angle of the gate electrode 320 in the edge.

对于平板显示器来说,当在形成栅电极320同时形成的栅极布线的电阻特性和蚀刻CD损失平衡时,栅电极320厚度介于约500~约3000之间是优选的。 For flat panel displays, when an etching resistance characteristic and CD loss in the gate electrode 320 is formed of a gate wiring while the balance, the thickness of the gate electrode 320 is interposed between about 500 ~ about 3000 preferred.

另外,在栅电极320上淀积栅绝缘层330。 Further, the gate electrode 320 is deposited on the gate insulating layer 330. 栅绝缘层330由例如氧化硅层或氮化硅层形成。 A gate insulating layer 330 is formed of e.g., silicon oxide layer or a silicon nitride layer. 优选的是,栅绝缘层330利用氧化硅层形成。 Preferably, the gate insulating layer 330 is formed using a silicon oxide layer. 另外,通过低温PECVD法或其它类似的方法,形成栅绝缘层330是优选的。 Further, low temperature PECVD, or other similar methods, a gate insulating layer 330 is preferable.

形成的栅电极320具有约80或更小的锥角边缘。 Gate electrode 320 is formed of about 80 or less cone angle edge. 这可以减弱栅绝缘层330在栅电极320的边缘变得太薄的问题。 This can weaken the gate insulating layer 330 on the edge of the gate electrode 320 becomes too thin a problem. 当栅绝缘层330在栅电极320的边缘变薄时,在栅绝缘层330的薄处出现介电击穿。 When the gate insulating layer 330 on the edge of the gate electrode 320 of the thin, appears in the gate insulating layer 330 at the thin dielectric breakdown. 因此,栅电极320可具有80或更小的锥角边缘,以使能够在栅电极320的上面和侧面均匀形成栅绝缘层330。 Therefore, the gate electrode 320 may have a 80 or smaller cone angle edge, so that the gate insulating layer 330 can be uniformly formed on the gate electrode 320 of the top and side. 因此,能够提高栅绝缘层330的介电强度。 Therefore, the gate insulating layer 330 can be improved dielectric strength.

出于与前边的实施例同样的原因,栅电极320中边缘的锥角具有30或更大是优选的。 For the same reason the front embodiment, the taper angle of the edge of the gate electrode 320 having a 30 or more is preferred.

另外,可在栅绝缘层330上依次形成半导体层和欧姆接触层。 In addition, the semiconductor layer and the ohmic contact layer are sequentially formed on the gate insulating layer 330. 这里,优选的是,半导体层由非晶硅形成,欧姆接触层可以是非晶硅中掺入杂质的区域。 Here, it is preferable that a semiconductor layer formed of amorphous silicon, amorphous silicon ohmic contact layer may be incorporated impurity region. 然而,在由非晶硅形成半导体层之后,通过ELA、SLS、MIC、MILC等使其结晶,形成多晶硅层。 However, after a semiconductor layer formed of amorphous silicon, by ELA, SLS, MIC, MILC, etc. to crystallize, forming a polysilicon layer. 对欧姆接触层和半导体层依次构图,形成半导体图形340和欧姆接触层图形350。 Ohmic contact layer and the semiconductor layer are sequentially patterned to form the semiconductor pattern 340 and the ohmic contact layer pattern 350. 在本实施例中,形成的半导体图形340覆盖栅电极320。 In the present embodiment, the semiconductor pattern 340 is formed to cover the gate electrode 320.

另外,在欧姆接触层图形350上淀积源/漏电极材料,并构图,形成源/漏电极360。 Further, on the ohmic contact layer pattern 350 is deposited source / drain electrode material, and patterned to form a source / drain electrode 360. 在本实施例中,半导体层图形340暴露在源/漏电极360之间。 In the present embodiment, the semiconductor layer pattern 340 is exposed between the source / drain electrode 360.

为了进一步帮助读者理解本发明,下面说明几个实施例。 To further assist the reader in understanding the invention, several embodiments will now be described.

实施例1在绝缘衬底上形成非晶硅层,构图,形成厚500的多晶硅层。 Example 1 forming an amorphous silicon layer is patterned on an insulating substrate, forming a thick 500 polysilicon layer. 在多晶硅层上形成光致抗蚀图形。 Is formed on the polysilicon layer photoresist pattern. 用光致抗蚀图形作掩模,蚀刻多晶硅层,形成半导体层。 The photoresist pattern as a mask, etching the polysilicon layer, forming the semiconductor layer. 使用比例为120/180sccm的SF6/O2气体,蚀刻多晶硅,形成半导体层。 Using the ratio of 120 / 180sccm of SF6 / O2 gas, etching the polysilicon, forming the semiconductor layer. 另外,在半导体层上PECVD淀积1000厚的氧化硅层,形成栅绝缘层。 Further, on the semiconductor layer is deposited PECVD silicon oxide layer 1000 thick, forming a gate insulating layer. 在栅绝缘层上形成栅电极,从而制得本实施例的薄膜晶体管。 Forming a gate electrode on the gate insulating layer, to thereby produce a thin film transistor according to the present embodiment.

实施例2在本实施例中,除了使用比例为100/200sccm的SF6/O2气体,蚀刻多晶硅层外,用与实施例1中相同的方法,制造薄膜晶体管。 Example 2 In the present embodiment, in addition to using a ratio of 100 / 200sccm of SF6 / O2 gas, etching the polysilicon layer, in Example 1 in the same method of manufacturing a thin film transistor.

比较例1除了使用比例为150/150sccm的SF6/O2气体,蚀刻多晶硅层外,用与实施例1中相同的方法,制造薄膜晶体管。 Comparative Example 1 Apart from the use of a ratio of 150 / 150sccm of SF6 / O2 gas, etching the polysilicon layer, in the same manner as in Example 1 was carried out, producing a thin film transistor.

比较例2除了使用比例为150/50sccm的SF6/O2气体,刻蚀多晶硅层外,用与实施例1中相同的方法,制造薄膜晶体管。 Comparative Example 2 except that the ratio of 150 / 50sccm of SF6 / O2 gas, etching the polysilicon layer, the use of Example 1 in the same manner, producing a thin film transistor.

如图4所示,对于实施例1的薄膜晶体管,半导体层中边缘的锥角R具有约78的角度。 As shown in Figure 4, for the thin film transistor of Example 1, the semiconductor layer has a taper angle R edge of an angle of about 78 . 如图5A所示,对于实施例2的薄膜晶体管,半导体层中边缘的锥角S具有约60的角度。 5A, for example a thin film transistor 2 embodiment, the taper angle of the edge of the semiconductor layer S has an angle of approximately 60 . 如图6A所示,对于比较例1的薄膜晶体管,半导体层中边缘的锥角T具有约82的角度。 As shown in Figure 6A, for the thin film transistor of Comparative Example 1, the taper angle T of the semiconductor layer having an edge angle of about 82 of. 如图7A所示,对于比较例2的薄膜晶体管,半导体层中边缘的锥角U具有约90的角度。 As shown in Figure 7A, for the thin film transistor of Comparative Example 2, the cone angle of the semiconductor layer in a U edge has an angle of approximately 90 .

图4B、5B、6B和7B是分别示出实施例1、实施例2、比较例1和比较例2的薄膜晶体管中栅绝缘层的介电强度图。 FIG. 4B, 5B, 6B and 7B are graphs showing Example 1, Example 2, Comparative Example 1 and Comparative Example 2, the thin film transistor gate dielectric strength of the insulating layer in FIG. 在图中,X轴表示栅电极和半导体层之间的电场(MV/cm),Y轴表示在栅电极处测得的漏电流(A)。 In the figure, X axis represents the electric field (MV / cm) between the gate electrode and the semiconductor layer, Y-axis represents the gate electrode of the measured leakage current (A).

如图4B和5B所示,对于实施例1和2的薄膜晶体管,直至栅电极和半导体层之间的电场达到约5MV/cm时,漏电流大致保持为定值(约110-12A)。 4B, and 5B, a thin film transistor for Examples 1 and 2 embodiment, until the electric field between the gate electrode and the semiconductor layer reaches approximately 5MV / cm As shown, the leakage current is substantially maintained at a constant value (about 1 10-12A) . 因此,提高了实施例1和实施例2的薄膜晶体管中的栅绝缘层的介电强度。 Therefore, improving the dielectric strength in Example 1 and Example 2 in the thin film transistor gate insulating layer implementation.

如图6B和7B所示,对于比较例1和2的薄膜晶体管,当栅电极和半导体层之间的电场超过2MV/cm时,栅极漏电流呈现迅速增长。 As shown in Figure 6B, Comparative Examples 1 and 2 of the thin film transistor, when the electric field between the gate electrode and the semiconductor layer exceeds 2MV / cm, the gate leakage current exhibits rapid growth 7B. 这表示栅绝缘层被介电击穿。 This means that a gate insulating layer is a dielectric breakdown. 这种击穿会导致薄膜晶体管故障。 This breakdown can cause thin film transistor failure. 也会导致使用薄膜晶体管的显示器出现缺陷。 Will lead to the use of thin-film transistor display defects. 这种情况下的缺陷包括点缺陷、线缺陷或亮度不均匀。 Defects in this case include point defects, line defects, or luminance unevenness.

如上所述,根据本发明,栅绝缘层的底图形可以具有80或更小的锥角的边缘,从而提高栅绝缘层的介电强度。 As described above, according to the present invention, the gate insulating layer pattern may have a bottom edge of the taper angle of 80 or less, thereby increasing the gate insulating layer of dielectric strength. 因此,能够阻止薄膜晶体管的故障和呈现的缺陷(当薄膜晶体管用于显示器时)。 Therefore, failure can be prevented, and the thin film transistor exhibits defects (time when a thin film transistor for a display).

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN101236993B31 Jan 20082 Mar 2011三菱电机株式会社Thin film transistor, method of producing the same, and display device using the thin film transistor
CN101263604B1 Jun 200630 May 2012夏普株式会社Thin film transistor
CN101626034B11 Dec 200815 Feb 2012乐金显示有限公司薄膜晶体管及其制造方法
US78590551 Jun 200628 Dec 2010Sharp Kabushiki KaishaThin film transistor
Classifications
International ClassificationH01L29/786, H01L29/423, H01L21/336
Cooperative ClassificationH01L29/78675, H01L29/42384, H01L29/78609, H01L29/66757, H01L29/66765, H01L29/78678
European ClassificationH01L29/66M6T6F15A2, H01L29/66M6T6F15A3, H01L29/423D2B8, H01L29/786E4C4, H01L29/786B2, H01L29/786E4C2
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