CN1416591A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN1416591A
CN1416591A CN01804753A CN01804753A CN1416591A CN 1416591 A CN1416591 A CN 1416591A CN 01804753 A CN01804753 A CN 01804753A CN 01804753 A CN01804753 A CN 01804753A CN 1416591 A CN1416591 A CN 1416591A
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monocrystalline
layer
compound semiconductor
semi
insulating barrier
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CN1261978C (zh
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贾马尔·拉姆戴尼
拉维德拉那斯·德鲁帕德
莱蒂·L·希尔特
库尔特·W·埃森伯萨
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NXP USA Inc
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Motorola Inc
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Abstract

通过首先生长一个适应缓冲层(24)可以生长高质量的化合物半导体材料的外延层，覆盖晶格不匹配的基片，最好为硅基片。适应缓冲层是通过优选的氧化硅的无定形氧化物分界层(28)与基片(22)相分隔的单晶绝缘体(24)的层面。该无定形分界层消除应力，并且允许生长高质量的单晶绝缘体适应缓冲层(24)，其最好为例如碱土金属钛化物、锆化物等等这样的钙钛矿氧化物材料。

Description

半导体结构
技术领域
本发明一般涉及半导体结构及其制造方法，更加具体来说涉及化合物半导体结构以及包括化合物半导体材料的半导体结构的制造和使用。
背景技术
绝大部分半导体分离元件和集成电路是由硅制造的，这至少部分因为能够获得廉价和高质量的单晶硅基片。例如所谓的化合物半导体材料这样的其它半导体材料具有某些物理特性，包括比硅更宽的能带隙和/或较高的迁移率，或者直的能带隙，这使得这些材料对于特定类型的半导体器件有利。但是，化合物半导体材料通常比硅更加昂贵并且不能够像硅那样获得大晶片。作为最容易获得的化合物半导体材料，砷化镓(GaAs)仅仅可以获得直径大约为150毫米(mm)的晶片。相反，硅晶片可以大到300毫米，并且通常可以获得200毫米的直径。150毫米的GaAs晶片比相应的硅晶片要贵许多倍。其它化合物半导体材料的晶片比GaAs更加不容易获得并且更加昂贵。
由于化合物半导体材料的所需特性，以及由于它们具有高成本并且不容易获得大体积的产品，许多年来人们尝试在异质基片上生长化合物半导体材料的薄膜。但是，为了获得该化合物半导体材料的优良特性，需要较高结晶质量的单晶薄膜。例如，尝试在锗、硅和各种绝缘体上生长单金化合物半导体材料的层面。这些尝试通常是不成功的，因为在基质晶体和生长晶体之间的晶格不匹配造成化合物半导体材料的薄膜具有较低的结晶质量。
如果能够以较低成本获得高质量的单晶化合物半导体材料的大面积薄膜，则与在化合物半导体材料的大晶片上制造这种器件或者在化合物半导体材料的大晶片上这种材料的外延膜中制造这种器件的成本相比，能够以低成本有利地制造多种半导体器件。另外，如果可以在例如硅晶片这样的大晶片上实现高质量的单晶化合物半导体材料的薄膜，则可以利用硅和化合物半导体材料的最佳特性获得集成器件结构。
另外，需要一种半导体结构，其在另一个单晶材料上提供高质量的单晶化合物半导体膜薄，以及对这种结构进行处理。
附图说明
本发明通过举例说明但不限于附图中所示，其中相同的标号表示相同的元件，其中：
图1、2、4、5简要地示出根据本发明各个实施例的器件结构的截面示图；
图3示出最大可获得的薄膜厚度与基质晶体和生长的结晶覆盖层之间的晶格不匹配的关系的示意图；
图6包括一种通信设备的一部分的方框图；
图7-11包括集成电路的一部分的截面示图，该集成电路包括化合物半导体部分、双极型部分和MOS部分；以及
图12-18包括另一种集成电路的一部分的截面示图，其中包括半导体激光器和MOS晶体管。
本领域的技术人员将认识到在图中的部件用于简单清楚地说明，并且不一定是按照比例描绘。例如，在图中一些元件的尺寸可能相对于其它元件被夸大，以有助于对本发明的实施例的理解。
附图的详细描述
图1简要示出根据本发明一个实施例的半导体结构20的一部分的截面示图。半导体结构20包括一个单晶基片22，由单晶材料所构成的适应缓冲层24、以及单晶化合物半导体材料的层面26。在上下文中，术语“单晶”应当具有在半导体工业中通常使用的含义。该术语应当是指作为单晶体或者基本上是单晶体的材料，并且应当包括具有例如错位等等这样相对较小的缺陷的材料，这些缺陷通常都会在硅或锗，或者硅和锗的混合物的基片中出现，以及包括在半导体工业中通常存在的这种材料的外延层。
根据本发明的一个实施例，结构20还包括一个置于基片22与适应缓冲层24之间的无定形中间层28。结构20可以包括在适应缓冲层与化合物半导体层26之间的模板层30。如下文更加详细地描述，该模板层有助于启动该化合物半导体层在适应缓冲层上的生长。该无定形中间层有助于释放在适应缓冲层上的应力，由此有助于高结晶质量的适应缓冲层的生长。
根据本发明的一个实施例，基片22是一个单晶半导体晶片，最好具有大直径。该晶片可以由来自元素周期表的IV族的材料所制成，并且最好是来自IVA族的材料。IV族半导体材料的例子包括硅、锗、混合的硅和锗、混合的硅和碳、混合的硅、锗和碳，等等。基片22优选的是包含硅或锗的晶片，最好是用于半导体工业中的高质量的单晶硅晶片。适应缓冲层24优选的是在下层基片上外延生长的单晶氧化物或氮化物材料。根据本发明一个实施例，在层面24的生长过程中，通过基片22的氧化，把无定形中间层28生长在基片22上，在基片22与该生长中的适应缓冲层之间的界面上。无定形中间层用于释放由于基片与缓冲层的晶格常数不同而可能在单晶适应缓冲层中出现的应力。如在此所用，晶格常数是指在表面的平面中测量的单元的原子之间的距离。如果这种应力没有被无定形中间层所释放，则该应力可能会在适应缓冲层的晶体结构中造成缺陷。在适应缓冲层的晶体结构中的缺陷反过来会导致难以在单晶化合物半导体层26中获得高质量的晶体结构。
适应缓冲层24最好为一种单晶氧化物或氮化物材料，其被选择用于与下层基片以及与覆盖的化合物半导体材料具有晶体兼容性。例如，该材料可以是具有与基片以及与随后施加的半导体材料相匹配的晶格结构的氧化物或氮化物适用于该适应缓冲层的材料包括金属氧化物，例如碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐、碱土金属钒酸盐、碱土金属锡基钙钛矿(perovskite)、铝酸镧、镧钪氧化物和轧氧化物。另外，例如氮化镓、氮化铝和氮化硼这样的各种氮化物还可以用作为该适应缓冲层。这些材料大多为绝缘体，但是例如钌酸锶为导体。通常，这些材料为金属氧化物或金属氮化物，更加具体来说，这些金属氧化物或氮化物一般包括至少两种不同的金属元素。在一些特定的应用中，该金属氧化物或氮化物可以包括三种或更多的不同的金属元素。
无定形界面层28最好为通过对基片22的表面氧化而形成的氧化物，并且最好由氧化硅所构成。该层面28的厚度能够充分排除由于基片22与适应缓冲层24的晶格常数之间的不匹配而导致的应力。一般来说，层面28具有大约0.5-5纳米范围的厚度。
根据对于特定半导体结构的需要，层面26的化合物半导体材料可以从任何IIIA和VA族元素(III-V半导体化合物)、混合的III-V化合物、II(A或B)和VIA族元素(II-VI半导体化合物)、以及混合的II-VI化合物。例如包括砷化镓(GaAs)、镓铟砷化物(GaInAs)、镓铝砷化物(GaAlAs)、磷化铟(InP)、硫化镉(CdS)、镉汞碲化物(CdHgTe)、硒化锌(ZnSe)、锌硫硒化物(ZnSSe)等等。适当的模板材料在所选择的位置化学键合到适应缓冲层24的表面上，并且为后续化合物半导体层26的外延生长的成核提供位置。适用于模板30的材料在下文中讨论。
图2示出根据本发明另一个实施例的半导体结构40的一部分的截面示图。材料40类似于上文所述的半导体结构20，只是额外的缓冲层30被置于适应缓冲层24与单晶化合物半导体材料26的层面之间。具体来说，额外的缓冲层被置于模板层30和化合物半导体材料的覆盖层之间。当适应缓冲层的晶格常数不能与覆盖的单晶化合物半导体材料层相匹配时，由半导体或化合物半导体材料所形成的额外缓冲层用于提供晶格补偿。
如下非限制性的例子说明用于根据本发明的各种实施例中的结构20和结构40的材料的各种组合。这些例子仅仅是说明性的，而不是把本发明限制于这些实施例。
例子1
根据本发明一个实施例，单晶基片22是定向在(100)方向上的硅基片。该硅基片例如可以是通常用于制作具有大约200-300毫米的直径的互补金属氧化物半导体(CMOS)集成电路中的硅基片。根据本发明的这一实施例，适应缓冲层24是一个SrzBa1-zTiO3的单晶层，其中z的范围是从0至1，并且该无定形中间层是形成在硅基片和适应缓冲层之间的界面上的氧化硅(SiOx)的层面。z的数值被选择以获得一种或多种晶格常数，其接近匹配于后续形成的层面26的相应晶格常数。适应缓冲层可以具有大约2至大约100纳米(nm)的厚度并且最好具有大约10纳米的厚度。通常，需要使适应缓冲层的厚度足以把该化合物半导体层与该基片相绝缘，以获得所需的电和光特性。比100纳米厚的层面通常提供较少的额外优越性，而且不必要的增加了成本；但是如果需要的话可以制造较厚的层面。氧化硅的无定形中间层可以具有大约0.5-5纳米的厚度，并且最好为大约1.5-2.5纳米的厚度。
根据本发明的实施例，化合物半导体材料层26是具有大约1纳米至大约100微米厚度的砷化镓(GaAs)或铝镓砷化物(AlGaAs)，并且最好为大约0.5微米至10微米的厚度。该厚度通常决定于该层面的应用。为了促进在单晶氧化物上外延生长砷化镓或铝镓砷化物，通过覆盖该氧化层而形成模板层。模板层最好为1-10层的单层Ti-As、Sr-O-As、Sr-Ga-O或者Sr-Al-O。通过一个优选例子，1-2层的单层Ti-As或Sr-Ga-O上能够成功地生长GaAs层。
例子2
根据本发明的另一个实施例，单晶基片22是如上文所述的硅基片。适应缓冲层是具有形成于硅基片和适应缓冲层之间的界面上的氧化硅的无定形中间层的处于立方相或正斜方晶相的单晶氧化锶或锆酸钡或者铪酸钡。该适应缓冲层可以具有大约2-100纳米的厚度并且最好具有至少5纳米的厚度以保证获得适当的晶体和表面质量，并且由单晶SrZrO3、BaZrO3、SrHfO3、BaSnO3或BaHfO3所形成。例如，BaZrO3的单晶氧化层可以在大约700℃的温度下生长。所获得的结晶氧化物的晶格结构相对于基片半导体晶格结构具有45度的旋转。
一个由锆酸盐或铪酸盐材料所形成的适应缓冲层适合于在磷化铟(InP)系统中生长化合物半导体材料。该化合物半导体材料例如可以是具有大约1.0纳米至10微米厚度的磷酸铟(InP)或者铟镓砷化物(InGaAs)。一种适合的用于该结构的模板是1-10的单层锆-砷(Zr-As)、锆-磷(Zr-P)、铪-砷(Hf-As)、铪-磷(Hf-P)、锶-氧-砷(Sr-O-As)、锶-氧-磷(Sr-O-P)、钡-氧-砷(Ba-O-As)、铟-锶-氧(In-Sr-O)或者钡-氧-磷(Ba-O-P)，并且最好为这些材料之一的1-2的单层。例如，对于锆酸钡适应缓冲层，该表面通过在1-2的单层锆上淀积1-2的单层砷而完成，以形成Zr-As模板。来自磷化铟系统的化合物半导体材料的单晶层然后生长在该模板层上。导致该化合物半导体材料的所得晶格结构相对于适应缓冲层晶格结构表现出45度的旋转，并且对于(100)InP的晶格不匹配小于2.5％，并且最好小于大约1.0％。
例子3
根据本发明的另一个实施例，提供一种适合于生长覆盖硅基片的II-VI材料的外延膜的结构。该基片最好是如下文所述的硅晶片。一种适合的适应缓冲层是SrxBa1-xTiO3，其中x的范围是从0至1，具有大约2-100纳米的厚度，并且最好厚度为大约5-15纳米。该II-VI化合物半导体材料例如可以是硒化锌(ZnSe)或者锌硫硒化物(ZnSSe)。用于该材料系统的适合的模板包括在1-10的单层锌-氧(Zn-O)上形成1-2的单层额外锌，随后在该表面上对锌执行硒化。另外，一个模板例如可以是在锶-硫(Sr-S)之上形成ZnSeS。
例子4
本发明的该实施例是图2中所示的结构40的一个例子。基片22、单晶氧化层24和单晶化合物半导体材料层26类似于例子1中所述。另外，额外的缓冲层32用于减轻由于适应缓冲层的晶格与单晶半导体材料的晶格的不匹配所导致的任何应力。缓冲层32可以是镓砷磷化物(GaAsxP1-x)或者铟镓磷化物(InyGa1-yP)应力补偿的超晶格。在镓砷磷化物超晶格中，x数值的范围是从0至1，并且在铟镓磷化物超晶格中，y的数值为从0至1。通过改变x或y的数值，根据情况，晶格常数从底部到顶部跨过超晶格，以形成下层氧化物与上层化合物半导体材料的晶格常数之间的匹配。超晶格可以具有大约50-500纳米的厚度，并且最好具有大约200-100纳米的厚度。用于该结构的模板可以与例子1中所述的相同。另外，缓冲层可以是具有1-50纳米厚度的单晶锗的层面，并且最好具有大约2-20纳米的厚度。在使用锗缓冲层中，可以使用具有大约一个单层厚度的锗-锶(Ge-Sr)或锗-钛(Ge-Ti)的模板层。氧化层的形成被单层的锶或单层的钛所覆盖，以作为用于后续淀积单层锗的成核位置。单层的锶或钛提供一个可以键合锗的第一单层的成核位置。
例子5
本例还说明用于如图2中所示结构40中的材料。基片材料22、适应缓冲层24、单晶化合物半导体材料层26和模板层可以与上述例子2中的相同。另外，缓冲层32被插入在适应缓冲层和覆盖单晶化合物半导体材料层之间。该缓冲层，另外的一个单晶半导体材料，例如可以是铟镓砷化物(InGaAs)的递变层，其中铟组份从0变为大约47％。该缓冲层最好具有大约10-30纳米的厚度。把缓冲层的组份从GaAs变为InGaAs用于提供下层单晶氧化物材料与上层单晶化合物半导体材料之间的晶格匹配。如果适应缓冲层24与单晶化合物半导体材料层26之间的晶格不匹配，则这种缓冲层特别有利。
再次参见图1和2，基片22是一个单晶基片，例如单晶硅基片。该单晶基片的晶体结构的特征在于晶格常数和晶格方向。按照类似的方式，适应缓冲层24也是一种单晶材料，并且该单晶材料的晶格的特征是晶格常数和晶格方向。该适应缓冲层和单晶基片的晶格常数必须接近匹配，或者必须在一个晶体方向相对于另一个晶体方向旋转之后，获得基本上匹配的晶格常数。在上下文中，术语“基本上相等”和“基本上匹配”的含义是在晶格常数之间足够接近以能够在下层上生长高质量的结晶层。
图3示出作为在基质晶体和生长晶体的晶格常数之间不匹配的一个函数，高结晶质量的生长结晶层的可获得厚度的关系的曲线图。曲线42表示高结晶质量材料的边界。在曲线42的右侧的区域表示要成为多晶体的层面。由于没有晶格不匹配，则理论上能够在基质晶体上生长无限厚的高质量外延层。由于晶格常数不匹配增加，可获得的高质量结晶层的厚度迅速减小。作为一个参考点，例如如果基质晶体和生长层之间的晶格常数不匹配程度大约为2％，因此不能够获得超过大约20纳米的单晶外延层。
根据本发明一个实施例，基片22是一种(100)或(111)方向的单晶硅晶片，并且适应缓冲层24是锶钡钛酸盐的层面。通过把钛酸盐材料的晶体方向相对于硅基晶片的晶体方向旋转45度，使这两种材料之间的晶格基本上匹配。在无定形界面层24(在本例中为氧化硅层)的结构中的内含物用于减小由于基质硅晶片与生长的钛酸盐层的晶格常数中的任何不匹配所导致的在钛酸盐单晶层中的应力。结果，根据本发明的实施例，可以获得高质量、厚的单晶钛酸盐层。
仍然参见图1和2，层面26为外延生长的单晶化合物半导体材料的层面，并且该结晶材料的特征也在于晶格常数和晶体方向。为了在该外延生长层面中获得高的结晶质量，适应缓冲层必须具有高的结晶质量。另外，为了在层面26中获得高的结晶质量，在这种情况中，需要基质晶体、单晶适应缓冲层和生长晶体的晶格常数之间基本上匹配。利用适当选择的材料，由于生长晶体的晶体方向相对于基质晶体的方向旋转的结果，基本上实现晶格常数的匹配。如果生产晶体是砷化镓、铝镓砷化物、硒化锌或者锌硫硒化物，并且该适应缓冲层为单晶的SrxBa1-xTiO3，则基本上实现两种材料的晶格常数相匹配，其中生长层的晶体方向相对于基质单晶氧化物的方向旋转45度。类似地，如果基质材料是锶或钡的锆酸盐，或者锶或钡的铪酸盐，或者钡锡氧化物，并且化合物半导体层是磷化铟或镓铟砷化物或者铝铟砷化物，则通过把生长晶体层相对于基质氧化物晶体旋转45度而获得晶格常数的基本匹配。在一些例子中，基质氧化物和生长化合物半导体层之间的晶体半导体缓冲层可以用于减小在生长单晶化合物半导体层中的应力，这可能导致晶格常数中出现小差别。从而可以在生长单晶化合物半导体层中获得更好的晶体质量。
如下文的例子说明根据本发明一个实施例的用于制造例如图1和2中所示结构的半导体结构的一个处理工艺。该处理工艺首先提供由硅或锗所构成的单晶半导体基片。根据本发明的一个优选实施例，该半导体基片是具有(100)方向的硅晶片。该基片最好定向在轴上，获得最多大约偏离轴0.50度。至少半导体基片的一部分具有暴露表面，但是如下文所述该基片的其它部分可以包括其它结构。在上下文中的术语“暴露”的含义是在该基片的部分中的表面被清洁以除去任何氧化物、污染物或者其它异质材料。众所周知，暴露的硅是具有较高的反应作用，并且容易形成自然氧化物。术语暴“暴露”是指包含这种自然氧化物。也可以特意在半导体基片上生长薄的氧化硅，但是这种生长的氧化物对于本发明的处理工艺来说并不重要。为了在单晶基片上外延生长单晶氧化层，必须首先除去该自然氧化层，以暴露出下层基片的晶体结构。如下处理最好通过分子束外延生长技术(MBE)来执行。自然氧化物可以首先通过在MBE装置中热淀积一个薄的锶层而除去。然后把基片加热到大约750℃的温度，使得锶与自然氧化硅层进行反应。该锶用于减少氧化硅，以产生无氧化硅的表面。表现出有序的2×1结构的所获得表面包括锶、氧和硅。该有序的2×1结构形成用于单晶氧化物的覆盖层的有序生长的模板。该模板提供所需的化学和物理特性，以为覆盖层的晶体生长形成晶核。
根据本发明的另一个实施例，通过在低温下用MBE把氧化锶淀积到基片表面，并且随后把该结构加热到大约750℃的温度，自然氧化硅可以被改变，并且基片表面可以准备用于单晶氧化层的生长。在该温度下，在氧化锶和自然氧化硅之间发生固态反应，导致减少自然氧化硅，并且在基片表面上保留具有锶、氧和硅的有序的2×1结构。再次，这形成用于有序的单晶氧化层的后续生长的模板。
下面从基片表面除去氧化硅，根据本发明一个实施例，该基片被冷却到大约400-600℃的温度，并且通过分子束外延生长技术在模板层上生长钛化锶的层面。通过打开MBE装置中的快门以露出锶、钛和氧源，从而启动MBE处理。锶和钛的比率大约为1∶1。氧的分压最初被设置为能够以大约0.3-0.5纳米每分种的生长速度来生长化学计量(100)的钛酸锶所需的最小值。在开始钛酸锶的生长之后，氧的分压被增加到大于初始最小值。氧的过压造成在下层基片和该生长的(100)钛酸锶层之间的界面上生长无定形硅氧化层。由于氧通过生长的钛酸锶层扩散到下层基片表面上氧与硅反应的界面，导致氧化硅层的生长。生长该(100)钛酸锶作为一个有序单晶，其具有相对于下层基片的有序2×1晶体结构旋转45度的晶体方向。在无定形硅氧化物中间层中减轻在硅基片的生长的晶体之间由于晶格常数中的小的不匹配而导致可能在钛酸锶层中存在的应力。
在已经把钛酸锶层生长到所需的厚度之后，单晶钛酸锶被有助于所需化合物半导体材料的外延层的后续生长的模板层所覆盖。为了砷化镓层的后续生长，可以通过用1-2的单层钛、1-2的单层钛-氧或者用1-2的单层锶-氧来结束该生长，而覆盖钛化锶单晶层的MBE生长。然后形成该覆盖层，淀积锶以形成Ti-As键、Ti-O-As键或者Sr-O-As。任何这些形成用于砷化镓单晶层的淀积和形成的适当模板。在模板形成之后，导入镓来与砷发生反应，并且形成砷化镓。另外，可以在覆盖层上淀积镓，以形成Sr-O-Ga键，并且导入砷与镓反应，以形成GaAs。
图2中所示的结构可以通过上述处理以及额外的附加缓冲层淀积步骤而形成。在淀积单晶化合物半导体层之前，形成覆盖模板层的该缓冲层。如果缓冲层为一种化合物半导体超晶格，这种超晶格例如可以通过MBE淀积在上述模板上。如果用锗层取代缓冲层，则上述处理被改变以用锶或钛的最后层面来覆盖该钛酸锶单晶层，然后通过淀积锗，以与锶或钛反应。该锗缓冲层然后可以直接淀积在该模板上。
上述处理说明用于通过分子束外延生长技术的处理形成半导体结构的一种处理，该半导体结构包括硅基片、单晶钛酸锶适应缓冲层、以及单晶砷化镓化合物半导体层。该处理还可以用化学汽相淀积(CVD)、金属有机化学汽相淀积(MOCVD)、迁移增强的外延生长(MEE)、原子层外延生长(ALE)等等方法来执行。另外，通过类似的处理，也可以生长其它单晶适应缓冲层，例如碱土金属钛酸盐、锆酸盐、铪酸盐、钽酸盐、钒酸盐、钌酸盐、铌酸盐、碱土金属锡基钙钛矿、铝酸镧、镧钪氧化物和轧氧化物。另外，通过例如MBE这样的类似方法，可以在单晶氧化物适应缓冲层上淀积其它III-V和II-VI单晶化合物半导体层。
化合物半导体材料和单晶氧化物适应缓冲层的每种变化使用适应的模板来启动化合物半导体层的生长。例如，如果适应缓冲层为碱土金属锆酸盐，则可以通过薄的锆层来覆盖该氧化物。淀积锆之后可以接着淀积砷或磷，以与锆反应，分别作为淀积铟镓砷化物、铟铝砷化物或者磷化铟层的母体。类似的，如果单晶氧化物适应缓冲层为碱土金属铪酸盐，则可以通过薄的铪层来覆盖该氧化物。淀积铪之后可以接着淀积砷或磷，以与铪反应，分别作为淀积铟镓砷化物、铟铝砷化物或者磷化铟层的母体。按照类似的方式，可以用锶或锶和氧的层面来覆盖钛酸锶，以及可以用钡或钡和氧的层面来覆盖钛酸钡。每次这些淀积之后接着淀积砷或磷，以与覆盖材料进行反应，形成用于淀积包括铟镓砷化物、铟铝砷化物或磷化铟的化合物半导体材料层的模板。
图4示出根据本发明另一个实施例的设备结构50的截面示图。设备结构50包括单晶半导体基片52，最好为单晶硅晶片。单晶半导体基片52包括两个区域，53和54。一般由曲线56所表示的一个电子半导体元件形成在区域53中。电子元件56可以是电阻器、电容器、有源半导体元件，例如二极管或三极管，或者例如CMOS集成电路这样的集成电路。例如，电子半导体元件56可以是被配置为执行数字信号处理或适合硅集成电路的其它功能的CMOS集成电路。在区域53中的电子半导体元件可以由常规的并且在半导体工业中广泛应用的公知半导体工艺所形成。例如二氧化硅等等这样的绝缘材料58的层面可以重叠在电子半导体元件56上。
绝缘材料58以及任何其它已经在半导体元件56的处理过程中在区域53中形成或淀积的层面被从区域54的表面上除去，以在该区域中提供暴露的硅表面。众所周知，暴露的硅表面是非常容易发生反应的，并且自然氧化硅膜会迅速地形成在暴露表面上。钡或钡和氧的层面被淀积到区域54表面上的自然氧化层上，并且与氧化表面发生反应，以形成第一模板层(未示出)。根据本发明一个实施例，通过分子束外延生长工艺在该模板层上形成单晶氧化层60。包括钡、钛和氧的反应物被淀积到该模板层上，以形成单晶氧化层。最初，在淀积过程中，氧的分压保持接近于需要与钡和钛发生反应以形成单晶钛酸钡层60所需的最小量。然后，氧的分压增加以提供氧的过压，并且使氧通过生长中的单晶氧化层扩散。通过钛酸钡扩散的氧与在区域54表面上的硅发生反应，以在第二区域上以及在硅基片与单晶氧化物之间的界面上形成氧化硅的非晶形层62。
根据本发明一个实施例，淀积单晶氧化物层60的步骤以淀积第二模板层64为结束，该第二模板层64可以是1-10的单层钛、钡、钡和氧、或钛和氧。然后通过分子束外延生长工艺淀积单晶化合物半导体材料的层面66，以覆盖第二模板层。通过把一个砷层淀积到该模板上而启动层面66的淀积。该初始步骤之后接着把镓和砷淀积，以形成单晶砷化镓。另外，锶可以代替上述例子中的钡。
根据本发明另一个实施例，通常由虚线68所表示的半导体元件被形成在化合物半导体层66中。半导体元件68可以通过通常用于制造砷化镓或者其它III-V化合物半导体材料器件中所用的处理步骤而形成。半导体元件68可以是任何有源或无源元件，并且最好是半导体激光发光二极管、光电检测器、异质结双极型晶体管(HBT)、高频MESFET、或者利用化合物半导体材料的物理特性的其它元件。由线70所示的金属导体可以形成为把器件68和器件56电连接，因此实现一个集成器件，其中包括至少形成在硅基片中的一个元件以及形成在单晶化合物半导体材料层中的一个器件。尽管所示的结构50已经被描述作为形成在硅基片52上并且具有钛酸钡(或锶)层60和砷化镓层66的一种结构，但是可以使用在本说明书中其它部分所述的其它结构、单晶氧化层和其它化合物半导体层制造类似的其它器件。
图5示出根据本发明另一个实施例的半导体结构72。结构72包括单晶半导体基片74，例如包括区域75和区域76的硅晶片。使用通常用于半导体工业中的常规硅器件处理系数把由虚线78所示的电子元件形成在区域75中。使用类似于上文所述的处理步骤，单晶氧化层80和中间无定形硅氧化层82形成在基片74的区域76上。模板层84以及随后的单晶半导体层86形成在单晶氧化物层80上。根据本发明另一个实施例，通过类似于用来形成层面80的处理步骤形成覆盖层面86的附加的单晶氧化物层88，以及通过类似于用来形成层面86的处理步骤形成覆盖单晶氧化物层88的附加单晶半导体层90。根据本发明一个实施例，至少层面86和90由化合物半导体材料所形成。
一般由曲线92所表示的半导体元件至少部分形成在单晶半导体层86上。根据本发明一个实施例，半导体元件92可以包括具有部分地由单晶氧化物层88所形成的栅绝缘体的场效应晶体管。另外，单晶半导体层92可以用于实现该场效应晶体管的栅极。根据本发明一个实施例，单晶半导体层86由III-V族化合物所形成，并且半导体元件92是应用III-V族元件材料的高迁移率特性的射频放大器。根据本发明另一个实施例，由线94所示的电互连线把元件78和元件92电互连。结构72如此利用两个单晶半导体材料的独特性能来集成元件。
通过更加具体的例子，在图6-18中示出其它集成电路和系统。图6包括一个简化的方框图，其中示出具有信号收发装置101、集成电路102、输出单元103和输入单元104的一部分通信设备100。信号收发装置的例子包括天线、调制解调器或者任何可以与外部设备之间收发信息或数据的其它装置。如在此所用，“收发”用于表示该信号收发装置可能仅仅能够接收、或仅仅能够发送、或者能够与通信设备之间接收和发送信号。输出单元103可以包括一个显示器、监视器、扩音器等等。输入单元可以包括话筒、键盘等等。请注意，在另一个实施例中，输出单元103和输入单元104可以由单个单元所代替，例如存储器等等。该存储器可以包括随机存取存储器或者非易失性存储器，例如硬盘、闪存卡或模块等等。
一个集成电路通常是在一个连续基片上或内部相关不可分离的至少两个电路元件的组合(例如，晶体管、二极管、电阻器、电容器等等)。集成电路102包括化合物半导体部分1022、双极型部分1024以及MOS部分1026。化合物半导体部分1022包括至少部分由化合物半导体材料所形成的电子元件。晶体管和其它在化合物半导体部分1022中的电子元件能够处理至少大约0.8GHz的射频信号。在其它实施例中，该信号可以是较低或较高频率。例如，一些材料，例如铟镓砷化物，能够处理在大约27GHz频率下的射频信号。
化合物半导体部分1022进一步包括双工器10222、射频-基带转换器10224(解调装置或解调电路)、基带-射频转换器10226(调制装置或调制电路)、功率放大器10228以及隔离器10229。双极型部分1024和MOS部分1026一般由IV族半导体材料所形成。双极型部分1024包括接收放大器10242、模-数转换器10244、数-模转换器10246以及发射放大器10248。MOS部分1026包括数字信号处理装置10262。这种装置的一个例子包括任何一个可以在市场上获得的通用DSP芯片，例如Motorola DSP 566xx(来自摩托罗拉公司，美国伊利诺斯州绍姆堡)以及德州仪器公司的数字信号处理器族TMS 320C54x(来自美国得克萨斯州的达拉斯)。该数字信号处理装置10262一般包括互补MOS(CMOS)晶体管和模-数以及数-模转换器。显然，其它电子元件也存在于该集成电路102中。
在一种操作模式中，通信设备100接收来自作为信号收发装置101的一部分的天线的信号。该信号通过双工器10227到达射频-基带转换器10224。模拟数据或其它信息被接收放大器10224所放大，并且发送到数字信号处理装置10262。在数字信号处理装置10262已经处理该信息或其它数据之后，所处理的信号或其它数据被发送到输出单元103。如果通信设备是传呼机，则输出单元可以是显示器。如果通信设备是移动电话，则输出单元103可以包括话筒、显示器或这两者都有。
数据或其它信息可以通过该通信设备100在相反方向上发送。数据或其它信息将通过输入单元104而到来。在移动电话中，可以包括话筒或键盘。然后，使用数字信号处理装置10262来处理该信息或其它数据。在处理之后，然后使用数-模转换器10246进行转换。所转换的信号被发射放大器10248所放大。放大后的信号被基带-射频转换器10226所调制，并且进一步被功率放大器10228所放大。所放大的射频信号通过隔离器10229和双工器10222到达天线。
该通信设备100的现有技术将具有至少两个分立的集成电路：一个用于化合物半导体部分1022以及一个用于MOS部分1026。该双极型部分1024可以在与MOS部分1026相同的集成电路上，或者可以是另一个集成电路。利用本发明的实施例，所有这三个部分现在可以形成在单个集成电路中。因为，所有晶体管可以位于单个集成电路上，该通信设备能够被大大地小型化，并且更大地增加通信设备的便携性。
现在针对如图7-11中所示用于形成集成电路102的示例部分的方法。在图7中，p型掺杂单晶硅基片110具有化合物半导体部分1022、双极型部分1024以及MOS部分1026。在双极型部分中，单晶硅基片被掺杂以形成N+埋置区1102。然后在埋置区1102和基片110上形成轻微p型掺杂的外延单晶硅层1104。然后执行掺杂步骤，以在N+埋置区1102上产生轻微n型掺杂的漂移区1117。该掺杂步骤把在双极型区域1024部分中轻微p型掺杂的外延层转换为轻微n型掺杂的单晶硅区域。场绝缘区1106然后形成在双极型部分1024和MOS部分1026之间。一个栅绝缘层1110形成在MOS部分1026中的外延层1104的一部分上，并且然后在栅绝缘层1110上形成栅电极1112。侧壁隔离1115沿着栅极1112和栅绝缘层1110的垂直侧壁而形成。
p型掺杂物被导入到漂移区117，以形成有源或固有基极区1114。n型深集电极区1108然后形成在双极型部分1024中，以电连接到埋置区1102。执行选择性的n型掺杂，以形成N+掺杂区1116和发射极区1120。N+掺杂区1116形成在沿着栅极1112的相邻侧的层面1104内，并且为用于MOS晶体管的源区、漏区或源/漏区。N+掺杂区1116和发射极区1120具有至少1E19个原子每立方厘米的掺杂浓度，以形成电阻接触。形成p型掺杂区，以创建无源或非固有的基极区1118，这是一个P+掺杂区(掺杂浓度至少为1E19个原子每立方厘米)。
在所述实施例中，已经执行几个处理步骤，但是没有示出或进一步描述，例如形成阱区、阈值调节注入、沟道击穿防止注入、场击穿防止注入、以及各种掩膜层。使用常规步骤执行到此所完成的器件形成工艺。如图所示，标准N沟道MOS晶体管已经形成在MOS区1026中，并且垂直NPN双极型晶体管已经形成在双极型部分1024中。到此为止，还没有电路形成在化合物半导体部分1022中。
已经在集成电路的双极型和MOS部分的处理过程中形成的所有层面现在被从化合物半导体部分1022的表面上除去。暴露硅表面如此被提供用于该部分的后续处理，例如按照上文所述的方式进行。
然后如图8中所示，在基片110上形成适应缓冲层124。该适应缓冲层将作为单晶层形成在部分1022的适当准备的(即，具有适当的模板层)暴露硅表面上。但是，形成在部分1024和1026上的部分层面124可以是多晶或无定型的，因为它形成在非单晶的材料上，因此没有成核单晶生长。该适应缓冲层124一般为单晶金属氧化物或者氮化物层，并且一般具有在大约2-100纳米范围内的厚度。在一个特定实施例中，该适应缓冲层大约为5-15纳米的厚度。在形成适应缓冲层过程中，沿着集成电路102的最上硅表面形成无定形中间层122。该无定形中间层122一般包括硅的氧化物，并且具有在大约1-5纳米范围内的厚度。在一个特定实施例中，该厚度大约为2纳米。在形成适应缓冲层124和无定形中间层之后，接着形成模板层126并且具有在大约1至10的单层材料范围内的厚度。在一个特定实施例中，该材料包括钛-砷、锶-氧-砷、或者其它类似的材料，如上文参照图1至5所述。
单晶化合物半导体层132然后外延生长在适应缓冲层124的单晶部分上，如图9中所示。生长在层面124的部分上的非单晶的层面132部分可以是多晶或无定形的。单晶化合物半导体层可以由多种方法所形成，并且一般包括例如砷化镓、铝镓砷化物、磷化铟、或者其它上文所述的化合物半导体材料。该层面的厚度在大约1-5000纳米的范围内，并且最好为100-500纳米。在该特定实施例中，在模板层中的每个元件还可以出现在适应缓冲层124、单晶化合物半导体材料132或这两者中。因此，在处理过程中，模板层126和它的两个相邻层面之间的分界线消失。因此，当采用透射电子显微(TEM)照像方法时，能够看到适应缓冲层124和单晶化合物半导体层132之间的界面。
在此时，化合物半导体层132和适应缓冲层124的部分被从覆盖如图10中所示的双极型部分1024和MOS部分1026的部分上除去。在除去该部分之后，然后在基片110上形成绝缘层142。绝缘层142可以包括多种材料，例如氧化物、氮化物、氧氮化物、低k电介质等等。如在此所用，低k是一种具有不大于约3.5的电介常数的材料。在已经淀积绝缘层142之后，然后进行抛光，除去覆盖单晶化合物半导体层132的绝缘层142的部分。
然后在单晶化合物半导体部分1022中形成晶体管144。然后在单晶化合物半导体层132上形成栅极148。然后在单晶化合物半导体层132中形成掺杂区146。在该实施例中，晶体管144是一种金属氧化物场效应晶体管(MESFET)。如果MESFET为n型MESFET，则掺杂区146和单晶化合物半导体层132被n型掺杂。如果要形成p型MESFET，则掺杂区146和单晶化合物半导体层132将具有相反掺杂类型。更浓的掺杂(N+)区146将能够进行与单晶化合物半导体层132的电阻接触。在此时，已经在集成电路中形成有源器件。特定实施例包括n型MESFET、垂直NPN双极型晶体管以及平面n沟道MOS晶体管。可以使用许多其它类型的晶体管，包括P沟道MOS晶体管、p型垂直双极型晶体管、p型MESFET、以及垂直和平面晶体管的组合。并且，其它电子元件，例如电阻器、电容器、二极管等等还可以形成在一个或多个部分1022、1024和1026中。
该处理继续进行以形成如图11中所示的基本完成的集成电路102。绝缘层152形成在基片110上。绝缘层152可以包括未在图11中示出的阻蚀或抛光防止区。然后在第一绝缘层152上形成第二绝缘层154。层面154、152、142、124和122的部分被除去，以确定设备互联的接触孔。互联通道形成在绝缘层154中，以提供接点之间的横向连接。如图11中所示，互联线1562把在部分1022中的n型MESFET的源或漏区连接到双极型部分1024中的NPN晶体管的深集电极区1108。NPN晶体管的发射极区1120连接到MOS部分1026中的n沟道MOS晶体管的一个掺杂区1116。其它掺杂区1116电连接到未示出的集成电路的其它部分。
钝化层156形成在互联线1562、1564和1566以及绝缘层154上。对所示的晶体管以及在集成电路102内的其它电子元件形成其它电连接，但是没有在图中示出。另外，其它绝缘层和互联线根据需要可以在集成电路102内的各个元件之间形成适当的互联。
如上一实施例所示，对于化合物半导体和IV族半导体材料的有源器件可以集成到单个集成电路中。由于在同一个集成电路中包含双极型晶体管和MOS晶体管存在一些困难，因此可以把双极型部分中的一些元件移到化合物半导体部分1022或MOS部分1024。更加具体来说，转到参照图6所述的实施例，可以把放大器10248和10242移到化合物半导体部分1022，以及把转换器10244和10246移到MOS部分1026。因此，可以取消专用于制作双极型晶体管的特殊制造部分的需要。因此，仅仅化合物半导体部分和MOS部分存在于集成电路中。
在另一个实施例中，可以如此形成一个集成电路，使得它包含在化合物半导体部分的激光器以及到相同集成电路的IV族半导体区的MOS晶体管的光互联(波导)。图12-18包括一个实施例的示意图。
图12包括包含单晶硅基片161的集成电路160的一部分的截面示图。类似于上文所述，无定形中间层162和适应缓冲层164已经形成在晶片161上。在该具体实施例中，将首先形成所需的层面，以形成激光器，然后形成MOS晶体管所需的层面。在图12中，下镜面层166包括化合物半导体材料的交替层。例如，在激光器中的第一、第三和第五薄膜可以包括例如砷化镓这样的材料，以及在下镜面层166中的第二、第四和第六薄膜包括铝镓砷化物，或者反之亦可。层面168包括将用于产生光子的活性层。按照类似于下镜面层166的方式形成上镜面层170，并且包括化合物半导体材料的交替薄膜。在一个特定实施例中，上镜面层170可以是p型掺杂化合物半导体材料，并且下镜面层166可以是n型掺杂化合物半导体材料。
类似于适应缓冲层164，另一个适应缓冲层172形成在上镜面层170上。在另一个实施例中，该适应缓冲层164和172可以包括不同的材料。但是，它们的功能基本上相同，都用于实现化合物半导体层和单晶IV族半导体层之间的跃迁。单晶IV族半导体层174形成在适应缓冲层172上。在一个特定实施例中，单晶IV族半导体层174包括锗、硅锗、硅锗碳化物等等。
在图13中，MOS部分被处理以形成在单晶IV族半导体层174中的电子元件。如图13中所示，场绝缘区域171由层面174的一部分所形成。栅绝缘层173形成在层面174之上，以及栅电极175形成在栅绝缘层173之间。如图所示，掺杂区177为用于晶体管的源区、漏区或者源/漏区。侧壁隔离179形成为与栅极175的垂直侧面相邻。其它元件可以制作在至少层面174的一部分中。这些其它元件包括其它晶体管(n沟道或p沟道)、电容器、晶体管、二极管等等。
单晶IV族半导体层外延生长在一个掺杂区177上。上部分184被P+掺杂，并且下部分182保持基本上不变(未掺杂)，如图13中所示。可以使用选择性外延生长工艺形成该层面。在一个实施例中，一个绝缘层(未示出)形成在晶体管181和场绝缘区171上。绝缘层被构图以确定暴露一个未掺杂区177的开口。至少在开始时，形成该选择性外延生长层，而不用掺杂剂。整个选择性外延生长层可以是固有的，或者可以在接近于选择性外延生长层形成结束时添加p型掺杂剂。如果该选择性外延生长层是固有的，可以通过注入或熔炉掺杂而形成掺杂步骤。无论如何形成P+的上部分184，接着除去该绝缘层，以形成图13中所示的所得结构。
接着执行下一组步骤，以确定如图14中所示的激光器180。场绝缘区171和适应缓冲层172被从集成电路的化合物半导体部分上除去。执行附加步骤，以确定激光器180的上镜面层170和活性层168。上镜面层170和活性层168的侧面基本上是相连的。
形成接点186和188用于分别连接到上镜面层170和下镜面层166，如图14中所示。接点186为环状，以使得光(光子)通过上镜面层170进入随后形成的光波导。
然后形成绝缘层190，并且进行构图以确定延伸到接触层186和一个掺杂区177的光开孔，如图15中所示。绝缘材料可以是任何不同的材料，包括氧化物、氮化物、低k电介质、或者它们之间的任何组合。在确定开孔192之后，然后在开孔中形成较高折射率的材料202，以在绝缘层190上淀积该层面，如图16中所示。对于该较高折射率材料202，“较高”与绝缘层190的材料相关(即，材料202与绝缘层190相比具有较高的折射率)。可选的，相对较薄的低折射率薄膜(未示出)可以在形成较高折射率材料202之前形成。然后在高折射率材料202上形成硬掩膜层204。硬掩膜层204和高折射率层202的部分被从覆盖开孔的部分到接近于图16的侧面的区域上除去。
如图17中所示，完成作为光互连的光波导的形成。执行淀积处理(可以是淀积-蚀刻处理)以有效地产生侧壁部分212。在该实施例中，该侧壁部分212由与材料202相同的材料所制成。然后除去硬掩膜层204，并且在绝缘层190的暴露部分和较高折射率材料212和202上形成低折射率层214(相对于材料202和层面212的折射率较低)。在图17中的虚线表示高折射率材料202和212之间的边界。该标记用于表示它们两者由相同的材料所形成，但是形成时间不同。
处理继续进行以形成如图18中所示的基本完成的集成电路。然后在激光器180和MOSFET晶体管181上形成钝化层220。尽管未示出，但是可以对该集成电路中的元件形成其它电或光连接，但是没有在图18中示出。这些连接可以包括其它光波导或者可以包括金属连接。
在其它实施例中，可以形成其它类似的激光器。例如，另一种类似的激光器可以水平地发光，而不是垂直发光。如果水平发光，则该MOSFET晶体管可以形成在基片161中，并且将重新构造该光波导，从而激光被适当地耦合(光连接)到晶体管。在一个特定实施例中，光波导可以包括至少一部分适应缓冲层。也可以有其它结构。
显然，这些具有化合物半导体部分和IV族半导体部分的集成电路的实施例是本发明的示例实施例，而不是对本发明的限制。存在有本发明的其它各种组合和其它实施例。例如，化合物半导体部分可以包括发光二极管、光电检测器、二极管等等，以及IV族半导体可以包括数字逻辑电路、存储器阵列、以及可以形成在常规MOS集成电路中的最适合结构。通过使用本发明的实施例，现在更加容易地把在化合物半导体材料中工作良好的器件与在IV族半导体材料中工作良好的其它器件相整合。这使得器件体积缩小、制造成本减小、以及生产率和可靠性增加。
尽管未示出，单晶IV族晶片不但可以用于在晶片上形成化合物半导体电子元件。按照这种方式，该晶片基本上是在覆盖晶片的单晶化合物半导体层中制造化合物半导体电子元件过程中所使用的“处理”晶片。因此，电子元件可以形成在至少大约200毫米并且可以至少为大约300毫米直径的晶片上的III-V或II-VI半导体材料中。
通过使用这种类型的基片，通过把化合物半导体晶片置于相对坚固和容易制造的基底材料上，相对较便宜的“处理”晶片克服该化合物半导体晶片的易碎特性。因此，可以形成一种集成电路，即使是基片本身可以包括IV族半导体材料，也能够使得所有电子元件，特别是所有有源电子器件，形成在化合物半导体材料中。用于化合物半导体器件的制造成本将被降低，因为与相对较小和易碎的常规化合物半导体晶片相比，可以更加经济和更加容易地处理较大的晶片。
在上述说明书中，本发明已经参照特定的实施例进行描述。但是，本领域内的普通技术人员将认识到可以作出各种变型和改变而不脱离如下权利要求中所给出的本发明的范围。相应地，本说明书和附图被认为是说明性而非限制性的，所有这种变型包含在本发明的范围内。
上文已经参照具体实施例描述本发明的效果、其它优点和对问题的解决方案。但是，该效果、优点、问题的解决方案、以及可能产生任何效果、优点或解决方案的任何要素不被认为是任何或所有权利要求的关键、必要或本质的特征或要素。如在此所用，术语“包括”、“包含”或者任何其它等价表述的含义是非排它性的包含，例如一种包含一系列要素的处理、方法、物体或装置不但包含这些要素，而且还可以包含其它没有列出或者这种处理、方法、物体或装置所固有的构件。

Claims (20)

1.一种半导体结构，其中包括：
单晶硅基片；
覆盖该单晶硅基片的无定形氧化物材料；
覆盖该无定形氧化物材料的单晶钙钛矿氧化物材料；以及
覆盖该单晶钙钛矿氧化物材料的单晶化合物半导体材料。
2.根据权利要求1所述的半导体材料，其中该单晶硅基片定向在(100)方向上。
3.根据权利要求1所述的半导体材料，其中进一步包括形成在单晶钙钛矿氧化物材料与单晶化合物半导体材料之间的模板层。
4.根据权利要求1所述的半导体材料，其中进一步包括形成在单晶钙钛矿氧化物材料和单晶化合物半导体材料之间的单晶半导体材料的缓冲材料。
5.根据权利要求4所述的半导体材料，其中进一步包括形成在单晶钙钛矿氧化物材料和缓冲材料之间的模板层。
6.根据权利要求4所述的半导体材料，其中该缓冲材料选自：镓、GaAsxP1-x超晶格，其中x的范围是从0至1；InyGa1-yP超晶格，其中y的范围是从0至1；以及InGaAs超晶格。
7.根据权利要求1所述的半导体材料，其中该单晶钙钛矿氧化物材料选自：碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐、碱土金属钒酸盐、碱土金属锡基钙钛矿、铝酸镧、以及镧钪氧化物。
8.根据权利要求1所述的半导体材料，其中单晶钙钛矿氧化物材料包括SrzBa1-zTiO3，其中z的范围是从0至1。
9.根据权利要求1所述的半导体材料，其中单晶化合物半导体材料选自：III-V化合物、混合的III-V化合物、II-VI化合物、以及混合II-VI化合物。
10.根据权利要求1所述的半导体材料，其中单晶化合物半导体材料选自：GaAs、AlGaAs、InP、InGaAs、InGaP、ZnSe、AlInAs、CdS、CdHgTe和ZnSeS。
11.一种半导体结构，其中包括：
具有第一晶格常数的单晶基片；
覆盖该单晶硅基片的具有不同于第一晶格常数的第二晶格常数的单晶绝缘层；
在单晶基片与单晶绝缘层之间的无定形氧化层；以及
覆盖该单晶绝缘层的具有不同于第一晶格常数的第三晶格常数的单晶化合物半导体层；其中第二晶格常数选自如下情况之一种：
    与第三晶格常数相等；以及
    在第一与第三晶格常数之间。
12.根据权利要求11所述的半导体结构，其中该单晶基片定向在(100)方向上。
13.根据权利要求11所述的半导体结构，其中该无定形氧化物层所具有的厚度足以释放在单晶绝缘层中的应力。
14.根据权利要求11所述的半导体结构，其中进一步包括形成在单晶绝缘层与单晶化合物半导体材料之间的模板层。
15.根据权利要求11所述的半导体结构，其中进一步包括形成在单晶绝缘层和单晶化合物半导体材料之间的缓冲层。
16.根据权利要求11所述的半导体结构，其中该单晶结构的特征是具有第一晶体方向，以及单晶绝缘层的特征是具有第二晶体方向，其中第二晶体方向相对于第一晶体方向旋转。
17.根据权利要求11所述的半导体结构，其中单晶基片包括硅。
18.根据权利要求11所述的半导体结构，其中单晶基片包括含硅的一种材料，单晶绝缘层包括碱土金属钛化物，以及单晶化合物半导体材料包括选自：GaAs、AlGaAs、ZnSe和ZnSeS的材料。
19.根据权利要求18所述的半导体结构，其中单晶绝缘层包括SrzBa1-zTiO3，其中z的范围是从0至1。
20.根据权利要求11所述的半导体结构，其中该单晶绝缘体包括选自碱土金属锆酸盐和碱土金属铪酸盐的氧化物，以及单晶化合物半导体层包括选自InP和InGaP的材料。
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