CN1324667C - 扩散式晶圆型态封装的结构与其形成方法 - Google Patents

扩散式晶圆型态封装的结构与其形成方法 Download PDF

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CN1324667C
CN1324667C CNB2004100432707A CN200410043270A CN1324667C CN 1324667 C CN1324667 C CN 1324667C CN B2004100432707 A CNB2004100432707 A CN B2004100432707A CN 200410043270 A CN200410043270 A CN 200410043270A CN 1324667 C CN1324667 C CN 1324667C
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layer
crystal grain
lead
mentioned
opening
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CN1624888A (zh
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杨文焜
杨文彬
陈世立
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Yupei Science & Technology Co Ltd
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Abstract

一种扩散式晶圆型态封装的结构与其形成方法，拾取与置放标准晶粒于一新的基底上以得到一比传统的晶圆上晶粒之间的距离更适当与更宽广的距离。由扩散式型态封装使得上述封装结构具有一比上述晶粒大小还大的球阵列。此外，上述晶粒可以与被动元件或其它具有并列结构或堆叠结构的晶粒一起封装。

Description

扩散式晶圆型态封装的结构与其形成方法
技术领域
本发明与一种半导体封装有关，特别是一种扩散式(fan out type)晶圆型态封装(wafer level package：WLP)。
背景技术
半导体技术已经发展的相当迅速，特别地是半导体晶粒(dies)有朝向小型化的趋势。然而，对于半导体晶粒(dies)功能的需求相对的具有多样化趋势。也就是说，上述半导体晶粒(dies)在一个很小的区域中必须具有更多的输入/输出垫(I/O pads)，因而使得引线(pins)的密度也快速提高了。这会导致上述半导体晶粒(dies)的封装变的越来越困难，并且良率也因此降低了。
上述封装结构的主要目的在于保护上述晶粒免于受到外在的损害。再者，由于上述晶粒所产生的热必须有效率地通过上述封装结构来扩散以确保上述晶粒的运作。
早期的导线架封装技术已经不适合引线(pins)密度过高的更进步的半导体晶粒。因此，一新的球阵列(Ball Grid Array：BGA)封装技术已经被发展出来，其可以满足上述更进步的半导体晶粒的封装需求。上述球阵列封装具有一个好处，也就是它的球形引线(pins)具有比上述导线架封装来得小的间距(pitch)，并且上述引线(pins)不容易损害与变形。此外，较短的讯号传递距离可以有益于提升操作频率以符合更快效率的需求。例如：由Mahulikar等人所提出的美国第5,629,835号专利，其揭露了一球阵列(BGA)封装；美国第5,239,198号专利揭露了另一个封装，其具有一导电图案形成于其上的FR4底材附著于一印刷电路板(PCB)上；由本发明人所提出的台湾第177,766号专利，其揭露了一扩散式(fan out type)晶圆型态封装(WLP)。
大部分的封装技术都是先将一晶圆上的晶粒分离成为个别的晶粒，然后再在封装与测试上述个别的晶粒。另外一种称为晶圆型态封装(waferlevel package：WLP)的封装技术可以在分离个别的晶粒之前就封装上述晶圆上的晶粒。上述晶圆型态封装(wafer level package：WLP)具有一些好处，例如：一个较短的生产周期(cycle time)、较低的价格以及不需要填充物(under-fill)或铸模(molding)。由Adams等人所提出的美国第5,323,051号专利″半导体晶圆型态封装(WLP)″揭露了一晶圆型态封装(WLP)的技术。上面技术描述如下。如图1所示，一晶粒4形成于一半导体晶圆2的一表面上，并且一具有预定图案的玻璃墙熔块8以作为黏合剂的上盖晶圆(cap wafer)6置于上述半导体晶圆2上，使得上述玻璃墙熔块8可以完全包围著上述晶粒4。然后，研磨没有晶粒4的半导体晶圆2表面以降低上述半导体晶圆2的高度，这一个步骤通常称为″背磨″(″backgrinding″)。上述晶粒4密封在一由上述半导体晶圆2、上盖晶圆(cap wafer)6与玻璃墙熔块8所组合形成的预定大小的空腔内。一复数个金属图形10形成了复数个电极于上述半导体底材晶圆2上，其提供了上述晶粒4的电性耦合。一复数个金属线12黏合到一形成于上述金属图形10外部的复数个垫上，并且透过洞14延伸而耦接外面的电性晶粒(未图示)。
如上所述，上述晶粒的大小是非常小的，并且输入/输出垫(I/O pads)是形成于传统公知技术的晶粒表面上。因此，上述垫(pads)的数目是受到限制的，并且垫(pads)之间太短的间距会导致讯号耦合或讯号干扰的问题。上述焊锡也会因为上述垫(pads)之间太短的间距而容易形成一焊锡桥(solder bridge)。此外，上述晶粒的大小渐渐地变得越来越小，并且上述晶粒的集成电路封装无法通过一些封装技术(例如晶片大小封装)而具有标准的大小，并且测试设备、封装设备等等对于一些固定大小的晶粒或封装也不能持续被使用。
发明内容
本发明的目的在于提供扩散式晶圆型态封装的结构与其形成方法。
本发明的另一目的在于提供扩散式晶圆型态封装的结构以维持上述封装结构二个相邻之间的垫具有一适当之间距。
此外，本发明的再一目的在于提供扩散式晶圆型态封装的结构以避免讯号耦合与讯号干扰的情形。
再者，本发明的目的在于降低封装结构的价格。
另外，本发明的又一目的在于提高封装结构的良率。
本发明的另一目的在于提供具有可调整大小的封装结构，其利用测试设备、封装设备等等来达到固定大小的晶粒或封装体。
如上所述，本发明的再一目的在于提供一种扩散式晶圆型态封装的方法。首先，一复数个晶粒附著到一绝缘基底上。一第一材料层形成于上述绝缘基底上，其中上述第一材料层填满于上述绝缘基底上的复数个晶粒之间，并且上述第一材料层与复数个晶粒的表面在相同的高度。然后，烘烤上述第一材料层。一第二材料层形成于上述第一材料层与复数个晶粒上。蚀刻上述复数个晶粒垫上的第二材料层的一部分区域，以形成第一开口。之后，烘烤上述第二材料层。接触导电层形成于上述第一开口上以分别与上述垫作电性耦合。一光阻层形成于上述第二材料层与第一接触导电层上。去除上述第一光阻层的一部分区域以形成一扇出图案并且暴露上述第一接触导电层。然后，导线形成于上述扇出图案上，并且上述导线分别与上述接触导电层耦合。去除剩余的上述第一光阻层。之后，一绝缘层形成于上述导线与第二材料层上。去除上述导线上的绝缘层的一部分区域以形成第二开口。烘烤上述绝缘层。最后，锻烧焊接球于上述第二开口上，并且切割上述基底以绝缘上述复数个晶粒。
本发明也提供一种扩散式型态封装的结构。上述封装结构包括：一绝缘基底、一晶粒、第一介电层、第二介电层、接触导电层、导线、绝缘层与焊接球。上述晶粒附著到上述绝缘基底上。上述第一介电层形成于上述绝缘基底上，其在上述绝缘基底上的晶粒外填满上述第一介电层，其中上述第一介电层与晶粒的表面在相同的高度。上述第二介电层形成于第一介电层与晶粒上，并且上述第二介电层具有第一开口形成于上述晶粒垫上。上述接触导电层形成于上述第一开口上的以分别与上述垫作电性耦合。上述导线形成于上述第二介电层与相对应的接触导电层上，并且上述导线从上述相对应的接触导电层往外延伸到相对应的第一端点，其中上述相对应的端点是在上述第二介电层的表面内。上述绝缘层形成于上述导线与第二介电层上的第一，并且上述绝缘层具有第二开口形成于上述导线上。锻烧的焊接球形成于上述第二开口上，其分别与上述导线耦合。
附图说明
图1为传统技术的一半导体晶圆型态封装的示意图。
图2A至图2C为利用拿与取的方式以重置标准晶粒于一新基底的示意图。
图3为形成第一材料层于基底上的示意图。
图4为形成第二材料层于第一材料层上的示意图。
图5为蚀刻晶粒垫上的第二材料层的一部分区域以形成第一开口的示意图。
图6为形成接触导电层于第一开口上的示意图。
图7为由一光阻层以形成导线于扇出图案上的纵向示意图。
图8为由一光阻层沿著图7的a-a’以形成导线于扇出图案上的横向示意图。
图9为形成绝缘层于上述导线与第二材料层上的示意图。
图10为根据本发明的一封装结构的示意图。
图11为根据本发明的一具有一晶粒与一被动元件的封装结构示意图。
图12为根据本发明的一具有二个晶粒的封装结构示意图。
图13为根据本发明的一具有二个晶粒的封装堆叠结构示意图。
具体实施方式
本发明的一些实施例将于目前详细地描述。然而，除了那些明确地描述之外，本发明也可以在一宽广的范围的其它实施例中被实施，并且本发明的范围也不限制于所描述的专利范围。
然而，不同构成要素的元件并不依实际的尺寸来显示。一些相关元件的大小是扩大的，并且无意义的部分没有画出来，这样比较容易提供本发明一更清楚的描述与理解。
本发明的本质在于拾取与置放标准晶粒于一新的基底上以得到一比传统的晶圆上晶粒之间的距离更适当与更宽广的距离。因此，上述封装结构具有一比上述晶粒大小还大的球阵列以避免具有太接近的球间距的问题。此外，上述晶粒可以与被动元件(例如：电容)或其它具有并列结构或堆叠结构的晶粒一起封装。本发明的详细方法将描述如下。
一具有晶粒完成制造硅晶圆置放于一底盘上，然后由背磨(backlapping)上述完成制造硅晶圆可以得到一范围为50～300微米(micron)的上述完成制造的硅晶圆厚度。上述完成制造的硅晶圆厚度可以很容易地切割上述硅晶圆上的晶粒以成为个别的晶粒。如果不经过背磨(back lapping)而上述完成制造硅晶圆不会很难切割的话，上述背磨(back lapping)步骤是可以被省略的。于切割前，一介电层是选择性地形成于上述完成制造硅晶圆上以保护晶粒免于损害。
上述个别晶粒接著经过测试以从其中选择标准的良好晶粒110。然后，拿取上述标准良好的晶粒110并重新置放在一个新基底100上，使得二个相邻的晶粒之间具有一个更宽广的距离，并且利用一具有良好热传导性的UV烘烤型态材料与/或热烘烤型态附著材料(未图示)附著上述晶粒110到上述基底100上，如图2A所示。上述附著材料是利用涂布方式形成在上述基底100上，并且上述附著材料的厚度最好是在20～60微米(micron)之间。当上述晶粒110置放于上述附著材料时，上述附著材料由UV光或热能来烘烤。上述置于基底100上的二个相邻晶粒之间的距离被安排而具有足够宽广的空间以形成以下步骤的扇出(fan out)球阵列。因此，本发明可以维持一个理想的球间距以避免讯号耦合与讯号干扰的问题，并且可以增加输入/输出(I/O)埠(球)的数目，甚至晶粒的大小也变的更小了。上述晶粒110具有输入/输出(I/O)垫116形成于上表面(如图4所示)。被动元件114或晶粒112也置放于上述基底100相邻位置上以得到一滤波或其它功能，如图2B与图2C所示。上述基底100材质可以是玻璃、硅、陶磁或晶体材料等等，并且其具有圆形或矩形形状。在本发明中，上述封装在一起的晶粒与被动元件的数目是不受限制的。由本发明，超过三个晶粒与被动元件也是可以被封装在相同封装结构中的。本发明的附著材料最好是良好的热传导材料，这样才可以使得上述起因于晶粒110与基底100之间温度差异所产生的问题(例如应力)被避免。
以下所对应的图与其图示是通过一个单一的晶粒来完成的，其为了简单化并提供一个对本发明较清楚的描述与理解。
第一材料层120形成而填满于上述相邻的晶粒110之间，并且上述第一材料层120与晶粒110表面在相同的高度。上述第一材料层120的材料可以是UV烘烤型态材料或热烘烤型态材料。然后，由UV或热能烘烤上述第一材料层120。上述第一材料层120可以由一网印的方法或一微影的方法来形成。上述第一材料层120可以用来作为一缓冲层以降低由于温度等所产生的应力。上述第一材料层120可以是一UV与/或热烘烤材料，例如：硅胶、环氧化物层、树脂、BCB等等。上述所提的包括基底100、晶粒110与第一材料层120的结构102看起来像一个晶圆具有晶粒110形成于其上。
如图4所示，一第二材料层122涂布形成于上述结构102上。上述第二材料层122的材料可以是UV烘烤材料或热烘烤材料，例如：BCB、环氧化物层、SINR3170(由Shin-Etsu化学有限公司所制造)等等。然后，利用一光罩来去除上述晶粒110的垫116上的第二材料层122的部分区域，以形成第一开口124于上述垫116上，之后，由UV或热能来烘烤上述第二材料层122。接著，选择性地利用电浆蚀刻(RIE)来清除上述垫116的表面以确保没有残留的材料留在上述垫116上。
接触导电层126形成于上述垫116上，如图6所示。上述接触导电层126的较佳材料是钛(Ti)、铜(Cu)或其组合。上述接触导电层126可以由一物理方法、化学方法或其组合的形成方式来形成，上述形成方法例如：化学气相沉积、物理气相沉积、溅镀与蒸镀。一光阻层128形成于上述第二材料层122与接触导电层126上，然后，由利用一光罩的曝光显影以形成上述光阻层128的扇出图案。上述扇出图案具有复数个扇出开口，该开口从上述垫116到上述第二材料层122的一表面内的端点。也就是说，二个相邻的扇出开口端点的间距可以比二个相邻的垫116的间距宽广。之后，由蒸镀方法，导线130形成于上述接触导电层126上，如图7(垂直图示)与图8所示(横向图示，沿著图7的a-a′方向)。上述导线130的材料较佳的是镍(Ni)、铜(Cu)、金(Au)或其组合。
请参考图9，蚀刻上述光阻层128与接触导电层126，然后，一绝缘层132形成于上述导线130与第二材料层122上，并且由一光罩使得第二开口134形成于上述导线130上。接著，烘烤上述绝缘层132。上述绝缘层132可以由旋转涂布或网印的方式来形成。上述第二开口134的位置可以形成上述晶粒110或第一材料层120上，较佳地是分别地形成于上述导线130的端点附近，所以相邻的二个第二开口134之间有一适宜距离可以形成锡球136于第二开口134上，这样就没有讯号耦合与讯号干扰的问题。
请参考图10，一环氧化物层140形成于上述基底100的背表面上，也就是没有晶粒110形成于其上的基底100的表面。然后，由一光罩使得一上标形成于上述环氧化物层140上，并且烘烤上述环氧化物层140。或者是利用印刷模板油印，热能/UV烘烤以形成一上标。上述上标是用来确认元件的名称。上述形成环氧化物层140的步骤也可以被省略。接著，上述锡球136置于上述第二开口134上，并且由一红外线回流(IR reflow)的方法将锡球136与上述导线130的表面连接在一起。
最后，前面所述的封装基底100沿著切割线138进行切割以隔绝个别的封装集成电路。如上所述，上述封装集成电路可以包括被动元件142与晶粒110，如图11所示。上述封装集成电路也可以是一并列结构的多晶粒，如图12所示。
本发明的封装方法甚至可以应用以形成具有堆叠结构的多晶粒。请参考图13，在形成上述绝缘层132或第二开口134的步骤后，于晶粒110的垂直方向将晶粒110置于上述绝缘层132上。然后，第三材料层120a、第四材料层122a与第二接触导电层126a也依序形成。蚀刻第三材料层120a、第四材料层122a与绝缘层132，以形成第三开口。之后，导电材料148置于上述第三开口内，并且上述导电材料148与上述导线130耦合。上述导电材料148可以是一焊锡。接著，类似上述图7到图10的图示，一第二导线130a、一第二绝缘层132a与锡球136依序形成。类似地，上述第三材料层120a与第四材料层122a的材料可以是UV烘烤型态或热烘烤型态的材料；上述第二接触导电层126a较佳的材料是钛(Ti)、铜(Cu)或其组合；而上述第二导线130a较佳的材料是铜(Cu)、镍(Ni)、金(Au)或其组合。虽然图13仅仅显示了一具有二个晶粒的封装堆叠结构，很明显地一个比二个晶粒还多的堆叠封装结构也可以由上面所描述的方式得到。
由此，根据本发明，上述封装结构可以维持上述封装结构的二个相邻之间的锡球具有一适当间距。因此，本发明可以避免讯号耦合与讯号干扰的情形。再者，本发明也利用了一个玻璃底材提供给LCD，并且上述玻璃底材的大小是很大的，所以本发明可以降低上述封装结构的价格，并且提高上述封装结构的良率。此外，本发明的封装大小可以很容易地调整以适合测试设备、封装设备等等。
本发明以较佳实施例说明如上，然其并非用以限定本发明所主张的专利权利范围。其专利保护范围当视申请的专利范围及其等同领域而定。凡熟悉此领域的技术人员，在不脱离本专利精神或范围内，所作的更动或润饰，均属于本发明所揭示精神下所完成的等效改变或设计，且应包含在申请的专利范围内。

Claims (7)

1.一种扩散式晶圆型态封装的形成方法，其特征在于包括：
附着一复数个第一晶粒到一绝缘基底；
形成一第一材料层于该绝缘基底上，其是在该绝缘基底上的该复数个第一晶粒之间填满该第一材料层；
形成一第二材料层于该第一材料层与该复数个第一晶粒上；
蚀刻该复数个第一晶粒的第一垫上的该第二材料层的一部分区域，以形成第一开口；
形成第一接触导电层于该第一开口上以分别与该第一垫作电性耦合；
形成一第一光阻层于该第二材料层与该第一接触导电层上；
去除该第一光阻层的一部分区域以形成一第一扇出图案并且暴露该第一接触导电层；
形成第一导线于该第一扇出图案上，并且该第一导线分别与该第一接触导电层耦合；
去除剩余的该第一光阻层；
形成一第一绝缘层于该第一导线与该第二材料层上；
去除该第一导线上的该第一绝缘层的一部分区域以形成第二开口；
于该复数个第一晶粒的上方附着一复数个第二晶粒至该第一绝缘层上；
形成一第三材料层于该第一绝缘层上，其是在该第一绝缘层上的该复数个第二晶粒之间填满该第三材料层；
形成一第四材料层于该第三材料层与该复数个第二晶粒上；
蚀刻该复数个第二晶粒的第二垫上的该第四材料层的一部分区域，以形成第三开口；
形成第二接触导电层于该第三开口上以分别与该第二垫作电性耦合；
去除该第一导线上的该第四材料层、该第三材料层与该第二材料层的一部分区域以形成第四开口；
以导电材料填充该第四开口；
形成一第二光阻层于该第四材料层、该导电材料与该第二接触导电层上；
去除该第二光阻层的一部分区域以形成一第二扇出图案并且暴露该第二接触导电层；
形成第二导线于该第二扇出图案上，并且该第二导线分别与相对应的该第二接触导电层以及相对应的该导电材料耦合，使得该第一晶粒采用该导电材料耦合该第二晶粒；
去除剩余的该第二光阻层；
形成一第二绝缘层于该第二导线与该第四材料层上；
去除该第二导线上的该第二绝缘层的一部分区域以形成第五开口；以及
锻烧焊接球于该第五开口上以耦合该第二导线。
2.如权利要求1所述的扩散式晶圆型态封装的形成方法，其特征在于，所述该第一材料层与该第二材料层包括UV烘烤型态材料、热烘烤型态材料与其组合；其中该第一接触导电层包括钛、铜与其组合；其中该第一导线层包括镍、铜、金与其组合；其中该绝缘层包括环氧化物层、树脂与其组合；其中该绝缘基底的材质是玻璃、硅、陶瓷或晶体材料。
3.如权利要求1所述的扩散式晶圆型态封装的形成方法，其特征在于，所述该第三材料层与该第四材料层包括UV烘烤型态材料、热烘烤型态材料与其组合；其中该第二接触导电层包括钛、铜与其组合；其中该第二导线包括镍、铜、金与其组合。
4.如权利要求1所述的扩散式晶圆型态封装的形成方法，其特征在于，更包括一切割该基底以隔绝具有该复数个第一晶粒与该复数个第二晶粒的封装晶粒的步骤。
5.一种扩散式型态封装的结构，其特征在于包括：
一绝缘基底；
一第一晶粒，附着到该绝缘基底上；
一第一介电层，形成于该绝缘基底上，其是在该绝缘基底上的该第一晶粒的外填满该第一介电层；
一第二介电层，形成于该第一介电层与该第一晶粒上，并且该第二介电层具有第一开口形成于该第一晶粒的第一垫上；
一第一接触导电层，形成于该第一开口上以分别与该第一垫作电性耦合；
一第一导线，形成于该第二介电层与该相对应的第一接触导电层上；
一第一绝缘层，形成于该第一导线与该第二介电层上，并且该第一绝缘层具有第二开口形成于该第一导线上；
一第二晶粒，附着于该第一晶粒上方的该绝缘基底上；
一第三介电层，形成于该绝缘基底的上与该第二晶粒之间；
一第四介电层，形成于该第三介电层与该第二晶粒上，并且该第四介电层具有第三开口形成于该第二晶粒的第二垫上；
一第二接触导电层，形成于该第三开口上以分别与该第二垫作电性耦合；
其中该第一导线上的该第四材料层、该第三材料层与该第二材料层中具有第四开口；
一导电材料，填充该第四开口；
一第二导线，形成于该导电材料与该第二接触导电层上，其中该第一晶粒采用该导电材料耦合该第二晶粒；
一第二绝缘层，形成于该第二导线与该第四材料层上，其中该第二绝缘层具有第五开口形成于其中；以及
焊接球，填入该第五开口中并耦合该第二导线。
6.如权利要求5所述的扩散式型态封装的结构，其特征在于，所述该第一介电层与该第二介电层的材料包括UV烘烤型态材料、热烘烤型态材料与其组合；其中该第一接触导电层包括钛、铜与其组合；其中该第一导线层包括镍、铜、金与其组合；其中该绝缘基底的材质是玻璃、硅、陶瓷或晶体材料；其中该第一绝缘层包括环氧化物层、树脂与其组合。
7.如权利要求5所述的扩散式型态封装的结构，其特征在于，所述该第三介电层与该第四介电层包括UV烘烤型态材料、热烘烤型态材料与其组合；其中该第二接触导电层包括钛、铜与其组合；其中该第二导线包括镍、铜、金与其组合。
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US20080105967A1 (en) 2008-05-08
DE102004033057A1 (de) 2005-06-30
TW200520190A (en) 2005-06-16
US7667318B2 (en) 2010-02-23
CN1624888A (zh) 2005-06-08
US20070059866A1 (en) 2007-03-15
US7262081B2 (en) 2007-08-28
US20050124093A1 (en) 2005-06-09
US7196408B2 (en) 2007-03-27
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US7459781B2 (en) 2008-12-02
US20050236696A1 (en) 2005-10-27
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US7557437B2 (en) 2009-07-07
US20060091514A1 (en) 2006-05-04

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