CN1321462C - High performance vertical PNP transistor and its manufacturing method - Google Patents
High performance vertical PNP transistor and its manufacturing method Download PDFInfo
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- CN1321462C CN1321462C CNB2003101163262A CN200310116326A CN1321462C CN 1321462 C CN1321462 C CN 1321462C CN B2003101163262 A CNB2003101163262 A CN B2003101163262A CN 200310116326 A CN200310116326 A CN 200310116326A CN 1321462 C CN1321462 C CN 1321462C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions
Abstract
The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.
Description
Technical field
The present invention relates to a kind of high-performance PNP transistor, and the method that forms vertical PNP and NPN transistor.
Background technology
The use to mobile communication of sustainable growth has promoted the progress of radio frequency (RF) communication.Particularly, the market demands of expansion reduce low in energy consumption and improve performance.A possible solution that has formed multiple application is bipolar CMOS (BiCMOS) technology.For example, see " Process HJ:A 30GHz NPN and 20GHz PNP Complementary BipolarProcess For High Linearity RF Circuits, " BCTM of people such as Wilson, 1998, the 164 pages; " Self-Aligned Complementary Bipolar Technology for Low-PowerDissipation and Ultra-High Speed LSI ' s, " IEEE TED of people such as Onai, 43:3,1995, the 413 pages; " A Complementary Bipolar Technology for Low Cost and HighPerformance Mixed Analog/Digital Applications, " BCTM of people such as Miwa, 1996, the 185 pages; And, " A 50GHz 0.25 μ m...BiCMOS Technology for Low-PowerWireless-Communication VLSI ' s " BCTM of people such as Chyan, 1998, the 128 pages.
Yet, along with using this technology more and more, such problem has appearred, promptly only can obtain high performance vertical NPN transistor at present.For the lateral PNP transistor of current low performance only can obtain to be lower than 1GHz by threshold value (fT).
For these reasons, need high-performance PNP transistor in the art, and preparation all have high performance NPN and the transistorized method of PNP.
Summary of the invention
The present invention includes a kind of be used to make high performance vertical NPN and the transistorized method of PNP, and resulting structures.The high performance vertical PNP transistor of gained comprises emitter region, and emitter region comprises silicon and germanium, and the base stage of its PNP emitter and NPN transistor is shared one deck silicon single-layer (a single layerof silicon).This method has been added two extra masks to traditional manufacturing process that is used for CMOS and bipolar device, has therefore realized the minimum of whole process flow additional.The structure of gained has obviously strengthened the PNP device performance.
According to the present invention, a kind of vertical PNP and NPN transistor are provided, comprising: the emitter region of vertical pnp transistor comprises silicon and germanium; The extrinsic base region of vertical NPN transistor and the intrinsic base region of vertical NPN transistor, the emitter region of they and vertical pnp transistor is arranged in one deck; Wherein, the silicon layer of the emitter region of vertical pnp transistor is a polysilicon, and the part of the extrinsic base region of vertical NPN transistor is a monocrystalline silicon, and the intrinsic base region of vertical NPN transistor is a monocrystalline silicon.
According to the present invention, a kind of transistorized method of PNP that forms when forming complementary mos device and NPN transistor is provided, it has adopted at least two masks except that the masks that is used to form complementary metal oxide semiconductors (CMOS) and NPN transistor, this method comprises: first masks, it limits first opening, is used for the injection of transistorized intrinsic base stage of PNP and collector electrode by first opening; And second masks, it limits the transistorized emitter of PNP, and wherein this method also comprises: deposit spathic silicon layer on second opening that second mask limits; And the epitaxial loayer of grown silicon and germanium, wherein silicon is grown to polysilicon on polysilicon layer, and is grown to monocrystalline silicon on NPN transistor.
Aforementioned and other feature of the present invention will become by following more concrete description to the embodiment of the invention and become apparent.
Description of drawings
Below, introduce embodiments of the invention with reference to the accompanying drawings in detail, wherein identical Reference numeral is represented components identical, and in the accompanying drawing:
Fig. 1 shows the first step of the method for making high-performance PNP device;
Fig. 2 and 3 shows the second and the 3rd step of this method respectively;
Fig. 4 shows optional the 4th step of this method;
Fig. 5 to 15 shows the 5th to the 15 step of this method respectively; And
Figure 16 shows the 16 step of this method and the high-performance NPN and the PNP transistor of gained.
Embodiment
The present invention includes the structure of making high performance vertical NPN and transistorized method of PNP and gained.This method has produced the high performance vertical PNP transistor as the part of traditional SiGe BiCMOS manufacturing technology.The high performance vertical PNP transistor of gained comprises the emitter region that contains silicon and germanium, and the base stage of its emitter and NPN transistor is shared one deck silicon single-layer.This structure is to use the result of SiGe low-temperature epitaxy layer, SiGe low-temperature epitaxy floor form polysilicon in the PNP district and in NPN district formation monocrystalline silicon and polysilicon, then form the single injection of the emitter of the extrinsic base of vertical NPN and vertical PNP.This method has increased by two extra masks to the traditional Si Ge manufacturing process that is used for CMOS and bipolar device, has realized the minimum of whole process flow additional thus.
With reference to accompanying drawing, Fig. 1 to 16 shows manufacturing technology steps.In institute's drawings attached, the NPN district 2 that wherein will set up vertical NPN transistor is shown in the left side, and the PNP district 4 that wherein will set up vertical pnp transistor is shown in the right side.It should be understood that for simplicity and clear for the purpose of, ignored some manufacturing steps according to traditional Si Ge technology.It should be understood that in addition for the sake of clarity, show the manufacturing step of some traditional Si Ge technology, but these steps not to constitute necessary part of the present invention.
In the first step, as shown in Figure 1, provide first masks, wherein for example go up painting photoresist 10 by being spin-coated on silicon dioxide layer 22 (below be called " oxide ").Any known or photo anti-corrosion agent material that develops recently of photoresist 10 and any other photoresist used herein.Press known way (for example, exposure and development) and in photoresist 10, be formed for injecting 15 opening.If device and substrate 12 are kept apart in expectation, and/or do not provide the existing technology that realizes identical purpose, first injection can comprise the n section bar material that is used to p type substrate 12 to set up n type isolated part 23.Therefore, this first injection is optional.Secondly, be provided for setting up the p section bar material of the collector electrode 16 of vertical pnp transistor.Be the n section bar material that is used to set up the intrinsic base stage 18 of vertical pnp transistor at last.Also can before above-mentioned injection, set up a plurality of other structures.Among these structures, as shown in Figure 1, comprise shallow-trench isolation (STI) 21, oxide layer 22 and NPN collector electrode 25.All the time the n section bar material that uses with this specification can be known or the material that is used for this type of doping of exploitation recently herein, for example combination of arsenic, phosphorus, antimony or these materials.Similarly, the p section bar material that uses all the time with this specification can be known or the material that is used for this type of doping of exploitation recently herein, for example combination of boron, indium or these materials.Then, press known way (for example, by etching) and remove photoresist 10.
Fig. 2 showed for second step, and wherein deposited silicon nitride layer 24 (below be called " nitride ") then is an oxide layer 26.Cover bi-pole area with resist 27, and etch layer 24 and 26, to expose non-bi-pole area.Then, remove resist 27, and layer 24 and 26 protection bi-pole area are avoided the CMOS processing.Yet it should be understood that the technology according to CMOS, these steps can be optional.Notice that ensuing accompanying drawing shows not etched seemingly layer 24 and 26.The known manufacturing step (not shown) that can operating part ground produces cmos device herein.CMOS handles and can keep or can not keep covering nitride film (blanket nitride film) (not shown).Yet CMOS handles and has removed oxide layer 26, and therefore need deposit another oxide layer 26 again protects the CMOS district during bipolar processing.
Fig. 3 showed for the 3rd step, wherein form second mask by painting photoresist on layer 24 and 26 28, and for example etch layer 22,24 and 26 forms openings 30 by exposing also via photoresist 28, thereby exposes the surface 31 of the oxide layer 22 (substrate 12) in the PNP district 4.Then, for example remove photoresist 28 by etching.
With reference to Fig. 4, it shows optional the 4th step.This optional the 4th step masks is included in painting photoresist 32 and exposure formation opening 34 on the position of the extrinsic base 36 that will produce PNP district 4.Then, thus the injection that can carry out n section bar material forms the extrinsic base 36 in PNP district 4.Then, remove photoresist 32.If do not carry out this step, as shown in figure 15, then can use the NFET source/drain to be infused in the n type of finishing the extrinsic base 36 that forms PNP district 4 when technology finishes and inject, this will introduce below.After this one select to have saved masks, but produced higher base resistance, and reduced the transistorized performance of PNP thus.For clarity sake, the not shown extrinsic base part 36 of Fig. 5 to 14.
Fig. 5 showed for the 5th step, and wherein the deposit spathic silicon layer 38, and it has been filled the opening in the PNP district 4 and has touched surface 31.Polysilicon layer 38 can be not less than 10nm and be not more than 100nm, and is generally about 45nm.
Then, as shown in Figure 6, by the deposition oxide (not shown), and nationality sheltered by coating/development photoresist (not shown), again in NPN district 2 etching polysilicon layer 38 to nitration case 24, thereby in NPN district 2, produce opening 40.(note: according to the processing of front, oxide can be optional.), carry out the injection of n type material herein, thus NPN collector electrode 50 (according to the processing of front NPN collector electrode, this injection can be optional) formed.Then, remove resist, and according to subsequent treatment, carry out etching, oxide layer 22 in NPN district 2 or substrate 12.
In the step below, as shown in Figure 7, the epitaxial loayer 42 of grown silicon-germanium on entire wafer (SiGe).Along with the growth of epitaxial loayer 42, SiGe contacts with silicon owing to it and be grown to single crystalline layer 46 in NPN district 2, but on polysilicon 38, promptly on the zone in the PNP district 4, grows into polycrystal layer 46.Follow the generation of deposition,, make the floor 42 of gained comprise the p type base stage 48 in NPN district 2 interpolation p section bar material.In some cases, epitaxial loayer 42 can comprise that also some are deposited near the carbon of p section bar material that is added into layer 42.Gained layer 42 comprise the Cmax of germanium be not less than total silicon and germanium composition (combined silicon and germanium composition) 10% and be not more than 30% zone of total silicon and germanium composition.
Fig. 8 to 16 shows the consecutive steps of last high-performance NPN of final acquisition and the transistorized known SiGe technology of PNP.These steps are described in No. the 5111271st, United States Patent (USP), and it is herein incorporated by reference.Should be realized that be applicable to different application in order to make integrated circuit, these steps can change slightly.Fig. 8 shows wherein that oxide layer 52 is grown on the entire wafer, then cvd nitride layer 54 and be the step of polysilicon layer 56 at last.
Fig. 9 shows following step, forms axle (mandrel) 58 thereby wherein deposit and etch away another floor nitration case (not shown) subsequently in NPN district 2.In addition, press traditional approach (for example, deposition and etching oxide) near axle 58 and form oxidation spaced walls 60.Then, inject p section bar material 61 (for example, boron) thus form the extrinsic base 62 in NPN district 2 and the emitter 64 in PNP district 4.P section bar material diffuses in the single crystalline layer 44 lentamente, but diffuses into polycrystal layer, for example polysilicon layer 38 and SiGe layer 46 apace.P type outdiffusion 65 forms by spreading rapidly in polysilicon.As a result, the emitter 64 in PNP district 4 and the extrinsic base 62 in NPN district 2 have been formed simultaneously.The structure of gained comprises monocrystalline silicon in the part of extrinsic base region 62 of polysilicon in the PNP emitter district 64 and NPN transistor and the monocrystalline silicon in the intrinsic base region 63.
As shown in figure 10, following step comprises from axle 58 and etches away spaced walls 60 (Fig. 9), and carries out heavy oxidation 68.Along with the generation of oxidation, polysilicon layer 56 (Fig. 9) is converted into oxide layer 70.Yet the part 71 of polysilicon layer 56 under nitride axle 58 is left polysilicon, therefore with the shape transferred thereon of axle 58 to polysilicon layer 56.The emitter in the NPN district 2 that the structure permission of gained will form and extrinsic base 62 autoregistrations in NPN district 2.
With reference to Figure 11, following step comprises the part under it that optionally etches away polysilicon segment 71, nitride axle 58 and oxide layer 70, nitration case 54 and oxide layer 52.
Following step as shown in figure 12, comprises deposit spathic silicon layer 72, and or between depositional stage or by injecting 74, with n section bar material it is mixed, thereby form the emitter 76 in NPN district 2.
As shown in figure 13, the cvd nitride layer 78.Cover NPN emitter 76 with the photoresist (not shown) then.Then, remove (for example by etching) each layer (be nitration case 78, polysilicon layer 72, oxide layer 50 and 70 and nitration case 54).Then, remove the resist (not shown).
Following step as shown in figure 14, comprises with the photoresist (not shown) and covers NPN district 2 and PNP emitter 64, and etches away SiGe polysilicon layer 46 and polysilicon layer 38.This etching defines the base stage of NPN transistor 100 and the emitter 64 of PNP transistor 102.Then, peel off the photoresist (not shown), and etching oxide layer 26.
With reference to Figure 15,, thereby then can use the CMOSNFET source/drain to handle the extrinsic base 36 that (not shown) forms PNP district 4 if omitted optional the 3rd mask shown in Figure 4.With this understanding, with etching nitration case 24 (if existence), form photoresist mask and inject n type material 80, thereby set up extrinsic base 36.Then, will peel off the photoresist (not shown).
At last, as shown in figure 16, see through the mask (not shown) and carry out the injection of p section bar material 82, to be used to form PFET source/drain (not shown).This injects and has also formed PNP collector electrode contact 84.
Continuation is referring to Figure 16, and the vertical transistor 100 and 102 of gained comprises the polysilicon emitter 64 of PNP transistor 102 and the polysilicon emitter 76 of NPN transistor 100.Vertical pnp transistor 102 comprises emitter region 64, and emitter region 64 comprises silicon and germanium.In addition, vertical NPN and PNP transistor 100 and 102 comprise silicon single-layer, and it has formed the emitter region 64 of PNP transistor 102, the extrinsic base 62 of NPN transistor 100 and the intrinsic base stage 63 of NPN transistor 100.The structure of gained provides the PNP transistor 102 of comparing the performance (cut-off frequency that can have fT＞1GHz) with obvious enhancing with current lateral PNP transistor.
As mentioned above, form the method for PNP transistor 102, except the masks that is used to form cmos device (not shown) and NPN transistor 102, use two additional masks, Fig. 1 and Fig. 3.Unshowned CMOS processing step can comprise the mask of the growth of the deposition of gate oxide growth, FET polysilicon and etching, spaced walls and/or deposition and etching, extension and annular (halo) mask and injection, source/drain and injection or the like.First masks of Fig. 1 defines opening 14, carries out PNP intrinsic base stage 18, PNP collector electrode 16 and PNP n type by opening 14 and isolates 23 (if the mask and the injection of front can be used for identical functions, the latter is optional) injection.Second masks of Fig. 3 defines opening 30, forms PNP emitter 64 by opening 30.
Though the present invention in conjunction with above-described specific embodiment introduction as above, obviously, various replacements, change and variation are fairly obvious to those skilled in the art.In addition, the embodiment that explain the present invention such as front is in order to illustrate, and and unrestricted.Various variations can be carried out under the condition that does not break away from the present invention such as essence that claim limited and scope.
Claims (11)
1. vertical PNP and NPN transistor comprise:
The emitter region of vertical pnp transistor comprises silicon and germanium;
The extrinsic base region of vertical NPN transistor and the intrinsic base region of vertical NPN transistor, the emitter region of they and vertical pnp transistor is arranged in one deck;
Wherein, the silicon layer of the emitter region of vertical pnp transistor is a polysilicon, and the part of the extrinsic base region of vertical NPN transistor is a monocrystalline silicon, and the intrinsic base region of vertical NPN transistor is a monocrystalline silicon.
2. vertical PNP as claimed in claim 1 and NPN transistor, wherein maximum germanium concentration formation is not less than 10% of silicon and germanium composition, and this germanium concentration formation is not more than 30% of silicon and germanium composition.
3. vertical PNP as claimed in claim 1 and NPN transistor, wherein emitter region also comprises carbon.
4. one kind forms the transistorized method of PNP when forming complementary mos device and NPN transistor, it has adopted at least two masks except that the masks that is used to form complementary metal oxide semiconductors (CMOS) and NPN transistor, and this method comprises:
First masks, it limits first opening, is used for the injection of transistorized intrinsic base stage of PNP and collector electrode by first opening; And
Second masks, it limits the transistorized emitter of PNP,
Wherein, this method also comprises:
Deposit spathic silicon layer on second opening that second mask limits; And
The epitaxial loayer of grown silicon and germanium,
Wherein, silicon is grown to polysilicon on polysilicon layer, and is grown to monocrystalline silicon on NPN transistor.
5. method as claimed in claim 4, thus comprise that also injecting the n type by first opening isolates the step that PNP transistor collector and substrate are separated.
6. method as claimed in claim 4 also comprises the 3rd masks, and it limits at least one opening, is used for the injection of the transistorized extrinsic base of PNP by this opening.
7. method as claimed in claim 4 also comprises by injecting the step that p section bar material forms the extrinsic base of transistorized emitter of PNP and NPN transistor simultaneously.
8. method as claimed in claim 7, wherein the transistorized emitter of PNP comprises silicon and germanium.
9. method as claimed in claim 4, wherein epitaxial loayer also comprises carbon.
10. method as claimed in claim 4 also is included in the step of adding p section bar material during the growth step.
11. method as claimed in claim 4, wherein polysilicon layer is not less than 10nm, and wherein polysilicon layer is not more than 100nm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/065837 | 2002-11-25 | ||
| US10/065,837 US6909164B2 (en) | 2002-11-25 | 2002-11-25 | High performance vertical PNP transistor and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1514494A CN1514494A (en) | 2004-07-21 |
| CN1321462C true CN1321462C (en) | 2007-06-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101163262A Expired - Lifetime CN1321462C (en) | 2002-11-25 | 2003-11-19 | High performance vertical PNP transistor and its manufacturing method |
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| Country | Link |
|---|---|
| US (2) | US6909164B2 (en) |
| KR (1) | KR100544548B1 (en) |
| CN (1) | CN1321462C (en) |
| TW (1) | TWI269432B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6933202B1 (en) | 2004-04-09 | 2005-08-23 | Newport Fab, Llc | Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure |
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2003
- 2003-10-24 KR KR1020030074524A patent/KR100544548B1/en not_active IP Right Cessation
- 2003-11-19 CN CNB2003101163262A patent/CN1321462C/en not_active Expired - Lifetime
- 2003-11-20 TW TW092132559A patent/TWI269432B/en not_active IP Right Cessation
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|---|---|
| US20040099895A1 (en) | 2004-05-27 |
| KR20040045291A (en) | 2004-06-01 |
| US7265010B2 (en) | 2007-09-04 |
| TWI269432B (en) | 2006-12-21 |
| US20040248352A1 (en) | 2004-12-09 |
| US6909164B2 (en) | 2005-06-21 |
| TW200423383A (en) | 2004-11-01 |
| KR100544548B1 (en) | 2006-01-24 |
| CN1514494A (en) | 2004-07-21 |
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