CN1320633C - Structure and producing method of back-fuse type memory assembly - Google Patents
Structure and producing method of back-fuse type memory assembly Download PDFInfo
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- CN1320633C CN1320633C CNB2004100594275A CN200410059427A CN1320633C CN 1320633 C CN1320633 C CN 1320633C CN B2004100594275 A CNB2004100594275 A CN B2004100594275A CN 200410059427 A CN200410059427 A CN 200410059427A CN 1320633 C CN1320633 C CN 1320633C
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Abstract
The present invention discloses a structure and a manufacturing method of a reverse fuse type memory assembly. The manufacturing method of a reverse fuse type memory assembly comprises the following steps: firstly, a substrate is provided and a metal layer is formed on the substrate; secondly, a silicon layer is formed on the metal layer, the partial silicon layer reacts with the metal layer to form a metal silicide, and the un-reacted silicon layer is used as a first type conducting layer; thirdly, a reverse fuse layer is formed on the first type conducting layer, the first type conducting layer, the metal silicide layer and the reverse fuse layer are patterned to form a character line, and a second type conducting layer is formed on the reverse fuse layer; finally, the second type conducting layer is patterned to form a bit line. The present invention can reduce the step of polysilicon deposition, simplify the manufacturing process of forming the metal silicide, shorten the time of a manufacturing process, lower manufacturing costs and reduce the total resistance of conducting layers.
Description
Technical field
The present invention relates to a kind of improvement of manufacture of semiconductor, particularly about a kind of structure and method of improving anti-fuse-type memory assembly polysilicon and metal silicide processing procedure.
Background technology
The memory assembly that anti-fuse-type memory assembly is a kind of three-dimensional (being memory assembly), its memory cell are provided in a side of the positive pole of diode and the antifuse layer between the negative pole to do control.When antifuse layer was intact, its anodal and negative pole opened circuit each other, but when antifuse layer is destroyed, its anodal and negative pole formation diode, and its line design is that the material of positive pole and negative pole is orthogonal.The anti-fuse-type memory assembly of three-dimensional structure and traditional two-dimensional structure memory compare, and the memory that the long-pending floor space of the silicon of its required use is more traditional is little, also therefore, can increase the positive degree of memory, reduces the cost of unit are.Anti-in addition fuse-type memory assembly can provide preferable protection owing to have the characteristic of a burning (OTP) on confidentiality.
See also Figure 1A to Fig. 1 D, be the generalized section of the metal silicide processing procedure of known anti-fuse-type memory assembly polysilicon.Shown in Figure 1A, the dielectric layer processing procedure was finished on the semiconductor-based end 100 between plain conductor and lead thereof, omitted for simple diagram, the polysilicon layer of deposition one doping P+ on dielectric layer between plain conductor and lead thereof is with as bottom polysilicon layer 110 herein.Deposit a undoped polysilicon or amorphous silicon layer as react polysilicon layer 111 in bottom polysilicon layer 110 on thereafter.Then, deposit a titanium coating 119 and follow-up titanium nitride layer 120 on undoped polysilicon or amorphous silicon layer 111.
Next, shown in Figure 1B, use a prompt tempering processing procedure, so that reaction polysilicon layer and titanium coating 119 and 120 reactions of part titanium nitride layer form a titanium-silicon compound layer 130.The titanium-silicon compound layer 130 of its formation has low electrical conductivity and good thermal stability, can reduce the resistance between lead.Afterwards, on titanium-silicon compound, deposit the polysilicon layer of one deck doping P+ as the first type conductive layer 135.
Follow-up, shown in Fig. 1 C, carry out a thermal oxidation processing procedure to form an antifuse layer 136 on the first type conductive layer 135.The antifuse layer 136 of its formation is the primary clustering as the anti-fuse-type memory cell of control.Thereafter, the antifuse layer 136 that forms before the definition, titanium-silicon compound layer 130, the first type conductive layer 135 and bottom polysilicon layer 110 are to form character line, it comprises little shadow, insert dielectric material and follow-up cmp processing procedure behind etching and the formation lead between lead, it is general known skill, does not encyclopaedize at this.At last, shown in Fig. 1 D, the polysilicon layer that deposits a doping N is as the second type conductive layer 140, and defines the second type conductive layer 140 to form bit line.
See also shown in Figure 3, it is the stereogram of the metal silicide processing procedure of known anti-fuse-type memory assembly polysilicon, bottom polysilicon layer 110 is formed at semiconductor-based the end 100, and bottom polysilicon layer 110, titanium-silicon compound layer 130, titanium nitride layer 120, the first type conductive layer 135 are arranged on it in regular turn.Bottom polysilicon layer 110, titanium-silicon compound layer 130 and the first type conductive layer 135 are as character line (WL).The second type conductive layer 140 is as accompanying an antifuse layer 136 in bit line (BL) and itself and the first type conductive layer 135.
This processing procedure needs polysilicon layer and follow-up undoped polysilicon or the amorphous silicon layer of deposition one P+ earlier when forming the titanium silicide.The titanium coating of heating deposition is so that titanium coating and the undoped polysilicon under it or amorphous silicon layer reaction form the titanium silicide layer.Again deposit the polysilicon layer of one deck doping P+ thereafter.Its step that forms the first type conductive layer is quite loaded down with trivial details, and the polysilicon deposition of multilayer must be constantly by the gross wafer take out by previous reactor and insert again in the reactor that reacts in advance, not only step is numerous and diverse, and need wait as long for and vacuumize, to reach the chamber pressure of standard, quite expend the processing procedure time.
Application No. has disclosed a kind of memory cell of low-leakage current for No. 09/560626, wherein between the diode of positive pole and negative pole, place an antifuse layer, when antifuse layer when being intact, its positive pole and negative pole open circuit each other, but when antifuse layer was destroyed, its positive pole and negative pole were connected at the antifuse layer of a zonule, also therefore formed diode, also because its very the fuse of zonule make its diode have very little scope zone, the also therefore relatively little leakage current of its tool.United States Patent (USP) discloses a kind of three-dimensional No. 6525953 in addition, programmable, nonvolatile memory cell, it is the column by a self-aligned, wherein comprises the positive pole and the negative pole assembly of diode, and between wherein antifuse layer, and column forms its memory cell according to this, its operation principles also is to be intact and whether to destroy according to antifuse layer, forms circuit, and the data of decision storage.
Therefore, for overcoming above-mentioned known method, promptly, produced the present invention in positive pole that forms diode and the shortcoming that the negative pole assembly all is to use the polysilicon of doping.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of structure and manufacture method of anti-fuse-type memory assembly of simplification, and it can reduce the deposition step of polysilicon, to simplify the processing procedure that forms metal silicide, reduction processing procedure time, and attenuating manufacturing cost.
Another technical problem that the present invention will solve provides a kind of structure and manufacture method of anti-fuse-type memory assembly, it is by reducing by a polysilicon layer, can reach the overall resistance matter that reduces polysilicon and silicide layer, and increase the drive current of anti-fuse-type memory assembly by this.
For solving the problems of the technologies described above, technical scheme of the present invention is: a kind of manufacture method of anti-fuse-type memory assembly comprises the following steps:
One substrate is provided;
Form a bonding coat on this substrate;
Form a metal level on this bonding coat;
Form a silicon layer on this metal level;
Make this metal level and this bonding coat of part and the reaction of this silicon layer of part with the silicon layer that forms a metal silicide layer and do not reacted as the first type conductive layer;
Form an antifuse layer on this first type conductive layer;
Graphical this first type conductive layer, metal silicide layer, antifuse layer are to form character line;
Form one second type conductive layer on this antifuse layer; And
Graphical this second type conductive layer is to form bit line.
The manufacture method of described anti-fuse-type memory assembly, this substrate are the semiconductor substrate.
The manufacture method of described anti-fuse-type memory assembly, this metal level are titanium, cobalt, or nickel is formed.
The manufacture method of described anti-fuse-type memory assembly, this bonding coat are the nitride of titanium, the nitride of cobalt or the nitride of nickel.
The manufacture method of described anti-fuse-type memory assembly, this silicon layer are that the polysilicon storehouse of a unadulterated polysilicon and one first type ion doping in regular turn constitutes.
The manufacture method of described anti-fuse-type memory assembly, the unadulterated polysilicon layer reaction that forms metal level and this silicon layer of this metal silicide layer forms.
The manufacture method of described anti-fuse-type memory assembly, this first type conductive layer are that the P type and the second type conductive layer are the N types.
The manufacture method of described anti-fuse-type memory assembly, this first type conductive layer are that the N type and the second type conductive layer are the P types.
The manufacture method of described anti-fuse-type memory assembly, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
The manufacture method of described anti-fuse-type memory assembly, the method that forms an antifuse layer is this first type conductive layer of heating.
The manufacture method of described anti-fuse-type memory assembly, this antifuse layer are silicon dioxide or silicon nitride.
A kind of structure of anti-fuse-type memory assembly, it comprises:
One metal silicide layer;
One first type conductive layer is on this metal silicide layer;
One antifuse layer is on this first type conductive layer; And
One second type conductive layer is on this antifuse layer.
The structure of described anti-fuse-type memory assembly, this first type conductive layer are that the P type and the second type conductive layer are the N types.
The structure of described anti-fuse-type memory assembly, this first type conductive layer are that the N type and the second type conductive layer are the P types.
The structure of described anti-fuse-type memory assembly, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
The structure of described anti-fuse-type memory assembly, this antifuse layer are silicon dioxide or silicon nitride.
A kind of structure of anti-fuse-type memory assembly, it comprises:
One first lead;
One bonding coat is positioned on this first lead;
One metal silicide layer is positioned on this bonding coat;
One first type conductive layer is positioned on this first lead;
One antifuse layer is positioned on this first type conductive layer; And
One second type conductive layer is positioned under one second lead, this first lead and second lead are orthogonal, and the antifuse layer in the middle of this first type conductive layer and this second type conductive layer is a square type zone, and only when this antifuse layer bursts apart the first type conductive layer and the second type conductive layer just can form diode.
The structure of described anti-fuse-type memory assembly, this first lead and second lead are constituted by tungsten, aluminium or copper.
The structure of described anti-fuse-type memory assembly, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
The structure of described anti-fuse-type memory assembly, this first type conductive layer and the second type conductive layer are P type or N type.
The structure of described anti-fuse-type memory assembly, kenel is different each other with the second type conductive layer for this first type conductive layer.
The structure of described anti-fuse-type memory assembly, this antifuse layer are silicon dioxide or silicon nitride.
The structure of described anti-fuse-type memory assembly, this bonding coat are the nitride of titanium, the nitride of cobalt or the nitride of nickel.
A kind of manufacture method of anti-fuse-type memory assembly comprises the following steps:
One substrate is provided;
Form a metal level on this substrate;
Form a silicon layer on this metal level;
Making this silicon layer reaction of this metal level and part is as the first type conductive layer with the silicon layer that forms a metal silicide layer and do not reacted;
Form an antifuse layer on this first type conductive layer; And
Graphical this first type conductive layer, metal silicide layer, antifuse layer are to form character line.
The manufacture method of described anti-fuse-type memory assembly, this substrate are the semiconductor substrate.
The manufacture method of described anti-fuse-type memory assembly, this metal level are titanium, cobalt, or nickel is formed.
The manufacture method of described anti-fuse-type memory assembly still comprises a bonding coat between this metal level and this substrate.
The manufacture method of described anti-fuse-type memory assembly, this bonding coat are the nitride of titanium, the nitride of cobalt or the nitride of nickel.
The manufacture method of described anti-fuse-type memory assembly, this silicon layer are that the polysilicon storehouse of a unadulterated polysilicon and one first type ion doping in regular turn constitutes.
The manufacture method of described anti-fuse-type memory assembly, the unadulterated polysilicon layer reaction that forms metal level and this silicon layer of this metal silicide layer forms.
The manufacture method of described anti-fuse-type memory assembly, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
The manufacture method of described anti-fuse-type memory assembly, the method that forms an antifuse layer is this first type conductive layer of heating.
The manufacture method of described anti-fuse-type memory assembly, this antifuse layer are silicon dioxide or silicon nitride.
The invention provides a kind of structure and manufacture method of anti-fuse-type memory assembly of simplification, comprise the following steps: at first, a substrate is provided and forms a metal level on this substrate.Thereafter, form a silicon layer on this metal level and make this metal level and the reaction of this silicon layer of part with the silicon layer that forms a metal silicide layer and do not reacted as the first type conductive layer.Next, form an antifuse layer on this first type conductive layer.Graphical this first type conductive layer, metal silicide layer, antifuse layer are to form character line and to form one second type conductive layer on antifuse layer, and the last graphical second type conductive layer is to form bit line.
The present invention proposes a kind of polysilicon and silicide structural of anti-fuse-type memory assembly again in addition, and it comprises: a metal silicide layer, one first type conductive layer on this metal silicide layer, an antifuse layer on this first type conductive layer and one second type conductive layer on this antifuse layer.
Characteristics of the present invention and advantage are: the present invention is in the processing procedure of anti-fuse memory assembly, in deposition one metal level on plain conductor, deposit a conversion zone in thereafter, and by heating processing, make upwards reaction formation one metal silicide of metal level, can reduce the polysilicon deposition step of known technology, to simplify the processing procedure that forms metal silicide, the reduction processing procedure time, and lower manufacturing cost.
The present invention so the overall resistance matter of its polysilicon and silicide layer is lower, can increase the drive current of anti-fuse-type memory assembly because it reduces by a polysilicon layer than known technology.
The present invention is formed metal silicide layer under polysilicon, only need increase the overall resistance matter that a processing procedure can reduce polysilicon and silicide layer, and increases the drive current of anti-fuse-type memory assembly by this.
Description of drawings
Figure 1A to Fig. 1 D is the generalized section of known anti-fuse-type memory assembly polysilicon and metal silicide processing procedure;
Fig. 2 A to Fig. 2 D is the anti-fuse-type memory assembly polysilicon and the metal silicide processing procedure generalized section of the embodiment of the invention;
Fig. 3 is the stereogram of the metal silicide processing procedure of known anti-fuse-type memory assembly polysilicon;
Fig. 4 is the stereogram of the metal silicide processing procedure of the anti-fuse-type memory assembly of the present invention polysilicon.
Symbol description:
Known technology:
100, the semiconductor-based end 110, bottom polysilicon layer 111, reaction polysilicon layer
119, titanium coating 120, titanium nitride layer 130, titanium-silicon compound layer
135, the first type conductive layer 136, antifuse layer 140, the second type conductive layer
The technology of the present invention:
200, semiconductor substrate 210, titanium nitride layer 212, titanium coating
220, reaction polysilicon layer 230, the first type conductive layer 240, titanium silicide layer
235, antifuse layer 250, the second type conductive layer
Embodiment
For technical problem of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
See also Fig. 2 A to Fig. 2 D, it is the processing procedure profile of the embodiment of the manufacture method of the anti-fuse-type memory assembly of the present invention's simplification.In the narration of present embodiment, substrate comprises established assembly on the semiconductor crystal wafer, for example gate etc.
At first, shown in Fig. 2 A, semiconductor substrate 200 is provided, and dielectric layer has been formed on the semiconductor substrate 200 between plain conductor and lead thereof, its plain conductor can be copper metal or tungsten metal, and dielectric layer can be unadulterated silex glass between its lead, and tetraethoxysilane is silicon dioxide or other dielectric material in silicon source.Thereafter, deposition titanium nitride layer 210 and follow-up titanium coating 212, but titanium nitride applied chemistry vapour deposition process (CVD) or the mode of physical vaporous deposition (PVD) forms, titanium is Applied Physics vapour deposition process (PVD) deposition.The thickness of titanium nitride is the 25-250 dust, and it is as titanium-silicon compound and its bonding coat of plain conductor down, and the thickness of titanium is the 200-800 dust, its as after form the source of titanium-silicon compound.
Thereafter, deposit a undoped polysilicon layer or amorphous silicon layer as reacting polysilicon layer 220 on titanium coating 212, it uses a chemical vapour deposition technique (CVD), in reaction temperature at 450 ℃-800 ℃, reaction pressure is in the condition deposit of 0.1Torr-10Torr, thickness of its reaction polysilicon layer 220 is the 200-1500 dust, is as reacting to form follow-up titanium-silicon compound layer with its titanium coating 212 and part titanium nitride layer 210 down.Next, the deposition first type conductive layer 230 on the reaction polysilicon layer, it can be the polysilicon layer of doping P+, also be that applied chemistry vapour deposition process (CVD) forms, but this polysilicon layer is as conduction and form diode action, need the lower resistivity of tool, so by mixing to reduce the resistivity of itself, the impurity that is mixed is boron or other triad.And, can be after the chemical vapor deposition (CVD) reaction of its polysilicon, by a high-temperature diffusion method impurity become into, or after deposition, adopt the mode that ion is implanted, with impurity with the ion kenel, in the implanted polysilicon, or when the deposition reaction of polysilicon, (In-situ) carries out the infiltration of impurity simultaneously, and the first type conductive layer, 230 thickness of its formation are the 300-2000 dust.
Follow-up, shown in Fig. 2 B, with a hot processing procedure, it can be Fast Heating processing procedure or boiler tube processing procedure, in temperature is 400 ℃-1200 ℃, feed inert gas, so that titanium/titanium nitride layer 210 that forms before and reaction polysilicon layer 220 react to form titanium silicide layer 240, the titanium silicide layer 240 of its formation has low-resistance matter and heat-staple characteristic.
Thereafter, shown in Fig. 2 C, carry out a hot processing procedure, it can be Fast Heating processing procedure or boiler tube processing procedure, is 400 ℃-1200 ℃ in temperature, aerating oxygen, make the first type conductive layer surface produce silicon dioxide layer, its silicon dioxide layer thickness is the 5-200 dust, as the antifuse layer 235 of the anti-fuse-type memory assembly of control, so important suitable with inhomogeneity control of the quality of antifuse layer 235.
Then, the antifuse layer 235 that forms before the definition, the titanium-silicon compound layer 240 and the first type conductive layer 230 are to form character line, and it comprises that known technologies such as little shadow and etching do not encyclopaedize at this.In between lead, insert dielectric material after forming lead, it can be the formed silicon dioxide of chemical vapour deposition technique with a high-density electric slurry (HDP), it is dense that the electricity slurry that ion concentration in its electricity slurry is more general excites chemical vapour deposition technique, so can utilize the method for deposition/etching/deposition, have preferable ditch and fill out ability, can insert in the gap that forms behind the lead.Next, (CMP) removes unnecessary dielectric layer with chemical mechanical milling method, and makes its planarization.
Next, shown in Fig. 2 D, deposit the second type conductive layer 250 on antifuse layer 235, it can be the polysilicon layer of doping N+, be to use a chemical vapour deposition technique (CVD), at 450 ℃-800 ℃, reaction pressure is in the condition deposit of 0.1Torr-10Torr in reaction temperature, and its thickness is the 1000-6500 dust.The second type conductive layer forms diode action as conduction and with the first type conductive layer that forms before, so it also needs lower resistivity, and the impurity that it mixed is arsenic or other pentad.The method of its implantation, also be can by high-temperature diffusion method impurity become into, or in the mode that adopts ion to implant.Being noted that it is opposite with the first type conductive layer 230 that forms before that the kenel of the second type conductive layer 250 needs, and easily says it, can also be the P+ type at the polysilicon layer of this step deposition, and the polysilicon of deposition be the N+ type before.
Thereafter, define the second type conductive layer 250 to form bit line, it comprises light shield, develop, and etching.In between lead, insert dielectric material after forming lead, it also is the formed silicon dioxide of chemical vapour deposition technique with a high-density electric slurry (HDP), inserts in the gap that forms behind the lead, thereafter, (CMP) removes unnecessary dielectric layer with chemical mechanical milling method, and makes its planarization.
See also shown in Figure 4, it is the stereogram of the metal silicide processing procedure of the anti-fuse-type memory assembly of demonstration the present invention polysilicon, titanium silicide layer 240 is formed at semiconductor-based the end 200, itself and the first type conductive layer 230 as character line (WL) and the second type conductive layer 250 as bit line (BL).Wherein, there is titanium nitride layer 210 at 200 at the titanium silicide layer 240 and the semiconductor-based end as adhesive effect, and in the middle of the first type conductive layer 230 and the second type conductive layer 250 antifuse layer 235 arranged.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, in not breaking away from design of the present invention and scope; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (20)
1. the manufacture method of an anti-fuse-type memory assembly comprises the following steps:
One substrate is provided;
Form a bonding coat on this substrate;
Form a metal level on this bonding coat;
Form a reaction polysilicon layer on this metal level;
Form one first type conductive layer on this reaction polysilicon layer;
Make this metal level and this bonding coat of part and the reaction of this reaction polysilicon layer to form a metal silicide layer;
Form an antifuse layer on this first type conductive layer;
Graphical this first type conductive layer, metal silicide layer, antifuse layer are to form character line;
Form one second type conductive layer on this antifuse layer; And
Graphical this second type conductive layer is to form bit line.
2. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this substrate is the semiconductor substrate.
3. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this metal level is a titanium, cobalt, or nickel is formed.
4. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this bonding coat is the nitride of titanium, the nitride of cobalt or the nitride of nickel.
5. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this reaction polysilicon layer constitutes for the polysilicon storehouse of unadulterated polysilicon in regular turn and one first type ion doping.
6. the manufacture method of anti-fuse-type memory assembly as claimed in claim 5 is characterized in that: the unadulterated polysilicon layer reaction that forms metal level and this reaction polysilicon layer of this metal silicide layer forms.
7. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this first type conductive layer is that the P type and the second type conductive layer are the N types.
8. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this first type conductive layer is that the N type and the second type conductive layer are the P types.
9. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
10. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: the method that forms an antifuse layer is this first type conductive layer of heating.
11. the manufacture method of anti-fuse-type memory assembly as claimed in claim 1 is characterized in that: this antifuse layer is silicon dioxide or silicon nitride.
12. the manufacture method of an anti-fuse-type memory assembly comprises the following steps:
One substrate is provided;
Form a bonding coat on this substrate;
Form a metal level on this bonding coat;
Form a reaction polysilicon layer on this metal level;
Form one first type conductive layer on this reaction polysilicon layer;
Make the reaction of this metal level and this reaction polysilicon layer to form a metal silicide layer;
Form an antifuse layer on this first type conductive layer; And
Graphical this first type conductive layer, metal silicide layer, antifuse layer are to form character line.
13. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this substrate is the semiconductor substrate.
14. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this metal level is a titanium, cobalt, or nickel is formed.
15. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this bonding coat is the nitride of titanium, the nitride of cobalt or the nitride of nickel.
16. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this reaction polysilicon layer constitutes for the polysilicon storehouse of unadulterated polysilicon in regular turn and one first type ion doping.
17. the manufacture method of anti-fuse-type memory assembly as claimed in claim 16 is characterized in that: the unadulterated polysilicon layer reaction that forms metal level and this reaction polysilicon layer of this metal silicide layer forms.
18. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
19. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: the method that forms an antifuse layer is this first type conductive layer of heating.
20. the manufacture method of anti-fuse-type memory assembly as claimed in claim 12 is characterized in that: this antifuse layer is silicon dioxide or silicon nitride.
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| CNB2004100594275A CN1320633C (en) | 2003-07-22 | 2004-06-18 | Structure and producing method of back-fuse type memory assembly |
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| CN03146105 | 2003-07-22 | ||
| CN03146105.0 | 2003-07-22 | ||
| CNB2004100594275A CN1320633C (en) | 2003-07-22 | 2004-06-18 | Structure and producing method of back-fuse type memory assembly |
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| CN1320633C true CN1320633C (en) | 2007-06-06 |
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| US7728390B2 (en) * | 2005-05-06 | 2010-06-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-level interconnection memory device |
| US8067815B2 (en) * | 2008-12-11 | 2011-11-29 | Macronix International Co., Lt.d. | Aluminum copper oxide based memory devices and methods for manufacture |
| CN106653729A (en) * | 2015-11-02 | 2017-05-10 | 中国科学院微电子研究所 | Anti-fuse structure and manufacturing method thereof |
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|---|---|---|---|---|
| US5298784A (en) * | 1992-03-27 | 1994-03-29 | International Business Machines Corporation | Electrically programmable antifuse using metal penetration of a junction |
| US6420215B1 (en) * | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
| US6444558B1 (en) * | 1996-08-26 | 2002-09-03 | Micron Technology, Inc. | Methods of forming and programming junctionless antifuses |
| US6525953B1 (en) * | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
| CN2741188Y (en) * | 2003-07-22 | 2005-11-16 | 台湾积体电路制造股份有限公司 | Structure of reverse-fuse memory assembly |
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2004
- 2004-06-18 CN CNB2004100594275A patent/CN1320633C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298784A (en) * | 1992-03-27 | 1994-03-29 | International Business Machines Corporation | Electrically programmable antifuse using metal penetration of a junction |
| US6444558B1 (en) * | 1996-08-26 | 2002-09-03 | Micron Technology, Inc. | Methods of forming and programming junctionless antifuses |
| US6420215B1 (en) * | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
| US6525953B1 (en) * | 2001-08-13 | 2003-02-25 | Matrix Semiconductor, Inc. | Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication |
| CN2741188Y (en) * | 2003-07-22 | 2005-11-16 | 台湾积体电路制造股份有限公司 | Structure of reverse-fuse memory assembly |
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