CN1314121C - 集成电路结构及其制造方法 - Google Patents
集成电路结构及其制造方法 Download PDFInfo
- Publication number
- CN1314121C CN1314121C CNB2004100949060A CN200410094906A CN1314121C CN 1314121 C CN1314121 C CN 1314121C CN B2004100949060 A CNB2004100949060 A CN B2004100949060A CN 200410094906 A CN200410094906 A CN 200410094906A CN 1314121 C CN1314121 C CN 1314121C
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- transistor
- field effect
- type field
- sidewall spacer
- effect transistor
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- 230000000295 complement effect Effects 0.000 title abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 64
- 230000005669 field effect Effects 0.000 claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
- 238000005516 engineering process Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims 2
- 230000008569 process Effects 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 239000007943 implant Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- 238000001802 infusion Methods 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 7
- 230000006872 improvement Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 235000013495 cobalt Nutrition 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Abstract
Description
Claims (24)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/726,326 US6946709B2 (en) | 2003-12-02 | 2003-12-02 | Complementary transistors having different source and drain extension spacing controlled by different spacer sizes |
US10/726,326 | 2003-12-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1624922A CN1624922A (zh) | 2005-06-08 |
CN1314121C true CN1314121C (zh) | 2007-05-02 |
Family
ID=34620506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100949060A Active CN1314121C (zh) | 2003-12-02 | 2004-11-18 | 集成电路结构及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6946709B2 (zh) |
JP (1) | JP2005167252A (zh) |
CN (1) | CN1314121C (zh) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6975006B2 (en) * | 2003-07-25 | 2005-12-13 | Taiwan Semiconductor Manufacturing Company | Semiconductor device with modified channel compressive stress |
JP2006253198A (ja) * | 2005-03-08 | 2006-09-21 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7541632B2 (en) * | 2005-06-14 | 2009-06-02 | Micron Technology, Inc. | Relaxed-pitch method of aligning active area to digit line |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
JP5076119B2 (ja) * | 2006-02-22 | 2012-11-21 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US7618868B2 (en) * | 2006-05-03 | 2009-11-17 | Samsung Electronics Co., Ltd. | Method of manufacturing field effect transistors using sacrificial blocking layers |
US7541239B2 (en) * | 2006-06-30 | 2009-06-02 | Intel Corporation | Selective spacer formation on transistors of different classes on the same device |
JP5096716B2 (ja) * | 2006-09-21 | 2012-12-12 | パナソニック株式会社 | 半導体装置の製造方法および半導体装置 |
US7550351B2 (en) * | 2006-10-05 | 2009-06-23 | International Business Machines Corporation | Structure and method for creation of a transistor |
JP5040286B2 (ja) * | 2006-12-13 | 2012-10-03 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
US20080272437A1 (en) * | 2007-05-01 | 2008-11-06 | Doris Bruce B | Threshold Adjustment for High-K Gate Dielectric CMOS |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
JP4994139B2 (ja) * | 2007-07-18 | 2012-08-08 | パナソニック株式会社 | 半導体装置及びその製造方法 |
CN102915969B (zh) * | 2011-08-03 | 2015-07-22 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其制造方法 |
CN102446857B (zh) * | 2011-09-08 | 2013-12-04 | 上海华力微电子有限公司 | 一种用于提高半导体器件性能的硅化物掩模刻蚀方法 |
CN106208990B (zh) * | 2016-08-26 | 2019-03-19 | 宜确半导体(苏州)有限公司 | 一种射频功率放大器及射频前端模块 |
CN108962987B (zh) * | 2017-05-19 | 2020-11-13 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5696012A (en) * | 1995-12-29 | 1997-12-09 | Lg Semicon Co., Ltd. | Fabrication method of semiconductor memory device containing CMOS transistors |
US5963803A (en) * | 1998-02-02 | 1999-10-05 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3095564B2 (ja) * | 1992-05-29 | 2000-10-03 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
JPH0766296A (ja) | 1993-08-31 | 1995-03-10 | Toshiba Corp | Mis型半導体装置及びその製造方法 |
US5846857A (en) | 1997-09-05 | 1998-12-08 | Advanced Micro Devices, Inc. | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance |
JP2000223568A (ja) * | 1999-02-02 | 2000-08-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002026139A (ja) | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US6696334B1 (en) * | 2002-09-30 | 2004-02-24 | Advanced Micro Devices, Inc. | Method for formation of a differential offset spacer |
-
2003
- 2003-12-02 US US10/726,326 patent/US6946709B2/en not_active Expired - Lifetime
-
2004
- 2004-11-18 CN CNB2004100949060A patent/CN1314121C/zh active Active
- 2004-12-02 JP JP2004349300A patent/JP2005167252A/ja active Pending
-
2005
- 2005-07-27 US US11/191,426 patent/US7572692B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5696012A (en) * | 1995-12-29 | 1997-12-09 | Lg Semicon Co., Ltd. | Fabrication method of semiconductor memory device containing CMOS transistors |
US5963803A (en) * | 1998-02-02 | 1999-10-05 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths |
Also Published As
Publication number | Publication date |
---|---|
US6946709B2 (en) | 2005-09-20 |
JP2005167252A (ja) | 2005-06-23 |
US20050116296A1 (en) | 2005-06-02 |
CN1624922A (zh) | 2005-06-08 |
US7572692B2 (en) | 2009-08-11 |
US20050263826A1 (en) | 2005-12-01 |
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Effective date of registration: 20170109 Address after: The Cayman Islands (British) Grand Cayman Patentee after: INTERNATIONAL BUSINESS MACHINES Corp. Address before: American New York Patentee before: Globalfoundries second U.S. Semiconductor Co.,Ltd. Effective date of registration: 20170109 Address after: American New York Patentee after: Globalfoundries second U.S. Semiconductor Co.,Ltd. Address before: American New York Patentee before: International Business Machines Corp. |
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Effective date of registration: 20180328 Address after: Ontario, Canada Patentee after: International Business Machines Corp. Address before: The Cayman Islands (British) Grand Cayman Patentee before: INTERNATIONAL BUSINESS MACHINES Corp. |