CN1306398C - Method for acquiring file status by using Verilog hardware description language - Google Patents
Method for acquiring file status by using Verilog hardware description language Download PDFInfo
- Publication number
- CN1306398C CN1306398C CNB031570372A CN03157037A CN1306398C CN 1306398 C CN1306398 C CN 1306398C CN B031570372 A CNB031570372 A CN B031570372A CN 03157037 A CN03157037 A CN 03157037A CN 1306398 C CN1306398 C CN 1306398C
- Authority
- CN
- China
- Prior art keywords
- file
- register
- data
- group
- original value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The present invention discloses a method utilizing a Vrilog hardware description language to obtain file states. The method comprises the following steps that a file register set which is composed of more than one register is set, and file data is stored in the file register set when the file is operated; the method judges whether the valve of the data in the file register set is the original value of the data in the register or not, if true, the register is empty, else, the register is not empty; the file state is judged according to the states of the registers of the file register set. On the basis of no need of other languages, the present invention utilizes the Verilog language to judge the file states, and accordingly the files are dynamically written, read and exchanged in the disc.
Description
Technical field
The present invention relates to electronic system design of Simulation technical field, be meant that especially a kind of Verilog of utilization hardware description language (HDL, Hardware Description Language) obtains the method for file status.
Background technology
Along with the expansion of electronic system scale in the Electronic Design and the raising of complexity, the designer must carry out the design of sophisticated electronic system by hardware description language by modes such as emulation, modelings.The main hardware description language that adopts is VHDL and Verilog HDL in the Electronic Design at present.Wherein, VerilogHDL releases later, this language relatively is suitable for the digital display circuit modeling from algorithm level, register transfer level, logic level, gate leve to the multiple abstract design level of switching stage, and with its grammer flexibly, be easy to characteristics such as grasp, complete function, favorable expandability, progressively become a kind of hardware description language that the designer extensively adopts.
But the Verilog language also comes with some shortcomings, for example: when using Verilog to carry out the simulating, verifying of FPGA (Field Programmable Gate Array) design, often need dynamically read and write the operation of exchange to the file in the disk.Wherein modal situation is: the test and excitation module generates data file, bus functional model (BFM, Bus Function Mode) module reads this document data, and send the data to logic by the interface of BFM and logic, after the BFM judgment data runs through, this data file is emptied, the test and excitation module judges that this data file is behind the sky, the regeneration data write this data file, so circulation; Equally, when logic sends data to BFM by interface, BFM writes a data file in the disk with the data of its reception, the test and excitation module judges whether this data file is empty, if non-NULL, the data that then read are wherein analyzed, empty this data file after running through, BFM judges that this data file behind the sky, receives data and writes this data file from logic again, so circulation.
In said process, test and excitation module and BFM module need all to judge that whether this data file is empty, and also want the judgment data file whether to run through when read data files when carrying out the dynamic data exchange by a file in the disk.But in the file operation system task that the Verilog language is provided, do not provide directly whether the judgment data file is empty, the system task whether data file runs through.Therefore often make that being obliged to go to seek method for distinguishing when carrying out this generic operation solves.
A solution of prior art is: utilize the language interface able to programme (PLI, Programming Language Interface) of Verilog language to expand the file operation function of Verilog, the file operation function of promptly using high-level programming language.As: judge whether file is sky, read file and parts such as whether file finishes are read in judgement, then the data that read is passed to the part that Verilog writes in the use C language compilation test code, last, combined debugging C and Verilog code.But this scheme need relate to the hybrid programming of Verilog and higher level lanquage, and like this, for the logical design personnel and the tester of PLI that is unfamiliar with Verilog and high-level programming language, this scheme is just unworkable.
The another kind of scheme of prior art is: utilize file operation system function and the system task of expanding Verilog based on the stdio function of C, provide empty not, read system tasks such as file individual data, the judgement end of file as the judgement file, and be compiled into kit, when emulation, be connected under the emulation tool working environment, and in the Verilog code, call these system functions and task in use.Though this scheme designs the programming that does not need directly to contact the C language with the tester, but how using by the Verilog file operation system task of stdio function expansion also needs to relearn, and when emulation, how to be connected with emulation tool, different emulation tools also there is different requirements, brought inconvenience to test so on the one hand, cause the transplantability of test code poor on the other hand, the test code of finishing can't carry out under different test software platform.
So, owing to do not provide the system task of obtaining this data file state in the Verilog language, make when the design of carrying out electronic system and test, often need be by means of other Languages or the extendfile beyond the Verilog, thereby caused user of service's design and tested inconvenience, a series of shortcomings that can't avoid such as test code transplantability difference.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of Verilog of utilization hardware description language to obtain the method for file status, utilize the Verilog language on the basis that need not the other Languages intervention, realize judgement, and then realize the dynamic read-write exchange of file file status.
A kind of Verilog of utilization hardware description language obtains the method for file status, may further comprise the steps:
A) the file register group of being made up of an above register is set, when file is operated, in order file data is stored in the file register group successively from first register;
B) judge whether the data in the file register group are the original value of this data place register, if then this register is empty, otherwise this register is a non-NULL;
C) judge file status according to the state of described file register group register.
This method step c) specifically comprise: judge in the file register group whether all registers all are empty, if then the file deposited of this document registers group is for empty, otherwise the file that this document registers group is deposited is a non-NULL.
This method step c) specifically comprise: judge in the file register group whether first register is empty, if then the file deposited of this document registers group is for empty, otherwise the file that this document registers group is deposited is a non-NULL.
This method step c) specifically comprise: the register number of non-original value in the statistics file registers group, this number are the number of data in the file deposited of described file register group.
This method step c) specifically comprise: find out the register that is positioned at last non-original value in the file register group, this register is the end point position of file register group respective file.
This method step c) specifically comprises: the data of reading each register by the order of deposit data successively, whether the register that the next one is read out in the file register group that judgement is read each all be original value, if, then this document data are run through, otherwise this document data do not run through as yet.
The described original value of this method is the x that is used to represent uncertain value before the initialization of register.
The described original value of this method is the z that is used to represent high value behind the initialization of register, or any one agreement can not appear at the character in the file data.
The described step a) of this method further comprises: before file operation each of each register in the file register group all is initialized as described original value.
The described step a) of this method further comprises: the wherein at least one position with each register in the file register group before file operation is initialized as described original value, specifically can be the beginning or the relaying optional position of storer.
This method is described with file data storing to the method in the file register group to be: adopting in the Verilog language standard provides De $readmemb Huo $readmemh system task that the file on the disk is read and is stored in the file register.
From such scheme as can be seen, a kind of Verilog of utilization hardware description language provided by the present invention obtains the method for file status, need not be by other Languages, by judging the original value of file register, just realized to file whether being empty, whether the data number of file, the end point of file and file data processed the judgement of a series of file status information such as finishes; And utilize the modular system task of Verilog language itself, realized the dynamic read-write exchange of file; Strengthened the function of file being operated by the Verilog language; And the present invention program's code compiling is simple, but design and tester only need use the writing and testing with regard to completion code of familiar Verilog language; Because not introducing other Languages makes the code transplantability good, can carry out emulation with the emulation tool of any support Verilog language.
Description of drawings
Fig. 1 is an embodiment of the invention process flow diagram.
Embodiment
When the present invention program is used to deposit the file register group of file data in establishment, be a certain original value with all register specifications in the file register group.Adopt the Xi Tongrenwu $readmemb Huo $readmemh that provides in the Verilog language standard to read file operation.Be read into the register of file register group when file data after, the file data content can cover the original value of its place register.Like this, just can whether consistent with the original value of register by the data content in the comparand register, judge whether register is empty, and and then know the pairing file status information of file register group, as: whether file is empty, whether the data number in the file, the end point of file and file are run through etc.
Be example with the read operation process to file in the disk below, the embodiment preferable to the present invention is described in detail, referring to shown in Figure 1:
For the file read-write operation, adopt in the Verilog language standard De $readmemb and $readmemh are provided.Their effect all is to read from disk data file is disposable, then data is wherein begun to deposit successively in the file register group from first register.Wherein and difference only is that the former reads binary number, and the latter reads sexadecimal number.
Step 101, define a file register group filereg who is used to preserve file content, the bit wide of the number of registers and each register all should be more than or equal to the number of data in the reading file and the bit wide of each data in the file register group, for example, the register that comprises 500 32 bit wides among the defined file registers group filereg:
reg [31:0] filereg[500:1]。
Each of each register is original value x in the initialization files register then:
for(i＝0；i＜500；i＝i+1)
Filereg[i]=512 ' hx; Each content of registers in the // initialization files registers group
Wherein, generally, be not initialised if carry out file read-write operation preceding document registers group filereg, then each original value of all registers should all be " x " of the uncertain value of representative also, and above-mentioned like this initialization can be omitted.
Step 102 reads file data.For example, adopt $readmemh to read in the file test.dat under the disk D root directory this registers group:
$readmemh(″D：/test.dat″，filereg)。
When reading file data to register, file content, the data that promptly read can cover the place register, and when depositing, the corresponding register of each data is deposited in order successively, and those do not have the register of store data, and its all positions still keep original value " x ".
Step 103, when needs obtain file status, only need to judge whether data value is consistent with original value in each register of file register group, each all still keeps original value " x " if read the result of file and be in the file register group all registers, illustrate that then this document is empty, otherwise, the file non-NULL.
In addition, when reading in register, be to begin to deposit in order from first register owing to file data, therefore if only judge whether non-NULL of file, whether the value that also can only judge first register still is original value, if promptly file is empty as can be known then need not to judge the register of back.For example:
If ((filereg[0])!==512 ' the hx) // current file non-NULL that reads is handled accordingly
begin
……
end
Else // current file the sky that reads handles accordingly
begin
……
end
Simultaneously, because file data is corresponding one by one with register, and deposits in order, therefore after sense data,, can know the number of data in the file by the register number that original value in the statistics file registers group changes; And, can also determine the end point position of file by finding out the reformed register of last original value.After file data is read the file register group, can read the data of handling each register successively by the order of deposit data, at this moment, whether each all is original value " x " can to pass through to judge register next processed in the file register group, judge whether file data is run through, if each all is " x " in the next register of promptly reading, then the supporting paper data are run through, otherwise, illustrate that this document data do not run through as yet.
Another program of the present invention can also be in advance all registers in the file register group each all the initialization value of giving be " z ", wherein " z " represents high value, can not appear in the file data usually.Like this when file is read in registers group, file data can cover place register " z ", those registers that do not covered by file data will still be kept " z " value, whether can be empty to file so equally, whether the data number of file, the end point of file and file data processed file status such as finishes and makes judgement.As a same reason, the present invention also can be in advance each of each register in the file register group all be initialized as other arbitrarily in advance agreement can not appear at value in institute's read data file, judge the state of file.
In addition, because when file data reads in register, all be step-by-step in sequence, therefore the present invention program also can be when initialization, only first assignment with each register of file register group is original value, like this, when carrying out the file status judgement, also can know file status by first place value of judging data in the register.And then, because when file data reads in register, if the file of being read is a non-NULL, file data meeting covers register content, if the bit wide of register is bigger than the bit wide of file data, the position that those file datas do not have to cover also can be received in data " 0 ", therefore, the present invention also can be with certain one or more original value that are set to of each register, like this when carrying out the file status judgement, only need to judge whether set this one or more original value changes, and just can know whether there is file data in the register, and then know file status.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind of Verilog of utilization hardware description language obtains the method for file status, it is characterized in that, may further comprise the steps:
A) the file register group of being made up of an above register is set, when file is operated, in order file data is stored in the file register group successively from first register;
B) judge whether the data in the file register group are the original value of this data place register, if then this register is empty, otherwise this register is a non-NULL;
C) judge file status according to the state of described file register group register.
2, according to the described method of claim 1, it is characterized in that this method step c) specifically comprise: judge whether all registers all are empty in the file register group, if, then the file deposited of this document registers group is for empty, otherwise the file that this document registers group is deposited is a non-NULL.
3, according to the described method of claim 1, it is characterized in that this method step c) specifically comprise: judge whether first register is empty in the file register group, if, then the file deposited of this document registers group is for empty, otherwise the file that this document registers group is deposited is a non-NULL.
4, according to the described method of claim 1, it is characterized in that this method step c) specifically comprise: the register number of non-original value in the statistics file registers group, this number are the number of data in the file deposited of described file register group.
5, according to the described method of claim 1, it is characterized in that this method step c) specifically comprise: find out the register that is positioned at last non-original value in the file register group, this register is the end point position of file register group respective file.
6, according to the described method of claim 1, it is characterized in that, this method step c) specifically comprises: the data of reading each register by the order of deposit data successively, whether the register that the next one is read out in the file register group that judgement is read each all be original value, if, then this document data are run through, otherwise this document data do not run through as yet.
According to the described method of claim 1, it is characterized in that 7, the described original value of this method is the x that is used to represent uncertain value before the initialization of register.
, according to the described method of claim 1, it is characterized in that the described original value of this method is the z that is used to represent high value behind the initialization of register, or any one agreement can not appear at character in the file data.
9, described according to Claim 8 method is characterized in that, described step a) further comprises: before file operation each of each register in the file register group all is initialized as described original value.
10, described according to Claim 8 method is characterized in that, described step a) further comprises: the wherein at least one position with each register in the file register group before file operation is initialized as described original value.
11, according to the described method of claim 1, it is characterized in that this method is described with file data storing to the method in the file register group to be: adopting in the Verilog language standard provides De $readmemb Huo $readmemh system task that the file on the disk is read and is stored in the file register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031570372A CN1306398C (en) | 2003-09-11 | 2003-09-11 | Method for acquiring file status by using Verilog hardware description language |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031570372A CN1306398C (en) | 2003-09-11 | 2003-09-11 | Method for acquiring file status by using Verilog hardware description language |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1595358A CN1595358A (en) | 2005-03-16 |
| CN1306398C true CN1306398C (en) | 2007-03-21 |
Family
ID=34660176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031570372A Expired - Fee Related CN1306398C (en) | 2003-09-11 | 2003-09-11 | Method for acquiring file status by using Verilog hardware description language |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1306398C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859242B (en) * | 2010-06-08 | 2013-06-05 | 广州市广晟微电子有限公司 | Register reading and writing method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6487698B1 (en) * | 2001-05-04 | 2002-11-26 | Lsi Logic Corporation | Process, apparatus and program for transforming program language description of an IC to an RTL description |
| US6539520B1 (en) * | 2000-11-28 | 2003-03-25 | Advanced Micro Devices, Inc. | Systems and methods for generating hardware description code |
| US20030084410A1 (en) * | 2001-10-05 | 2003-05-01 | Andrew Rankin | SPICE to Verilog netlist translator |
-
2003
- 2003-09-11 CN CNB031570372A patent/CN1306398C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6539520B1 (en) * | 2000-11-28 | 2003-03-25 | Advanced Micro Devices, Inc. | Systems and methods for generating hardware description code |
| US6487698B1 (en) * | 2001-05-04 | 2002-11-26 | Lsi Logic Corporation | Process, apparatus and program for transforming program language description of an IC to an RTL description |
| US20030084410A1 (en) * | 2001-10-05 | 2003-05-01 | Andrew Rankin | SPICE to Verilog netlist translator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1595358A (en) | 2005-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3786795A1 (en) | Memory allocation method and apparatus for neural network | |
| CN103577308B (en) | Method for obtaining log files of mobile device | |
| US5966143A (en) | Data allocation into multiple memories for concurrent access | |
| CN1248116C (en) | General purpose testing arrangement for embedded module and subsystem based on host machine platform | |
| CN1229721C (en) | In circuit emulated equipment using high-level programming language and method thereof | |
| CN109522428A (en) | A kind of external memory access method of the figure computing system based on index positioning | |
| CN1334466A (en) | Modular structure for testing momery in testing system based on event | |
| CN1801155A (en) | Method for combination of original files of hardware design language and checking data files | |
| CN103324466B (en) | Data dependency serialization IO parallel processing method | |
| CN101330412B (en) | Automatization test approach and system based on topological discovery | |
| CN108897572B (en) | Complex type reconstruction method based on variable association tree | |
| Evangelista | High level petri nets analysis with helena | |
| CN103617124B (en) | Flash memory management method and device | |
| CN106055481A (en) | Computer program test method and device | |
| CN1306398C (en) | Method for acquiring file status by using Verilog hardware description language | |
| CN1790316A (en) | Method of inserting and playing slide in file | |
| US5519860A (en) | Central processor index sort followed by direct record sort and write by an intelligent control unit | |
| US7761832B2 (en) | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model | |
| CN113986145B (en) | Memory management method suitable for large-scale integrated circuit back-end design | |
| CN1652111A (en) | Method for implementing realtime database routine operation | |
| US6591264B1 (en) | Method that allows I/O requests to run concurrently with a rollback from a snapshot in a drive array | |
| CN100485637C (en) | Method for realizing hardware register based on built-in applied system | |
| CN1805582A (en) | Method of testing with integrated test tools | |
| CN1622312A (en) | Method for verifying consistency of chip hardware behavior and software simulation behavior | |
| CN101206617B (en) | Data storage method of flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070321 Termination date: 20140911 |
|
| EXPY | Termination of patent right or utility model |