CN1206226A - 球栅极阵列插件 - Google Patents

球栅极阵列插件 Download PDF

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CN1206226A
CN1206226A CN98115625A CN98115625A CN1206226A CN 1206226 A CN1206226 A CN 1206226A CN 98115625 A CN98115625 A CN 98115625A CN 98115625 A CN98115625 A CN 98115625A CN 1206226 A CN1206226 A CN 1206226A
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semiconductor chip
grid array
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CN1126172C (zh
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南泽焕
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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Abstract

一种改进的球栅极阵列插件BGA,可防止焊锡球之间的冲击且提高集成度,包括:衬底,具有第一表面和比第一表面高的第二表面;至少一个半导体芯片,被叠放着配置在第一表面上,在其上部表面设有多个衬垫;多根引线,设在衬底上,其一端与半导体芯片的一部分衬垫连接,另一端露出在该第二表面上;多个导电性焊锡球,形成于半导体芯片的表面和衬底的第二表面上,与半导体芯片的衬垫、以及露出在衬底的第二表面上的引线电气连接。

Description

球栅极阵列插件
本发明涉及一种球栅极阵列插件，特别涉及一种具有经过改进的球配置构造的微型球栅极阵列插件。
随着集成电路制造工艺的迅速发展，用于保护形成于单位芯片上的许多单位元件不受外部环境影响的插件技术，也同其他的制造技术一起得到了发展。在大部分电子装置中，安装有制成插件的半导体芯片，人们努力尽量减小装设有这种半导体芯片的印刷电路板的面积，与这种努力相对应，要求实现插件尺寸的小型化。作为使插件尺寸小型化的技术之一，人们提出了芯片尺寸插件(Chip Size Package：CSP)或芯片规模插件(Chip Scale Package：CSP)，这种插件的尺寸减小到与芯片尺寸相当的程度。在这种芯片规模插件中，球栅极阵列插件(Ball Grid Array Package：BGB Package)，不仅因为它的面积小，而且，还因它的良好的性能及可靠性而引人注目。这种BGA插件有塑料球栅极阵列(Plastic Ball Grid Array：PBGA)插件、多层陶瓷球栅极阵列(CeramicBall Grid Array：CBGA)插件、条带载体自动化引线键合(TAB：Tape AutomatedBonding)球栅极阵列插件及类似球栅极阵列(Ball Grid Array-like)插件。另外，还有Tessera公司开发的微型球栅极阵列插件。
所述球栅极阵列插件，通过在其表面上形成的导电性球与外部电路进行信号传送。半导体芯片集成度的增加会使所述BGA插件上的球数量增加。球数增加会引起球之间的碰击，而且还会使通过球输出、输入的数据产生误差。为了解决这个问题，必须减小球的直径，但这种解决办法受到工艺上的限制而不易实现。
此外，在包括所述BGA插件在内的所有插件中，必须在不增加插件所占面积的条件下提高集成度。
因此，本发明的目的在于提供一种球栅极插件，随着在一定面积内增加安装在单位芯片上的半导体芯片的集成度，可以相应增加用于与外部电路传递信号的球数量。
本发明的另一目的是，提供一种不增加插件所占面积却能提高集成度的球栅极阵列插件。
根据本发明的一个方案，本发明涉及的球栅极阵列插件包括衬底和设置在该衬底内的半导体芯片之类的各种元件。该衬底具有第一表面和比所述第一表面高且形成于所述第一表面周围的第二表面。半导体芯片配置在第一表面上，在其上部表面设有用于与外部电路进行信号传送的多个衬垫，设置在各层上的具有相同功能的衬垫之间相互电气连接，并至少叠放一个。球栅极阵列插件包含设在所述衬底上、其一端与所述半导体芯片的一部分衬垫连接而另一端露出在所述第二表面上的多根引线。本发明的球栅极阵列插件还包含多个导电性焊锡球，形成于半导体芯片的表面和衬底的第二表面上，与半导体芯片的衬垫、以及露出在衬底的第二表面上的引线电气连接。
根据另一个方案，本发明涉及的球栅极阵列插件包括衬底和设在该衬底内的两个叠放的半导体芯片之类的各种元件。衬底具有第一表面和比第一表面高且形成于第一表面周围的第二表面。半导体芯片包括：第一半导体芯片，配置在所述衬底的第一表面上，在其上端的表面上设有用于与外部电路进行信号传送的多个衬垫；第二半导体芯片，配置在所述第一半导体芯片的上部表面上，其尺寸小于所述第一半导体芯片，以便使所述第一半导体芯片的衬垫露出，且在其上部设有多个衬垫。此外，本发明的球栅极阵列插件包含设在衬底上、与线与第一半导体芯片的衬垫在电气上相连通且露出在第二表面上的多根引线。而且，本发明球栅极阵列插件还包括许多导电性焊锡球，这些焊锡球形成在第二半导体芯片的表面和所述衬底的第二表面上，与第二半导体芯片的衬垫、以及露出在衬底的第二表面上的引线电气连接。
附图的简要说明如下：
图1是现有实施例的球栅极阵列插件的概略剖面图；
图2是本发明实施例的球栅极阵列插件的概略剖面图；
图3A～图5B是表示图2所示插件的制造过程的示意图。
图1是现有的芯片规模插件(Chip Scale Package)群中具代表性的微型球栅极阵列(μ-Ball Grid Array：μ-BGA)的概略剖面图。
参照图1，提供了半导体芯片2即印模(die)，它具有内表面2a和外表面2b，在内表面2a上形成有多个半导体元件，在内表面2a的上部表面上形成有许多用于与外部电路传递信号的键合点(未图示)。这些键合点形成于半导体芯片2的端部。在图1中，半导体芯片2的内表面2a朝向下部。在所述半导体芯片2的内表面2a上依次层叠着弹性橡胶4和印刷有电路配线的柔软的梁式引线薄膜6。下面，同附属层(Compliant layer：8)一起说明弹性橡胶4和梁式引线薄膜6。梁式引线薄膜6的配线通过半导体芯片2的键合点和键合连线8而在电气上相互连结。在所述梁式引线薄膜6的表面上，配置有许多导电性焊锡球10，用于在与半导体芯片2之间进行信号的输出输入、以及与外部电路电气连接。
具有上述结构的球栅极阵列插件，通过将导电性的焊锡球10与形成于外部装置的印刷电路板上的配线进行锡焊、或将焊锡球10连接到插座上，而形成电气信号传送体系。
具有上述结构的球栅极阵列插件，为了与日益成为高集成化及小型化的半导体芯片尺寸相适应地增加单位芯片面积上的焊锡球数量，需要减小球径、提高梁式引线键合技术。在满足不了这种要求的情况下，半导体芯片尺寸的减小受到限制。
下面，参照附图说明本发明的优选实施例。
如图2所示，本发明的球栅极阵列插件包括具有第一表面22a和第二表面22b的衬底22。此外，所述衬底22还包括将第一表面22a与第二表面22b的端部连接起来的内侧壁的表面22c。所述衬底22的第一表面22a的尺寸稍大于芯片尺寸，以便将半导体芯片26、32装入在其上。衬底22的第一表面22a形成在衬底22的内表面的中央上，第二表面22b比第一表面22a高规定高度，并沿着第一表面22a的端部配置。第二表面22b具有使衬底22的尺寸不超出半导体芯片26、32的尺寸范围很多的宽度。
半导体芯片26、32包括：第一半导体芯片26，其外表面通过第一粘接剂层24粘接在第一表面22a上；第二半导体芯片32，其外表面通过第一条带(tape)28a和第二条带28b、以及位于它们之间载体薄膜30(Carrier film)而粘附在第一半导体芯片的上部。在第一半导体芯片26和第二半导体芯片32的端部形成多个键合点(未图示)。第一半导体芯片26的形成有键合点的端部，其宽度比第二半导体芯片32大规定尺寸，这是为了使第一半导体芯片26的键合点不被设置在其上方的第二半导体芯片32所覆盖而露出。在第二半导体芯片32上装入弹性橡胶34，该弹性橡胶具有可使第二半导体芯片32端部上的键合点露出的尺寸。在弹性橡胶34的上部和第二半导体芯片32端部的上面，覆盖着柔软的导电性梁式引线薄膜36。该梁式引线薄膜36包含从第二半导体芯片32的键合点所在端部一直延伸到弹性橡胶34的上表面的多根第一引线。该梁式引线薄膜36的第一引线的一端与第二半导体芯片32的键合点电气连结着。其另一端与附着在其上的导电性的第一焊锡球38a相连接。
在衬底22上埋设着多根第二引线40，这些引线的两侧端部露出在第二表面22b和内侧壁的表面22c上。露在衬底22的内侧壁表面22c上的第二引线40的一端，通过连线42与第一半导体芯片26的相应键合点进行键合。露在衬底22的第二表面22b上的第二引线40的另一端，与形成于第二表面22b上的第二焊锡球38b连接。为了保护连线42和设在第二半导体芯片32的端部上的印刷电路板不受外部冲击、并固定，在其上覆盖一层密封剂44。
具有上述结构的球栅极插件，通过将导电性的第一、第二焊锡球38a、38b与形成于印刷电路板上的配线进行锡焊、或与插座连接，形成电信号传送系统。
此外，根据设计规则(Design rule)，所述第一半导体芯片26的键合点，可全部与第二焊锡球38b进行电气连接、或只有一部分与第二焊锡球38b进行电气连接。在只有一部分与第二焊锡球38b连接的情况下，其余的键合点与梁式引线薄膜36的第一引线中的、不与第二半导体芯片32的键合点相连接的剩余的引线相连接，并与第一焊锡球38a相连接。
如上所述，通过改变键合点的连接方式，本实施例的构造可适用于第一半导体芯片26与第二半导体芯片32具有相同功能的RAM(随机存储器)或ROM(只读存储器)中。此外，本实施例的构造也适用于第一半导体芯片26与第二半导体芯片32具有不同功能的情况，即例如第一半导体芯片26是具有控制功能的微处理器、第二半导体芯片是具有存储功能的RAM(随机存储器)或ROM(只读存储器)等存储芯片的情况。
下面，参照图3A至图5B说明制造图2中的球栅极阵列插件的方法。
图3A表示在衬底22的第一表面上装入第一半导体芯片26的状态的平面图，图3B是沿图3A中的3B-3B′线剖开的断面图。
参照图3A和图3B，可提供这样的衬底22，即，例如具有正六面体形状，并具有比其端部侧的第二表面22b的高度低规定高度的第一表面22a，该高度差可使半导体芯片被装入到衬底22的中央部。所述衬底22由绝缘材料制成，最好是用塑料化合物制成。所述衬底22侧壁的内表面22c具有规定的倾斜度，如图3C的概略放大图所示，在该倾斜面中埋设着多根具有导电性能的第二引线(或接线柱：Stud)40，用于与第一半导体芯片26进行信号的输入出入。所述第二引线40最好是用金(Au)制成。如图3C所示，衬底22的侧壁内表面22c形成阶梯式的，以便使每3根引线配置在同一平面上，这样可提高引线40的集成度。在所述衬底22的第一表面22a上，粘附着沿其端部具有许多衬垫电极(图未示)的第一半导体芯片26，而且是在填充有粘接剂24的状态下粘附的。粘附第一半导体芯片26之后，再实施把所述第二引线40与第一半导体芯片26的衬垫电极电气连接的工序。如图3C所示，在本实施例中，由于所述第一半导体芯片26与第二引线40保持相隔规定距离的状态，因此，采用引线键合方法，用连线42把各第二引线40和与其对应的各衬垫电极连接起来。但是，上述引线键合方法也可改变为其他方法。
参照图4A和图4B，为了在第一半导体芯片26上叠放面积小于第一半导体芯片26的第二半导体芯片32，将第一条带28a粘附在所述第一半导体芯片26上，然后在其上依次粘附载体薄膜30和第二条带28b。在第二条带28b上装入第二半导体芯片32，在第二半导体芯片32上装入弹性橡胶(elastomer)34，该弹性橡胶34的面积足以使沿第二半导体芯片32的端部形成的衬垫电极露出。把形成有配线图的梁式引线薄膜36粘接在所述弹性橡胶34和第二半导体芯片32的端部上，然后进行梁式引线键合，把形成于第二半导体芯片32端部的多个衬垫电极与梁式引线薄膜36的第一引线电气连接。图4A所示的平面图表示上述过程结束的状态。
配线工序结束后，进行封装(encapsulation)工序，用密封剂44把露出有配线的斜面区封起来。此时，用于密封的物质是液态的密封树脂。
接着，如图5A及图5B所示，为了分别与第一半导体芯片26和第二半导体芯片32进行信号的输入出入，进行形成焊锡球的工序。露出在衬底22的第二表面上的引线40的端部与形成于其表面上的第二焊锡球38b连接，梁式引线薄膜36的各引线与形成于其上部表面的第一焊锡球38a连接，构成与所述第一、第二半导体芯片26、32之间的信号传送系统。
在上述实施例中，虽说明了叠放一个半导体芯片的例子，但也可以通过减小倾斜面的斜度来增加接线柱(stud)的集成度的办法，用2层或2层以上的芯片构成插件。即，装入在最上部的半导体芯片，用与上述实施例的第二半导体芯片同样的方法进行配线连接，其余半导体芯片用引线连接，这样，能够以固定面积制造具有更高容量的插件。
此外，所述球栅极阵列插件也适用于单层芯片的插件，这种插件存在着键合点数量过多且焊锡球之间易产生冲击的问题。在这种情况下，半导体芯片的一部分键合点与形成于衬底的第二表面上的第二焊锡球之间形成电信号传送通路；半导体芯片的其余键合点与形成于梁式引线薄膜的上部的第一焊锡球之间形成电信号传送通路。前面未说明的结构与前面说明的实施列一样，因此，这里不再重复。
如上所述，本发明的球栅极阵列插件是将半导体芯片进行多层叠放而成的，因此，能够以一样的面积制造具有更高容量的插件。而且，本发明的插件，不仅在芯片上部、而且在衬底上部也可形成用于构成与半导体芯片的键合点之间的信号传送通路的焊锡球，因此，即使不发展用于减小球径的技术，也可防止焊锡球之间的冲击。又因不需要更高的引线键合技术，可利用现有技术水平的引线键合技术，所以，可防止制造费用增加和收获率降低的问题。而且，制成的插件是降温型插件(down type)，所以散热效果好。
这里，虽然对本发明的特定实施例作了说明，但同业者可对它进行修改或改变其形式。因此，可理解为只要是属于本发明的真正思想范畴内的所有的修改和变形均包括在本发明的权利要求范围内。

Claims (14)

1．一种球栅极阵列插件，其特征在于，包括：衬底，具有第一表面和比所述第一表面高且形成于所述第一表面周围的第二表面；至少一个半导体芯片，被叠放着，并配置在所述第一表面上，在其上部表面设有用于与外部电路进行信号传送的多个衬垫(pad)，设置在各层上的具有相同功能的衬垫之间相互电气连接；多根引线，设在所述衬底上，其一端与所述半导体芯片的一部分衬垫连接，另一端露出在所述第二表面上；多个导电性焊锡球，形成于所述半导体芯片中的放置于最上层的半导体芯片的表面和所述衬底的第二表面上，与所述半导体芯片的衬垫、以及露出在所述衬底的第二表面上的引线电气连接。
2．如权利要求1所述的球栅极阵列插件，其特征在于，还包括介于所述半导体芯片的衬垫与连接在所述半导体芯片的衬垫上的焊锡球之间的附属(compliant)层，所述附属层包括：导电性的图样层，把所述半导体芯片的衬垫与所述半导体芯片的衬垫电气连接；缓冲层，用于缓冲对所述半导体芯片的外部冲击。
3．如权利要求2所述的球栅极阵列插件，其特征在于，所述缓冲层是弹性橡胶(elastomer)。
4．如权利要求1所述的球栅极阵列插件，其特征在于，与所述引线相连接的键合点，通过连线被键合。
5．如权利要求4所述的球栅极阵列插件，其特征在于，具有所述连线和通过所述连线被键合部分的部分，被硬化的液态树脂封装起来。
6．如权利要求1所述的球栅极阵列插件，其特征在于，所述半导体芯片中的最下方的半导体芯片粘附在所述衬底的第一表面上，在所述半导体与所述衬底的第一表面之间填有粘接剂。
7．如权利要求1所述的球栅极阵列插件，其特征在于，所述插件还包含按第一粘接层、具有导电性图样的载体薄膜、以及第二粘接层的顺序介于所述半导体芯片之间的膜。
8．一种球栅极阵列插件，其特征在于，包括：衬底，具有第一表面和比所述第一表面高且形成于所述第一表面周围的第二表面；第一半导体芯片，配置在所述衬底的第一表面上，在其上端的表面上设有用于与外部电路进行信号传送的多个衬垫；第二半导体芯片，配置在所述第一半导体芯片的上部表面上，其尺寸小于所述第一半导体芯片，以便使所述第一半导体芯片的衬垫露出，且在其上部设有多个衬垫；多根引线，设置在所述衬底上，与所述第一半导体芯片的衬垫电气连接，且露出在所述第二表面上；多个导电性的焊锡球，形成于所述第二半导体芯片的表面和所述衬底的第二表面上，并与所述第二半导体芯片的衬垫、以及露出在所述衬底的第二表面上的引线电气连接。
9．如权利要求8所述的球栅极阵列插件，其特征在于，还包括介于所述半导体芯片的衬垫与连接在所述半导体芯片的衬垫上的焊锡球之间的附属(compliant)层，所述附属层包括：导电性的图样层，把所述半导体芯片的衬垫与所述半导体芯片的衬垫电气连接；缓冲层，用于缓冲对所述半导体芯片的外部冲击。
10．如权利要求9所述的球栅极阵列插件，其特征在于，所述缓冲层是弹性橡胶(elastomer)。
11．如权利要求8所述的球栅极阵列插件，其特征在于，与所述引线相连接的键合点，通过连线被键合。
12．如权利要求8所述的球栅极阵列插件，其特征在于，具有所述连线和通过所述连线进行键合的部分，被硬化的液态树脂封装起来。
13．如权利要求8所述的球栅极阵列插件，其特征在于，所述半导体芯片中的最下方的半导体芯片粘附在所述衬底的第一表面上，在所述半导体与所述衬底的第一表面之间填有粘接剂。
14．如权利要求8所述的球栅极阵列插件，其特征在于，所述插件还包含按第一粘接层、具有导电性图样的载体薄膜、以及第二粘接层的顺序介于所述半导体芯片之间的膜。
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TW396473B (en) 2000-07-01
CN1126172C (zh) 2003-10-29
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KR19990006158A (ko) 1999-01-25
US6072700A (en) 2000-06-06
JPH11135670A (ja) 1999-05-21

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