CN1167336A - 多层非晶硅的制造方法 - Google Patents
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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Abstract
一种形成多层非晶硅的方法，包含在一半导体底材上形成一氧化硅层；在氧化硅层上形成至少二层的多晶硅层；在多晶硅层上形成一金属硅化层；及在金属硅化层上定义闸极区。本发明可以减低氟原子对于氧化硅层及整个元件的影响并可以减低多晶硅化金属与金属连线之间的电阻值。
Description
本发明是关于一种形成多晶硅化金属的方法，特别是关于一种形成多层非晶硅的制造方法。
传统金属氧化半导体形成闸极的方法是使用多晶硅化金属的结构，因此又称为沉积的多晶硅(ADP)结构，也即先在硅底材上长一薄氧化硅层，再沉积一多晶硅层，最后在此多晶硅层上以化学气相沉积法形成一金属硅化层，例如硅化钨。当以化学气相沉积法形成硅化钨时，其反应的副产物氟会在回火时侵入到氧化硅层内，增加氧化硅层的有效厚度，以致影响元件的特性(参考S.L.Hsuet al.，“Direct evidence of gate oxide thickness increase in tungsten polycideprocesses”，IEEE Electron Device Lett.，vol.EDL-12，pp.623-625，1991)。另外，当制程当中进行掺杂步骤时，这些掺杂物会产生横向扩散现象，造成闸极内的掺杂重新分配，使得元件特性改变(参考H.Hayashida et al.，“Dopant redistribution indual gate W-polycide CMOS and its improvement by RTA”，in 1989 VLSI Symp.Tech.Dig，pp 29-30)。再者，由于传统方法所形成的元件结构表面很粗糙，造成多晶硅化金属与金属连线之间的阻值增加(参考H.Yen，“Thermal treatment andunderlayer effects on silane and dichlorosilane based tungsten silicide for deep sub-micro interconnection processes”，in 1995 VLSI Technology，Systems，andApplicaions，pp.176-179)。
鉴于上述的发明背景中，传统方法所产生的诸多缺点，本发明的主要目的在于提供一种形成多层非晶硅的制造方法，可以减低氟原子对于氧化硅层及整个元件的影响。
本发明的另一目的在于减低多晶硅化金属与金属连线之间的电阻值。
本发明的再一目的，可在掺杂过程中防止掺杂物产生横向扩散，以避免在闸极内产生掺杂重新分配现象。
本发明的又一目的，使闸极的表面具有较小的晶体颗粒及较平坦的结构。
根据以上所述的目的，本发明提供了一种在多层非晶硅上形成金属硅化层的方法，包含：在一半导体底材上，形成隔离区，再在半导体底材上形成一氧化硅层；在氧化硅层上沉积至少二层，例如三层，多晶硅层，并在最上层的多晶硅上沉积一金属硅化层；在金属硅化层上定义闸极区及利用闸极及隔离区为遮罩以在半导体底材上植入离子。
根据本发明的如上方法制成的多层非晶硅，其可以减低氟原子对于氧化硅层及整个元件的影响，并减低了多晶硅化金属与金属连线之间的电阻值，另外可在掺杂过程中防止掺杂物产生横向扩散，以避免在闸极内产生掺杂重新分配现象，且使闸极的表面具有较小的晶体颗粒及较平坦的结构。
图1A～1G为本发明形成多晶硅化金属闸极结构的剖面图。
图2显示本发明与传统方法的比较。
图3A为本发明的剖面结构示意图。
图3B为传统方法的剖面结构示意图。
图4A为本发明所产生的闸极的表面显微照片。
图4B为传统方法所产生的闸极的表面显微照片。
图1A显示在半导体底材10上形成隔离区12，此隔离区12的形成如传统区域氧化隔离法，亦即先长一垫氧化层，沉积一氮化硅层，再由光阻定义主动元件区，并在隔离区域植入通道阻隔离子，再以热氧化方法长一约3000～10000A的厚氧化区12。接着，在底材10上长一厚度约30～250A的氧化硅层14，如图1B所示的剖面示意图。
图1C中在氧化硅层14之上连续沉积三层厚度约100～3000A的多晶硅层16、18及20，此多晶硅层的个数至少为二层以上，而在本实施例中为三层，至于其层数的变化，例如四或五层，并不会脱离本发明的精神，均应包含在申请专利范围之内。多晶硅层16、18及20的沉积通常是用化学气相沉积法以100％的SiH4或混合N2、H2，在600至650℃下反应形成的。而在金属氧化半导体的闸极中形成此多晶硅层16、18及20是用以提供较低的功函数，以得到较低的起始电压。
图1D显示在最上层的多晶硅层20上形成一厚约200～2000A的金属硅化层22，用以和多晶硅层20形成低接触电阻，以降低整个闸极的电阻值(又称为sheet resistance)。金属硅化层22通常是经由硅和反射性金属或贵金属的反应而形成，常见的金属硅化物有WSi2、TiSi2、CoSi2、PtSi、MoSi2、Pd2Si及TaSi2。金属硅化物的好处在于降低和多晶硅的串联电阻值，且较金属铝能够承受较高的温度以实施平坦化步骤，其中又以WSi2、TiSi2及CoSi2具较低电阻值及高稳定性而最常被使用。形成金属硅化物的方法可以使用溅镀、蒸镀或化学气相沉积法，将金属沉积在硅表面，再经过几次的回火而得到。另外一种形成金属硅化物的方法是采用同时沉积金属和硅，而此法不像前述方法会侵入多晶硅内部。
形成金属硅化层22之后，再以光阻24定义闸极区26，并蚀去非定义部分直到源汲极区的硅表面露出，如图1F所示。接着，利用闸极区26及隔离区12为遮罩植入离子，以形成源汲极28、30，如图1G所示。
图2显示本发明多层非晶硅与传统方法的比较，纵轴代表经过回火后的氟原子浓度(atoms/cm3)，而横轴则代表闸极的深度(μm)，且图中号码50代表闸极的氧化层。由此图可清楚看出，使用本发明后，其氟原子侵入氧化硅层50及其下方的浓度远较传统(ADP)方法为小，故其形成的元件较易控制，特性也较好。另外，图3A所示为本发明所形成的剖面结构示意图，相对于传统方法所形成的结构(图3B)，本发明借助多层非晶硅60、62及64的结构可以压抑晶体颗粒的成长，因此比图3B多晶硅层66具有较小的晶体颗粒，故氟原子从最上的多晶硅层64向下侵入氧化硅层68的路径远比图3B长，可以减低氟原子对于氧化硅层及整个元件的影响。
由于本发明多层非晶硅(stacked-amorphous-silicon，SAS)具有较小的晶体颗粒，使得元件的表面较平坦，减低多晶硅金属与金属线之间的电阻值。再者，本发明所形成的结构可以在掺杂过程中防止掺杂物产生横向扩散，以避免闸极内的掺杂重新分配现象。
图4A及图4B分别为本发明及传统方法所产生的闸极的表面显微照片，可清楚看出图4A较图4B具有较小的晶体颗粒及较平坦的表面结构。
以上所述仅为本发明的较佳实施例而已，并非用以限定本发明的申请专利范围；凡其它未脱离本发明所揭示的精神下所完成的等效改变或修饰，均应包含在下述的专利要求范围内。
Claims (14)
1.一种在多层非晶硅上形成金属硅化层的方法，其特征在于包含：
在一半导体底材上形成一氧化硅层；
在该氧化硅层上形成至少二层的多晶硅层；
在该多晶硅层上形成一金属硅化层；
在该金属硅化层上定义复数闸极区；及蚀去未被定义的该金属硅化层、该多晶硅层及氧化硅层部分。
2.根据权利要求1所述的方法，其特征在于其中上述的金属为下列之一：钨、钛、钴、铂、钼、钯、钽。
3.根据权利要求1所述的方法，其特征在于其中上述的多晶硅层层数为三。
4.根据权利要求1所述的方法，其特征在于其中上述的金属硅化层是以化学气相沉积法形成。
5.根据权利要求1所述的方法，其特征在于更包含在该半导体底材上形成复数隔离区。
6.根据权利要求5所述的方法，其特征在于形成该闸极之后更包含利用该闸极及该隔离区为遮罩以植入离子至该半导体底材上。
7.根据权利要求1所述的方法，其中上述各多晶硅层的厚度为100～3000。
8.根据权利要求1所述的方法，其中上述的金属硅化层的厚度为200～2000。
9.一种在多层非晶硅上形成金属硅化层的方法，其特征在于包含：
在一半导体底材上形成复数隔离区；
在该半导体底材上形成一氧化硅层；
在该氧化硅层上沉积复数多晶硅层；
在该多晶硅层上沉积一金属硅化层；
在该金属硅化层上定义复数闸极区；
利用该闸极及该隔离区为遮罩以植入离子至该半导体底材上；及蚀去未被定义的该金属硅化层、该多晶硅层及氧化硅层部分。
10.根据权利要求9所述的方法，其特征在于其中上述的金属为下列之一：钨、钛、钴、铂、钼、钯、钽。
11.根据权利要求9所述的方法，其特征在于其中上述多晶硅层的层数为二。
12.根据权利要求9所述的方法，其特征在于其中上述的金属硅化层是以化学气相沉积法形成。
13.根据权利要求9所述的方法，其特征在于其中上述各多晶硅层的厚度为100～3000
14.根据权利要求9所述的方法，其特征在于其中上述的金属硅化层的厚度为200～2000。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/638671 | 1996-04-29 | ||
| US08/638,671 US5710454A (en) | 1996-04-29 | 1996-04-29 | Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure. |
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| Publication Number | Publication Date |
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| CN1167336A true CN1167336A (zh) | 1997-12-10 |
| CN1048820C CN1048820C (zh) | 2000-01-26 |
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| CN97100900A Expired - Lifetime CN1048820C (zh) | 1996-04-29 | 1997-04-04 | 多层非晶硅的制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5710454A (zh) |
| CN (1) | CN1048820C (zh) |
| TW (1) | TW344866B (zh) |
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| US5767558A (en) * | 1996-05-10 | 1998-06-16 | Integrated Device Technology, Inc. | Structures for preventing gate oxide degradation |
| IT1289540B1 (it) * | 1996-07-10 | 1998-10-15 | Sgs Thomson Microelectronics | Metodo per trasformare automaticamente la fabbricazione di una cella di memoria eprom nella fabbricazione di una cella di memoria |
| JP3635843B2 (ja) | 1997-02-25 | 2005-04-06 | 東京エレクトロン株式会社 | 膜積層構造及びその形成方法 |
| JPH10270380A (ja) * | 1997-03-21 | 1998-10-09 | Nec Corp | 半導体装置 |
| JP3109449B2 (ja) * | 1997-04-25 | 2000-11-13 | 日本電気株式会社 | 多層配線構造の形成方法 |
| JP2982759B2 (ja) * | 1997-08-12 | 1999-11-29 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5846871A (en) * | 1997-08-26 | 1998-12-08 | Lucent Technologies Inc. | Integrated circuit fabrication |
| US6208003B1 (en) * | 1997-09-26 | 2001-03-27 | Nippon Steel Corporation | Semiconductor structure provided with a polycide interconnection layer having a silicide film formed on a polycrystal silicon film |
| TW379371B (en) * | 1997-12-09 | 2000-01-11 | Chen Chung Jou | A manufacturing method of tungsten silicide-polysilicon gate structures |
| US6096614A (en) * | 1998-02-06 | 2000-08-01 | Texas Instruments - Acer Incorporated | Method to fabricate deep sub-μm CMOSFETS |
| US6265259B1 (en) * | 1998-02-06 | 2001-07-24 | Texas Instruments-Acer Incorporated | Method to fabricate deep sub-μm CMOSFETs |
| US6143655A (en) * | 1998-02-25 | 2000-11-07 | Micron Technology, Inc. | Methods and structures for silver interconnections in integrated circuits |
| US5920121A (en) * | 1998-02-25 | 1999-07-06 | Micron Technology, Inc. | Methods and structures for gold interconnections in integrated circuits |
| US6121126A (en) * | 1998-02-25 | 2000-09-19 | Micron Technologies, Inc. | Methods and structures for metal interconnections in integrated circuits |
| US6492694B2 (en) * | 1998-02-27 | 2002-12-10 | Micron Technology, Inc. | Highly conductive composite polysilicon gate for CMOS integrated circuits |
| US6815303B2 (en) * | 1998-04-29 | 2004-11-09 | Micron Technology, Inc. | Bipolar transistors with low-resistance emitter contacts |
| US6239003B1 (en) * | 1998-06-16 | 2001-05-29 | Texas Instruments Incorporated | Method of simultaneous fabrication of isolation and gate regions in a semiconductor device |
| JP2002544658A (ja) * | 1998-08-21 | 2002-12-24 | マイクロン テクノロジー， インク． | 電界効果トランジスタ、集積回路、電界効果トランジスタのゲートを形成する方法、及び集積回路を形成する方法 |
| US6011289A (en) * | 1998-09-16 | 2000-01-04 | Advanced Micro Devices, Inc. | Metal oxide stack for flash memory application |
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| KR100377160B1 (ko) * | 1998-12-03 | 2003-08-19 | 주식회사 하이닉스반도체 | 다층실리콘을이용한게이트전극형성방법 |
| KR100505449B1 (ko) * | 1998-12-24 | 2005-10-14 | 주식회사 하이닉스반도체 | 반도체 소자의 폴리사이드 게이트 전극 형성방법 |
| US6221744B1 (en) * | 1999-01-20 | 2001-04-24 | United Microelectronics Corp. | Method for forming a gate |
| US6150251A (en) * | 1999-01-22 | 2000-11-21 | United Microelectronics Corp | Method of fabricating gate |
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| US6001717A (en) * | 1999-02-12 | 1999-12-14 | Vanguard International Semiconductor Corporation | Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set |
| US6797601B2 (en) | 1999-06-11 | 2004-09-28 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects |
| US6730584B2 (en) * | 1999-06-15 | 2004-05-04 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US6153470A (en) * | 1999-08-12 | 2000-11-28 | Advanced Micro Devices, Inc. | Floating gate engineering to improve tunnel oxide reliability for flash memory devices |
| US6642590B1 (en) * | 2000-10-19 | 2003-11-04 | Advanced Micro Devices, Inc. | Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process |
| US6642112B1 (en) * | 2001-07-30 | 2003-11-04 | Zilog, Inc. | Non-oxidizing spacer densification method for manufacturing semiconductor devices |
| KR100481073B1 (ko) | 2002-07-09 | 2005-04-07 | 삼성전자주식회사 | 박막 형성 방법과 이를 이용한 게이트 전극 및 트렌지스터 형성 방법 |
| US6861339B2 (en) | 2002-10-21 | 2005-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for fabricating laminated silicon gate electrode |
| US6902993B2 (en) * | 2003-03-28 | 2005-06-07 | Cypress Semiconductor Corporation | Gate electrode for MOS transistors |
| CN1989597A (zh) * | 2004-07-30 | 2007-06-27 | 应用材料股份有限公司 | 薄硅化钨层沉积和栅金属集成 |
| TWI291246B (en) * | 2005-10-20 | 2007-12-11 | Epistar Corp | Light emitting device and method of forming the same |
| US8252640B1 (en) | 2006-11-02 | 2012-08-28 | Kapre Ravindra M | Polycrystalline silicon activation RTA |
| KR100913003B1 (ko) * | 2007-10-18 | 2009-08-20 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
| US10510851B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance contact method and structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58155760A (ja) * | 1982-03-02 | 1983-09-16 | Fuji Photo Film Co Ltd | 埋め込まれた交差ｍｏｓアレイ及びその製造方法 |
| US4958318A (en) * | 1988-07-08 | 1990-09-18 | Eliyahou Harari | Sidewall capacitor DRAM cell |
| US5347161A (en) * | 1992-09-02 | 1994-09-13 | National Science Council | Stacked-layer structure polysilicon emitter contacted p-n junction diode |
| US5350698A (en) * | 1993-05-03 | 1994-09-27 | United Microelectronics Corporation | Multilayer polysilicon gate self-align process for VLSI CMOS device |
| US5393687A (en) * | 1993-12-16 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making buried contact module with multiple poly si layers |
-
1996
- 1996-04-29 US US08/638,671 patent/US5710454A/en not_active Expired - Fee Related
- 1996-11-04 TW TW085113448A patent/TW344866B/zh not_active IP Right Cessation
-
1997
- 1997-04-04 CN CN97100900A patent/CN1048820C/zh not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5710454A (en) | 1998-01-20 |
| CN1048820C (zh) | 2000-01-26 |
| TW344866B (en) | 1998-11-11 |
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