CN1154167C - 半导体管芯上互连凸块的制作方法 - Google Patents

半导体管芯上互连凸块的制作方法 Download PDF

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CN1154167C
CN1154167C CNB991016068A CN99101606A CN1154167C CN 1154167 C CN1154167 C CN 1154167C CN B991016068 A CNB991016068 A CN B991016068A CN 99101606 A CN99101606 A CN 99101606A CN 1154167 C CN1154167 C CN 1154167C
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layer
projection
eutectic
tin
copper
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CN1224926A (zh
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�޲��ء�A��â��
罗伯特·A·芒罗
�ء�E�������
斯图尔特·E·格里尔
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NXP USA Inc
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Abstract

一种制作互连凸块结构(32，33)的方法。公开了含有铬层(16)、铜层(36)和锡层(40)的内凸块合金化11(UBM)。在一个实施例中，在UBM(11)上制作共晶焊料(45)并回流以形成互连凸块结构。在另一个实施例中，在制作共晶焊料(48)之前，在UBM(11)上制作铅支座(46)。

Description

半导体管芯上互连凸块的制作方法
技术领域
本发明一般涉及到半导体器件的封装，更具体地说是涉及到半导体器件上互连凸块的制作。
背景技术
在半导体工业中，芯片直接焊接(DCA)或倒装芯片键合被用来将半导体管芯连接到诸如陶瓷芯片载体或有机印刷电路板之类的下一层互连布线上。一种DCA方法，即熟知的控制熔塌芯片连接(C-4)，涉及到在半导体管芯的可浸润的键合焊点上淀积高铅含量的焊料凸块。这些焊料凸块然后焊接到PC板之类的下一层互连上的线路或焊点上。
在将焊料凸块连接到PC板之前，必须借助于将诸如共晶锡-铅焊料之类的低温焊料放置在位于需要物理和电学连接的PC板上的焊点上来制备PC板。然后使器件的焊料凸块对准焊料涂覆的焊点并加热，使共晶焊料在器件、C-4凸块和PC板之间产生连接。C-4焊料凸块直接连接到PC板时，要求高于330℃的高温，这要求PC板能够承受这种温度，这样的PC板通常对于大多数应用来说是太昂贵了。
C-4技术在DCA应用中的问题是在PC板上使用第二低温焊料。为了适应C-4管芯的安装而在印刷电路板上放置共晶焊料，这需要额外的时间和费用。估计对于每一个DCA芯片，在印刷电路板上放置共晶焊料的额外费用可能在＄0.50-1.00的范围内。这一额外费用对于某些应用是无法接受的。曾经试图克服用在C-4管芯凸块上放置共晶焊料的方法而对电路板使用共晶焊料的费用。虽然这消除了对电路板使用共晶焊料的费用，但仍然要求在使用共晶焊料之前完成整个C-4工序，而且是C-4工序中的一个额外步骤。与采用C-4结构相关的另一个缺点是用蒸发方法制作高铅含量材料的费用。因此，说明了在制造环境中使用C-4凸块结构倾向于费用昂贵。
使用C-4凸块结构的另一个长期存在的问题是器件的长期可靠性，特别是当用高锡焊料来连接下一层互连时。很早以前就观察到，在某些条件下，内凸块合金化(UBM)受到冲击，引起可靠性问题。在极端的情况下，部分UBM整个剥离管芯，并进入凸块本身。结果是高铅凸块与铬层16直接接触，这不会提供良好的金属间界面。
另一种DCA采用蒸发延伸共晶工艺(E-3)。E-3凸块结构包括直接在厚得多的铅层顶部制作的薄的锡层即帽层。利用这一锡帽，凸块结构在加热时借助于与小部分铅进行反应而形成共晶液态层，形成大块蒸发凸块。使用E-3凸块不需要制备带有共晶焊料的PC板。而且，使用E-3凸块不需要在安装到下一层衬底之前回流焊料凸块。
虽然使用E-3凸块结构克服了C-4结构的某些缺点，但E-3凸块比较软也是有问题的。E-3凸块由于厚的铅层而比较软。铅是高度可延展的元素。虽然铅的延展性有某些优点，但另一些情况下则高度延展性是不可取的。例如，高度可延展的凸块更容易因器件封装和运输过程中发生的物理力而变形。一旦损坏，后续工序就无法保证。因此，一旦E-3凸块结构变形了，器件就必须报废。
DCA工业中一个正在成长的吸引人的领域是为了克服现有技术的问题而采用共晶凸块。但共晶凸块的使用也已证明是有问题的。与DCA器件上共晶凸块相关的一个问题是与安装凸块管芯的有机电路板的限制有关。通常，特别是在廉价应用中，印刷电路板对于确定焊点互连位置具有很宽的制造裕度。由于这种宽的容差，PC板上的大量铜互连可以被暴露作为接触位置。在共晶凸块管芯结构安装到这种电路板的过程中，与DCA凸块相关的焊料和PC板上的铜互连之间的浸润使得得到的支座高度(从PC板表面到器件表面的距离)低于现有下部填充工艺得以可靠地使用的尺寸。
用来克服最小支座高度问题的一个现有技术方法是形成其高度被限制为特定距离的用于管芯的铜支座。但使用铜支座也有问题。使用铜支座的一个问题是大的铜支座能够将应力转移到管芯的有源部分，导致可靠性失效。相反，小的铜支座在与锡发生反应方面有问题，导致完全被反应的铜支座，因而使连接更不可靠。
因此，确认一种能够用于DCA应用中的克服了现有技术问题的凸块结构是有用的。
发明内容
本发明提供一种制作半导体器件上的导电凸块的方法，其特征是下列步骤：提供具有多个凸块焊点的半导体管芯；在多个凸块焊点的每一个上制作引晶层；在引晶层上制作锡层；在多个凸块焊点的每一个上淀积共晶层，使共晶层直接覆盖锡层；以及淀积共晶层后回流共晶层。
本发明提供一种制作半导体器件上的导电凸块的方法，此方法的特征是下列步骤：提供具有互连位置的半导体器件；在互连位置上制作引晶层；在引晶层上制作由铜组成的第一层；使用蒸发工艺在第一层上制作由锡组成的第二层；使用蒸发工艺制作由铅组成的第三层，其中铅形成支座结构；在第三层上制作由共晶材料组成的第四层；回流第四层，以便在互连位置上形成共晶凸块，其中第四层在回流之后包围支座结构。
附图说明
图1剖面图示出了半导体器件上的内凸块合金化结构；
图2剖面图示出了淀积凸块材料之后的图1的内凸块合金化结构；
图3剖面图示出了图2的凸块材料回流之后的管芯凸块；
图4剖面图示出了具有制作在内凸块合金化结构顶部的支座部分的图3的管芯凸块。
具体实施方式
图1示出了具有半导体衬底24、导电互连22(也称为凸块焊点)、钝化层30以及内凸块合金化部分11的器件32。在一个实施例中，半导体衬底24是单晶硅衬底。作为变通，半导体衬底10可以是绝缘体上硅衬底、蓝宝石上硅衬底之类。
在一个实施例中，导电互连22是提供形成对器件32的连接引出用来物理键合的金属键合焊点。此金属焊点通常包含铝或铜。作为变通，导电互连22可以是铝-铜合金或带有氮化钛覆盖层的铝之类的复合层或合金层。
在一个实施例中，钝化层30可以用绝缘材料制作。例如，钝化层可以用掺磷的玻璃、等离子体淀积的氮氧化硅、等离子体增强氮化物、或它们的组合、或其它绝缘材料来制作。
在一个实施例中，器件32的UBM 11包括制作在金属焊点22上的铬层16、铜层36、和锡层40。在UBM 11中可以有另外一些层。例如，在铬层和铜层之间可以有薄的相位区，以及/或者在铜上可以制作金层38以便防止铜在后续加工之前被氧化。
在一个实施例中，用蒸发工艺来制作锡层40，以便确保后续凸块结构对半导体器件32的恰当键合。在另一个实施例中，可以用溅射等方法来制作锡层，具体地说，锡层40用作铜层36和后续层之间的键合剂。通常，锡层40的厚度为1000-12000埃。在一个具体的实施例中，本发明人观察到厚度为1250-1750埃的锡层40足以克服在现有技术中观察到的可靠性问题。下面更详细地讨论本发明的锡层40的相互作用及其在改善整个可靠性方面的效果。
图2示出了在UBM结构11上制作共晶材料42之后的图1结构的一个实施例。为了方便使用半导体管芯的工艺，使用了共晶材料。这种工艺通常是将管芯安装到印刷电路板。在一个实施例中，共晶材料可能包括高锡化合物。一种这样的共晶材料是64％锡-36％铅的焊料。已知有许多其它的共晶材料。此外，本发明人预测了可使芯片适当地安装到衬底的近共晶材料。通常，本发明使用的焊料可以用低于280℃的峰值回流温度来加工，以便能够使用经济的PC板材料。
共晶材料42可以用大量方法和形状中的任何一种来制作。在图2所示的实施例中，已采用了共晶材料42，使之完全包围UBM结构11。这样就有更大的把握在后续的回流步骤中使共晶材料42沿结构11边沿浸润。但在另一个实施例中，共晶材料42可以主要淀积在UBM结构11的顶部而不整个地围绕UBM，其中后续的回流仍然允许围绕边沿而适当地浸润。
在又一个实施例(未示出)中，UBM结构11的实际边沿可以被部分钝化材料30覆盖。在这种结构中，共晶材料42可以制作在结构11的暴露的边界内或结构11的暴露的边界外。可以用任何一种焊料淀积方法来淀积共晶材料42。例如，可以使用焊料喷射淀积、采用模板或掩模或者采用焊料胶的焊料印刷淀积。而且，淀积的焊料42的实际量是所希望的凸块最终尺寸的函数。换言之，为了制作较大的焊料凸块，就需要对器件使用较多的焊料42。通过采用较厚的淀积或借助于将焊料涂于较大的面积，可以控制焊料材料42的不同的量。
回流工序之后，图2的共晶材料42被示作图3中的焊料凸块45。如图3所示，在回流步骤之后，形成了通常包住UBM结构11的边沿的回流共晶区域45。此外，回流工序使共晶区域45能够获得用来进一步安装到印刷电路板衬底时所需的形状。
如前所述，在UBM的铜上制作含锡的凸块和共晶焊料，已引起长期可靠性问题。现有技术指出，过量的锡引起可靠性问题。根据本发明人的工作和观察，现认为可靠性问题的根本原因不仅仅是过量的锡，而且还有与铜锡金属间化合物在UBM层上的形成方法相关的不均匀的应力。此外，本发明人已观察到当高锡焊料在超过220℃的工艺温度下被用于现有技术时，UBM受到冲击的速率大为增加。这被认为是由于铜锡金属间化合物在227℃下与锡接触时变成了液体。见Matijasevic等人的论文Copper Tin Multi-layer Composite Solder。
采用C-4工艺，据信当铅锡被熔化形成C-4凸块时，由于锡-铅凸块中锡的动态相互作用而出现UBM的锡层破裂。锡-铅C-4凸块是在大约3％锡-97％铅的浓度中淀积的。形成C-4凸块的回流步骤之后，在锡-铅C-4凸块中观察到的浓度大约为2％锡-98％铅。损失的1％与UBM的铜层相互作用。由于凸块熔化过程中锡与铜的相互作用，相信在锡与铜反应时就在铜层表面上出现不均匀的应力。由于不一致的应力，就形成裂纹，从而暴露更多的铜去与锡相互作用。结果，分析表明现有技术C-4凸块中的所有的铜最终都与锡反应。这导致锡-铅凸块与铬层16之间的主要物理连接。如已观察到的，这一物理连接很容易随时间变坏。
对本发明的铜层(其中在淀积锡-铅焊料之前制作了均匀的锡层40)的分析显示，在焊料凸块回流之后保留了均匀的铜层。但均匀的锡层40意外地有利于反应，不引起与现有技术C-4铜层相关的破裂。这一结果的意外性质得到了Powell和Trivedi论文Flip Chip on FR-4Integrated Circuit Packaging的支持，该文指出可得到的过量的锡冲击芯片焊点。
优于现有技术的另一点是，比之E3型器件，采用共晶区45降低了器件对物理损伤的敏感性。降低敏感性的一个原因是，即使受到了损伤，在后续安装到印刷电路板的过程中，共晶区45具有回流到其所希望的位置的特性。因此，共晶材料对损伤有较大的容许度。相反，E-3结构具有一旦损伤就倾向保持损伤的刚性的铅部分。当凸块由共晶锡-铅之类构成时，由于整个凸块回流，装配工序就比采用E-3结构时更结实。若采用大量共晶锡-铅焊料来连接C-4凸块，则如Powell和Trivedi所指出的那样，UBM冲击就引起可靠性问题。
在图2的另一个实施例中，层43是C-4工艺所用类型的高铅含量的焊料。通常为97％铅，3％锡。在此实施例中，图3中的结构45可代表回流的高铅含量的焊料。
参照图4，示出了一个变通实施例。在图4的实施例中，在制作共晶部分48之前，在UBM 11顶部制作了支座结构46。支座部分46选择成具有比共晶区45更高的熔点。在后续的安装到印刷电路板的过程中，支座部分46确定半导体器件钝化层30与安装器件的印刷电路板(未示出)之间的空间。当确定将下层膜材料置于器件33和印刷电路板(未示出)之间时，此支座部分46提供了更大的灵活性。虽然任何铅淀积工序应该都可以用，但通常，可利用蒸发铅的工序来制作支座区46。在具体的实施例中，支座区46基本上是纯铅。结构46的高度依赖于填充安装在PC板上的管芯底部所需要的高度。通常，在钝化区以上大约75μm的高度是有利的。在制作支座区46之后，可淀积共晶区48，然后回流以形成图4所示的器件。
应该指出的是，本发明的优点之一是制作在铜层36上的锡层40提供了均匀的锡铜金属间化合物。由于这一金属间化合物，在回流过程中，铜层比现有技术更能够抵抗损伤。例如，在C-4现有技术中，与C-4结构相关的UBM的铜层在回流工序中已观察到完全与锡反应。但在本发明中，由于所形成的均匀的表面结构，UBM的铜层没有机会以不均匀的方式与锡相互作用。结果，在回流之后就仍然保留均匀的体铜层36。同时，部分原来的铜界面36与原来的锡层40已反应以形成铜锡金属间化合物。作为比较，采用诸如与C-4结构相关的现有技术方法，则在铅锡凸块材料回流之后不保留连续的体铜层。此外，保留的铜是金属间化合物形式并已经反应，以致在铜锡金属间化合物的单个“岛”之间形成裂纹和窗口。铜锡金属间化合物之间的间隙使下方的铬能够暴露于铅凸块化合物。结果，铅与铬形成接触，但不一定是可靠的电接触。

Claims (9)

1.一种制作半导体器件上的导电凸块的方法，其特征是下列步骤：
提供具有多个凸块焊点的半导体管芯；
在多个凸块焊点的每一个上制作引晶层；
在引晶层上制作锡层；
在多个凸块焊点的每一个上淀积共晶层，使共晶层直接覆盖锡层；以及
淀积共晶层后回流共晶层。
2.权利要求1的方法，其特征是，还包括在制作锡层的步骤之前和制作引晶层的步骤之后，在多个凸块焊点的每一个上制作铜层的步骤。
3.权利要求2的方法，其特征是，还包括在制作铜层的步骤之后和制作锡层的步骤之前，制作金层的步骤。
4.权利要求1的方法，其中的锡层用蒸发工艺制作。
5.权利要求1的方法，其特征是，还包括在淀积共晶层的步骤之前，在多个导电凸块焊点的每一个上制作支座层的步骤。
6.权利要求5的方法，其中的支座层由铅构成。
7.权利要求5的方法，其中的支座层在回流步骤之后被共晶层包围。
8.权利要求5的方法，其中的支座层在淀积锡层的步骤之后制作。
9.一种制作半导体器件上的导电凸块的方法，此方法的特征是下列步骤：
提供具有互连位置的半导体器件；
在互连位置上制作引晶层；
在引晶层上制作由铜组成的第一层；
使用蒸发工艺在第一层上制作由锡组成的第二层；
使用蒸发工艺制作由铅组成的第三层，其中铅形成支座结构；
在第三层上制作由共晶材料组成的第四层；
回流第四层，以便在互连位置上形成共晶凸块，其中第四层在回流之后包围支座结构。
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