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Publication numberCN1152792 A
Publication typeApplication
Application numberCN 96114412
Publication date25 Jun 1997
Filing date1 Nov 1996
Priority date4 Dec 1992
Also published asCN1052570C, CN1090426A, CN1091943C, CN1149634C, CN1285611A, CN1299331C, CN1348199A, CN1599030A, CN1658389A, CN1658389B, CN100437907C, US5403772, US5563426, US5888857
Publication number96114412.2, CN 1152792 A, CN 1152792A, CN 96114412, CN-A-1152792, CN1152792 A, CN1152792A, CN96114412, CN96114412.2
Inventors张宏勇, 鱼地秀贵, 高山彻, 福永健司, 竹村保彦
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Semiconductor device and making process
CN 1152792 A
Abstract  translated from Chinese
一种制造半导体器件,例如薄膜晶体管的方法。 An example method for manufacturing a thin film transistor semiconductor device. 在非晶硅膜之上或之下,选择形成岛状、线状、条状、点状或膜状的镍、铁、钴、钌、铑、钯、锇、铱、铂、钪、钛、钒、铬、锰、铜、锌、金、银及其硅化物,得到结晶硅膜,再以它们作起始点,在低于普通非晶硅的结晶温度下退火使其结晶化。 Above or below the amorphous silicon film, is selectively formed island-like, linear, strip, dot, or film-like nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold, silver and silicide, to obtain a crystalline silicon film, then they make a starting point, at a crystallization temperature lower than the ordinary annealing the amorphous silicon to crystallize. 通过在将变成晶体管有源区的半导体层之上选择形成覆盖膜,然后再使其热结晶化,构成具有薄膜晶体管的动态电路的同时,得到漏电小和迁移率高的晶体管。 By over the transistor active region into a semiconductor layer formed to cover the film of choice, and then thermally crystallized, while constituting a dynamic circuit having a thin film transistor, and small leakage obtain high mobility transistor.
Claims(7)  translated from Chinese
1.一种制造半导体的件的方法,包括下列步骤:通过低压化学汽相淀积法在衬底上形成一种包括硅的非单晶半导体膜;选择性地形成一包含催化元素的与非单晶半导体膜相接触的衬底;其中一部分非单晶半导体膜是沿着与衬底表面相平行的横方向结晶的。 1. A member of a semiconductor manufacturing method, comprising the steps of: by low pressure chemical vapor deposition method is formed non-monocrystalline semiconductor film comprising silicon on a substrate; selectively forming a catalytic element containing the non- single crystal semiconductor film in contact with a substrate; wherein a portion of the non-single crystal semiconductor film is parallel to the substrate surface along a lateral direction crystal.
2.一种制造半导体的件的方法,包括下列步骤:通过低压化学汽相淀积法,使用单硅烷或乙硅烷在衬底上形成包括硅的非单晶半导体膜;形成一含催化元素的与非单晶膜相接触的衬底;以及用催化元素使非单晶半导体膜结晶。 2. A method of fabricating a semiconductor element, comprising the steps of: by low pressure chemical vapor deposition method, monosilane or disilane comprises a non-single crystal silicon semiconductor film formed on a substrate; forming a catalytic element containing substrate in contact with the non-single-crystal film; and a catalytic element with non-single crystal semiconductor film is crystallized.
3.一种制造半导体的件的方法,包括下列步骤:在衬底上形成一包含催化元素的衬底;用低压汽相淀积法在衬底上形成非单晶半导体膜;以及用催化元素沿着与衬底表面垂直的方向使非单晶半导体膜结晶。 3. A method of fabricating a semiconductor element, comprising the steps of: forming on a substrate comprising a substrate of a catalytic element; non-single crystal semiconductor film by low pressure vapor deposition is formed on a substrate; and a catalytic element along a direction perpendicular to the surface of the substrate so that the non-single-crystal semiconductor film is crystallized.
4.一种制造半导体的件的方法,包括下列步骤:在衬底上选择性地形成包含催化元素的衬底;通过低压化学相淀积法在衬底上形成非单晶半导体膜;以及用催化元素使非单晶半导体膜结晶,其中一部分非单晶半导体膜是沿着平行于衬底表面的横方向结晶的。 A method of fabricating a semiconductor element, comprising the steps of: selectively forming on a substrate a substrate comprising the catalytic element; non-single crystal semiconductor film is formed by low-pressure chemical deposition method is formed on a substrate; and with catalytic element so that non-monocrystalline semiconductor film is crystallized, in which a portion of the non-single crystal semiconductor film is parallel to the substrate surface along a lateral direction crystal.
5.一种制造半导体的件的方法,包括下列步骤:通过低压化学汽相淀积法在衬底上形成包括硅的非单晶半导体膜;形成一包含催化元素的与非单晶半导体膜相接触的衬底;用催化元素使非单晶半导体膜结晶;以及在非单晶硅膜上形成栅电极,其间形成有绝缘膜。 A member of a semiconductor manufacturing method, comprising the steps of: a non-monocrystalline semiconductor film comprising silicon by low pressure chemical vapor deposition is formed on a substrate; forming a catalytic element comprising a non-single crystal semiconductor film with phase a substrate contact; with a catalytic element so that non-monocrystalline semiconductor film is crystallized; in the non-single-crystal silicon film and forming a gate electrode, an insulating film formed therebetween.
6.一种制造半导体的件的方法,包括下列步骤:在衬底上形成栅电极;通过低压化学汽相淀积法在栅电极上形成包括硅的非单晶半导体膜,其间形成有绝缘膜;形成包含催化元素的衬底与非单晶半导体膜相接触;以及用催化元素使非单晶半导体膜结晶。 A member of a semiconductor manufacturing method, comprising the steps of: forming a gate electrode on a substrate; a non-single crystal semiconductor film comprising silicon by low pressure chemical vapor deposition method is formed on the gate electrode, an insulating film formed therebetween ; forming a catalytic element comprising a substrate in contact with the non-single crystal semiconductor film; and a catalytic element used to make non-monocrystalline semiconductor film is crystallized.
7.一种制造半导体的件的方法,包括下列步骤:通过低压化学汽相淀积法在衬底上形成一包括硅的非单晶半导体膜;形成一含催化元素的衬底与非单晶半导体膜相接触;以及在结晶步骤后,除去催化元素。 A member of a semiconductor manufacturing method, comprising the steps of: a non-monocrystalline semiconductor film comprising silicon by low pressure chemical vapor deposition is formed on a substrate; forming a non-monocrystalline substrate and containing the catalyst element contacting the semiconductor film; and after the crystallization step, to remove the catalytic element.
Description  translated from Chinese
半导体器件及其制造方法 Semiconductor device and manufacturing method thereof

本发明涉及一种制造集成电路的方法,或者更具体地涉及包括具有矩阵结构的矩阵器件(包括电——光显示器和半导体存储器)和作为开关元件的MOS或MIS(金属一绝缘体一半导体)型场效应元件(下文一般称之为MOS型元件)的半导体电路,其特征在于它的动态工作,诸如液晶显示和动态RAM(DRAM)及其驱动电路或类似图像传感器的集成驱动电路。 The present invention relates to a method of manufacturing an integrated circuit, or more specifically relates to a device comprising a matrix having a matrix structure (including electrical - optical display and semiconductor memory) and used as the switching element MOS or MIS (metal-insulator-semiconductor) type field-effect element (hereinafter generally referred to as MOS type element) of the semiconductor circuit, characterized in that its dynamic work, such as a liquid crystal display and dynamic RAM (DRAM) or the like and its driving circuit integrated driving circuit of the image sensor. 本发明特别涉及一种采用薄膜半导体元件,诸如形成于绝缘表面的薄膜半导体晶体管或类似物,如MOS型元件的器件,还涉及具有薄膜晶体管的、其有源层是用晶体硅形成的器件。 The present invention particularly relates to the use of a thin-film semiconductor element, such as a thin film formed on a semiconductor transistor or the like, an insulating surface, such as device-type MOS element, but also involves that the active layer is formed using crystalline silicon devices with a thin film transistor.

通常,用于薄膜器件,如薄膜绝缘栅型场效应晶体管(TFT)结晶硅半导体薄膜是用等离子CVD或热CVD方法形成的非晶硅膜在一种设备,如电炉中,在温度高于600℃经24小时以上进行结晶化的方法制备的。 Typically, for the thin film device, such as a thin film insulated gate field effect transistor (TFT) is a crystalline silicon semiconductor thin film amorphous silicon film plasma CVD or thermal CVD method and the like in an apparatus, such as an electric furnace at a temperature higher than 600 Preparation crystallization method ℃ carried by more than 24 hours. 为了得到良好的特征,如高场迁移率和高可靠性,需要进行很多小时的热处理。 In order to obtain good characteristics, such as high-field mobility and high reliability, required many hours of heat treatment.

然而,通常的方法存在许多问题。 However, there are many problems conventional method. 问题之一是其生产率低,随之而来的是产品的成本变得高。 One problem is its low productivity, followed by the cost of the product becomes high. 例如,若花24小时作晶体化处理时,而若每片衬底花费2分钟时间处理,在相同的时间内,必须处理720片衬底。 For example, if it costs 24 hours for the crystallization treatment, and if each piece of the substrate takes 2 minutes treatment, at the same time, the substrate 720 to be processed. 然而一个常用的管式炉一次最多能处理50片衬底,当仅用一个设备(反应管)时,每片花30分钟。 However, a conventional tube furnace can handle a maximum of 50 of the substrate, when only one device (the reaction tube), it took 30 minutes per sheet. 即,为在2分钟处理1片,就必须用15个反应管。 That is, for a 2 min treatment, it is necessary to use 15 reaction tubes. 这意味着必须增加投资规模,那是因为投资被大幅度折旧,但不能在产品成本中反映出来。 This means that you must increase the scale of investment, it is because the investments are substantial depreciation, but not reflected in the product cost.

另一个问题在于热处理的温度。 Another problem is that the heat treatment temperature. 一般,用于制造TFT的衬底大致分为由纯氧化硅组成的玻璃,如石英玻璃、非碱硼硅酸玻璃,诸如Coning No7059(下文称之为Coning7059)。 In general, for manufacturing a TFT is broadly divided into a substrate made of pure silica glass composition, such as quartz glass, non-alkali borosilicate glass, such as Coning No7059 (hereinafter referred Coning7059). 在这些衬底中,前者就温度而言不成问题,因为它的耐热性好,因而能按与正常半导体集成电路的片子加工工艺相同的方式来操作,然而,它的成本高,并随衬底面积的增大而指数增加。 In these substrates, the former will not be a problem in terms of temperature, because of its good heat resistance, which can press with a normal semiconductor integrated circuit wafer processing same approach to the operation process, however, its high cost, and with the liner bottom area increases exponentially. 所以,它仅被用作面积比较小的TFT集成电路。 Therefore, it is used only as a relatively small area TFT integrated circuit.

另一方面,与石英玻璃相比,非碱玻璃的成本虽然十分低,但在耐热方面还存在问题。 On the other hand, compared with quartz glass, non-alkali glass, although the cost is very low, but there are still problems in terms of heat resistance. 因为它的应变点一般在550~650℃,对某些易于应用的材料,或低于600℃。 Because of its strain point is generally 550 ~ 650 ℃, some materials easily applied, or less than 600 ℃. 当用600℃做热处理时,就会导致衬底出现不可逆的收缩或翘曲之类的问题。 When done with 600 ℃ heat treatment, the substrate can lead to problems of irreversible shrinkage or warping and the like. 当衬底的对角线距离超过10cm时尤为显著。 When the diagonal length of the substrate than 10cm is particularly significant. 基于上述原因,人们认为必须保持热处理条件低于550℃,时间不超过4小时,以便降低硅半导体膜结晶化的成本。 For the above reasons, it is believed the heat treatment conditions must be maintained below 550 ℃, no more than 4 hours in order to reduce the silicon semiconductor film is crystallized costs. 因而,本发明的一个目的是提供一种半导体的制造方法,其排除这些条件,以及采用这种半导体来制造半导体器件的方法。 Accordingly, an object of the present invention is to provide a method for producing a semiconductor, which exclude these conditions, and the method of manufacturing such a semiconductor to a semiconductor device.

近来。 Recently. 已进行有关具有薄膜有源层(或称为有源区)的绝缘栅型半导体器件的研究。 Studies have been made about the insulation gate type semiconductor device having a thin film active layer (or active area) of the. 特别是对薄膜绝缘栅晶体管或所谓的薄膜晶体管(TFT)做了热烈的研究。 Especially for the film insulated gate transistors or so-called thin-film transistor (TFT) made a lively research. 它们形成在透明的绝缘衬底上,用来控制每个图象和驱动它的在显示器件,如一个具有矩阵结构的液晶显示器中的矩阵,或用作一个同样形成于绝缘衬底上的图象传感器的驱动电路。 They are formed on a transparent insulating substrate, for controlling each picture and drive it in a display device such as a liquid crystal display matrix structure in the matrix has, or is used as an equally formed on the insulating substrate in Fig. image sensor drive circuit. 根据所用的半导体的材料的晶体状态,它们被分成非晶硅TFT或结晶硅(或称多晶硅)TFT。 The crystal state of the semiconductor material, they are divided into amorphous silicon TFT or crystalline silicon (or polysilicon) TFT.

最近,正开展利用介于多晶和非晶硅之间的中间态的材料的研究。 Recently, the research being carried out between the use of an intermediate state between polycrystalline and amorphous materials. 虽然中间态尚处于讨论中,但所有那些用任何热处理(如用强能量,象激光辐照,在450℃以上的温度的退火)获得的某些晶体状态,在本说明书中被称为结晶硅。 Although the intermediate state is still under discussion, but some of the crystalline state of all those with any heat treatment (e.g. with a strong energy, such as laser irradiation, at annealing temperatures above 450 ℃) is obtained, in the present specification is called a crystalline silicon .

结晶硅TFT作为一个所谓的SOI技术远被用于单晶硅集成电路中,在高集成的SRAM中它被用作一个负载晶体管。 Crystalline silicon TFT as a so-called SOI technology is used in single crystal silicon integrated circuit is far, the high integration of the SRAM which is used as a load transistor. 然而,在这种情况下,很少用非晶硅TFT。 However, in this case, rarely with amorphous silicon TFT.

还有绝缘衬底上的半导体电路的工作速度可以很高,因为在衬底和布线之间没有电容耦合,因而提出一种技术,用它作很高速度的微处理机或很高速度的存储器。 There working speed of the semiconductor circuit on the insulating substrate can be very high, because there is no wiring between the substrate and the capacitive coupling, thus proposed a technique in using it as a high speed microprocessor or a high speed memory .

一般,一个处于非晶态的半导体的场迁移率是低的,因而不能用于工作速度要求很高的TFT。 Usually, an amorphous state of the field mobility of the semiconductor is low, and therefore can not be used for demanding operating speed TFT. 还有,因为P型非晶硅的场迁移率显著的小,不能制成P-型TFT(PMOS的TFT),因而,不能与N沟型TFT(NMOS的TFT)结合形成一个互补MOS电路(CMOS)。 Further, since the P-type amorphous silicon field mobility significantly small, can not be made P- type TFT (PMOS of TFT), and therefore, can not be combined to form a complementary MOS circuit and N-channel type TFT (NMOS the TFT) ( CMOS).

然而,用非晶半导体形成的TFT有一个优点,OFF(关断)电流小。 However, TFT is formed using an amorphous semiconductor has an advantage, OFF (OFF) current is small. 因而它可被用于:工作速度要求不是很高、仅一种导电类型即可、以及要求一个电荷保持能力高的TFT,如具有小矩阵规模的液晶显示的有源矩阵电路的晶体管。 So that it can be used: the operating speed is not very high, only one conductivity type can be, and require a high charge retention capability TFT, such as a transistor active matrix circuit having a matrix of small-scale liquid crystal display. 然而,将非晶硅TFT用于尖端应用,如具有大规模矩陈的液晶显示器中,是困难的。 However, the amorphous silicon TFT for cutting-edge applications, such as a large-scale liquid crystal display moments Chen, is difficult. 还有它自然不能用于显示的外围电路和要求工作速度高的图象传感器的驱动电路。 As well as its nature can not be used for the peripheral circuits and high operating speed requirements of the displayed image sensor driving circuit.

另一方面,结晶半导体的场迁移率大于非晶体半导体的迁移率,可以高速工作。 On the other hand, a crystalline semiconductor field mobility greater than the mobility of an amorphous semiconductor can operate at high speed. 例如,在由激光退火利用再结晶的硅膜制得的TFT中,得到地场迁移率有300cm2/Vs之大。 For example, by the use of laser annealing recrystallized silicon film obtained in the TFT, to obtain a large field mobility of 300cm2 / V s. 由在正常单晶硅衬底上形成的MOS晶体管的场迁移率大约是500cm2/Vs来看,上面的迁移率则是一个极大的数值。 Field on the mobility of a MOS transistor formed normal monocrystalline silicon substrate is about 500cm2 / V s, the mobility of the above it is a great value. 但是,单晶硅上的MOS电路的工作速度受衬底与布线间的寄生电容所限,对用结晶化的硅膜制成的TFT来说,则没有这种限制,因为它是形成于绝缘衬底上的。 However, the operating speed of MOS circuits on a silicon single crystal by the parasitic capacitance between the wiring substrate limited, the TFT of crystalline silicon film is made, there is no such limitation, since it is formed in the insulating on the substrate. 所以在这种TFT中,可达到预期显著高的工作速度。 Therefore, in this TFT, you can achieve a significantly higher expected operating speed.

另外,因为不仅能得到NMOS TFT,而且同样还能得到PMOSTFT,所以可以用结晶硅形成CMOS电路。 Further, since not only get NMOS TFT, but also can get PMOSTFT, crystalline silicon can be formed using a CMOS circuit. 例如,在有源矩阵系统的液晶显示器中,已知用CMOS结晶硅TFT可构成一个不仅具有有源矩阵部分,而且还有外围电路(如驱动器)的所谓的单片结构的系统。 For example, in an active matrix liquid crystal display system, it is known to use a crystalline silicon TFT CMOS may constitute only a portion having an active matrix, a so-called monolithic structure of the system but also a peripheral circuit (e.g., driver). 用于前述的SRAM的TFT正是所提示的这一点,其中的PMOS作为负载晶体管是由TFT构成的。 SRAM is used for a TFT of the tips of the aforementioned point, wherein the PMOS transistor as the load is constituted by a TFT.

再有,用于单晶IC技术的自对准工艺,在正常非晶TFT中不易形成源/漏区,并且由栅极与源/漏区的几何重叠引起的寄生电容带来一个问题。 Furthermore, self-aligned process for the single crystal IC technology, in normal amorphous TFT difficult to form source / drain regions, and the parasitic capacitance caused by the geometry of the gate overlaps with the source / drain regions lead to a problem. 但结晶硅TFT有显著压低这种寄生电容的优点,因为它可采用自对准工艺。 However, the crystalline silicon TFT significant advantage of this parasitic capacitance down, since it can be self-aligned process.

然而,当没有电压施加于栅极(非选时期)时,结晶硅TFT的漏电流,与非晶硅TFT的漏电流相比,是大的。 However, when no voltage is applied to the gate electrode (non-selected period), the leakage current of the crystalline silicon TFT, an amorphous silicon TFT as compared with the leakage current is large. 但采取这样一种对策,提供一个辅助电容去补偿漏电流,并将两个TFT串联连接,减少它用于液晶显示时的漏电流。 But taking such a countermeasure, providing an auxiliary capacitor to compensate for leakage current, and two TFT connected in series, it is used to reduce the leakage current when the LCD.

例如,已经提出:先形成一非晶硅,再在其上选择地辐照激光,仅仅使外围电路结晶化的方法,以便在同一衬底上形成具有高迁移率的单片多晶硅TFT的外围电路,同时利用非晶硅TFT的高截止(OFF)阻抗。 For example, it has been proposed: forming a first amorphous silicon, and then thereon selectively irradiating the laser, so that only the peripheral circuit crystallization method, so as to form peripheral circuit chip having a high mobility polysilicon TFT on the same substrate, , while taking advantage of the high cut-off of amorphous silicon TFT (OFF) impedance.

然而,目前其产量还是低的,那是因为激光辐照工艺的可靠性尚有问题(如在辐照表面内辐照能量的均匀度不好),因而终于采用一种用非晶硅TFT构成一个矩阵,再按TAB或类似方法连接单晶集成电路构成驱动电路的方法。 However, the current yield is still low, it is because there are still question the reliability of the laser irradiation process (such as poor uniformity of radiation energy in the irradiated surface), thus finally adopt a constitution with amorphous silicon TFT a matrix, press TAB, or the like connection method monocrystalline integrated circuits drive circuit. 然而,从连接的结构限制考虑,本方法要宽于0.1mn的象素间距,并且其成本也变得很高。 However, from consideration of the structure of the connection restriction, the present method to be wider than 0.1mn pixel pitch, and its cost becomes high.

本发明想要解决这些难题,但不希望使工艺复杂化,最后降低成本率,提高成本。 The present invention is intended to solve these problems, but do not want to make the process more complicated, the last rate cut costs and improve cost. 本发明想要容易地、区别对待地制造两种类型的TFT,即一种要求迁移率高的TFF和一种要求漏电流低的TFT,同时保持批量生产,并尽量减少工艺的改动。 The present invention is intended to be easily treated differently manufactured two types of TFT, that is, a high mobility requirements TFF low leakage current and a requirement of TFT, while maintaining the mass production, and to minimize process changes.

另外,本发明的另一个目的在于减小CMOS电路中NMOS和PMOS迁移率的差值。 It is another object of the present invention to reduce the difference between the CMOS circuit NMOS and PMOS mobility. NMOS和PMOS间差值的减小可增加电路设计的自由度。 Reduce the difference between the NMOS and PMOS can be increased freedom of circuit design.

采用本发明的半导体电路不是万能的。 The present invention uses a semiconductor circuit is not a panacea. 即,本发明适合于利用电场作用改变透光率或反光率的那种材料,将材料夹在面对面的两电极间,并在电极间施加电场来显示图象的有源矩阵电路,如液晶显示器;在电容内存贮电荷用于保持记忆的存储器件,如DRAM:具有动态电路的电路,如动态移位寄存器,它用MOS晶体管的MOS结构部位的电容或其它电容驱动下一个电路;以及具有数字电路和控制模拟信号输出的电路,如图象传感器的驱动电路。 That is, the present invention is adapted to use an electric field to change the kind of material of the light transmittance or reflectance of the material is sandwiched between two facing electrodes, and the electric field is applied between the electrodes to display an image of the active matrix circuit, such as a liquid crystal display ; charge stored in the capacitor is used to keep the memory of storage device, such as DRAM: dynamic circuit having a circuit, such as the dynamic shift register, with parts of the structure of a MOS transistor MOS capacitor or other capacitor driven by a circuit; and having digital circuits and analog signal output control circuit, such as the image sensor driving circuit. 本发明特别适合于动态电路和静态电路混合设置的一种电路。 A circuit of the present invention is particularly suited for dynamic and static circuit hybrid circuit settings.

本发明的特征在于:先在硅膜之上或之下形成含有由下列材料所组成的组中选出的一种材料的岛状膜、圆点、颗粒、团块或线条,再使其在低于仅仅一般非晶硅热处理过程中的结晶化温度做较短时间的退火,即可得到结晶硅膜,这些材料如下:镍、铁、钴、钌、铑、钯、锇、铱、铂、钪、钛、钒、铬、锰、铜、锌、金和银,以及它们的组合物,而硅膜处于非晶态或无序晶态(例如,一种结晶好的部分和非晶部分相混的状态),可以说基本上是处于非晶态。 The present invention is characterized in that: the first is formed by the group comprising the following materials consisting of a material selected from the island-like film, dot, granules, agglomerates or lines above or below the silicon film, and then to make it in Usually just below the amorphous silicon during annealing crystallization temperature do shorter annealing, the crystalline silicon film can be obtained, these materials are as follows: nickel, iron, cobalt, ruthenium, rhodium, palladium, osmium, iridium, platinum, scandium, titanium, vanadium, chromium, manganese, copper, zinc, gold and silver, and combinations thereof, and the silicon film is an amorphous or disordered crystalline state (e.g., a crystalline portion and the amorphous portion with good mixed state), it can be said substantially amorphous state. 退火可以在氢、氧或氮气氛下进行。 Annealing can be carried out under hydrogen, oxygen or nitrogen atmosphere. 退火可以按下列条件进行:(1)在含氧的气氛中加热A小时,然后在含氢的气氛中加热B小时;(2)在含氧的气氛中加热C小时,再在含氮的气氛中加热D小时;(3)在含氢的气氛中加热E小时,再在含氧的气氛中加热F小时;(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时;(5)在含氮的气氛中加热I小时,再在含氧的气氛中加热J小时;(6)在含氮的气氛中加热K小时,再在含氢的气氛中加热L小时;(7)在含氧的气氛中加热M小时,在含氢的气氛中加热N小时,然后在含氮的气氛中加热P小时;(8)在含氧的气氛中加热Q小时、在含氮的气氛中加热R小时,再在含氢的气氛中加热S小时;(9)在含氢的气氛中加热T小时,在氧气氛中加热U小时,再在含氮的气氛中加热V小时;(10)在含氢的气氛中加热W小时,在含氮的气氛中加热X小时,再在含氧的气氛中加热Y小时;(11)在含氮的气氛中加热Z小时,在含氧的气氛中加热A′小时,再在含氢的气氛中加热B′小时;或(12)在含氮的气氛中加热C′小时,在含氢的气氛中加热D′小时,再在含氧的气氛中加热E′小时。 Annealing can be carried out under the following conditions: (1) A heated hours in an atmosphere containing oxygen, and then heated in the atmosphere containing hydrogen B h; (2) heated in an atmosphere containing oxygen C hours, and then in an atmosphere containing nitrogen heating D hours; (3) heating the E h in the atmosphere containing hydrogen, and then heated in an atmosphere containing oxygen F h; (4) heating in the atmosphere containing hydrogen G hour and then heated in an atmosphere containing nitrogen H hours; (5) was heated in an atmosphere containing nitrogen I hour and then heated in an atmosphere containing oxygen and J h; (6) was heated in an atmosphere containing nitrogen K hour and then heated in the atmosphere containing hydrogen L h ; (7) is heated in an oxygen-containing atmosphere, M h, heated in the atmosphere containing hydrogen N hours, then heated in an atmosphere containing nitrogen P hour; (8) was heated in an oxygen-containing atmosphere, Q h, containing heated in an atmosphere of nitrogen R h, and then heated in the atmosphere containing hydrogen S hours; (9) is heated in the atmosphere containing hydrogen T h, is heated in an oxygen atmosphere U hours and then heated in an atmosphere containing nitrogen V h ; (10) was heated in the atmosphere containing hydrogen W h, heated in an atmosphere containing nitrogen X hours and then heated in an atmosphere containing oxygen Y hours; (11) was heated in an atmosphere containing nitrogen Z hours, containing heated in an atmosphere of oxygen A 'hours and then heated in the atmosphere containing hydrogen B' h; or (12) was heated in an atmosphere containing nitrogen C 'hours, heated in the atmosphere containing hydrogen D' hours, containing heated in an atmosphere of oxygen E 'hours.

关于硅膜的结晶化,过去已经提出一种先形成作为晶核或籽晶的结晶的岛状膜,再使它固相外延生长(例如日本特开平1-214110)的方法。 On the silicon film crystallized in the past has been proposed as a pre-formed crystalline nuclei or seed island film, and then makes the solid phase epitaxial growth (for example, Japanese Unexamined Patent Publication 1-214110) method. 然而,在600℃的温度下,用此方法,可勉强生长晶体。 However, at a temperature of 600 ℃, and by this method, can barely growing crystal. 一般,当硅从非晶态转变为结晶态时,它经受一个工艺过程,非晶态分子链被分开,并在把分开的分子置于不与其它分子耦连的状态之后,分子与某些结晶化的分子相结合,而再结合成为晶体的一部分。 In general, when the amorphous silicon into a crystalline state from, it is subjected to a process, the amorphous molecular chains are separated, and placed in the separate molecules are not coupled with other molecules even after the state of molecules with certain crystallized molecule combination, and then incorporated as part of the crystal. 然而分离原始分子链并保持它们不与其它分子耦合的状态的能量,在此工艺过程中是大的,它阻止了结晶化反应。 However, energy separation and retain their original molecular chain are not coupled with other molecules, a state, in the course of the process is large, which prevents the crystallization reaction. 为提供此能量,用1000℃的温度,需用数分钟,或用600℃的温度,需用数十小时。 To provide this energy, a temperature of 1000 ℃, required a few minutes, or a temperature of 600 ℃, the need to use several tens of hours. 因为,时间与温度(=能量)有指数关系,例如,在低于600℃或在550℃,几乎一点看不到结晶化反应的进展。 Because, time and temperature (= energy) have exponential relationship, e.g., at or below 600 ℃ at 550 ℃, almost point of view see the progress of the crystallization reaction. 固相外延结晶化的概念对此问题也不能给予任何解答。 Solid-phase epitaxial crystallization concept on this issue can not give any answers.

本发明的发明者考虑到,用某些催化作用来降低前述工艺过程中的阻止能量,它完全不同于常规的固相结晶化概念。 Taking into account the present inventors, the use of certain catalytic process to reduce the aforementioned stop energy, it is completely different from the conventional concept of solid-phase crystallization. 本发明者提到:镍(Ni)、铁(Fe)、钴(Co)、钌(Ru)、铑(Rh)、钯(Pd)、锇(Os)、铱(Ir)、铂(Pt)、钪(Sc)、钛(Ti)、钒(V)、铬(Cr)、锰(Mn)、铜(Cu)、锌(Zn)、金(Au)以及银(Ag),易于与硅耦连。 The present inventors mentioned: nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt) , scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au) and silver (Ag), silicon-coupled easy even.

例如,本发明者指出,就镍来说,它易于制成硅化镍(NiSix,0.4≤X≤2.5)其晶格常数接近硅晶体的晶格常数。 For example, the present inventors have noted on nickel, it is easy to be made of nickel silicide (NiSix, 0.4≤X≤2.5) with a lattice constant close to the lattice constant of the silicon crystal. 那么,当模拟三元系-晶体硅硅化镍非晶硅中的能量和其它条件时。 So, when the analog ternary - crystalline amorphous silicon nickel silicide energy and other conditions. 可以观察到,在与硅化镍的边界上,非晶硅易于反应,并大约发生下列反应:非晶硅(硅A)+硅化镍(硅B)→硅化镍(硅A)+晶体硅(硅B)(硅A和硅B指示硅的位置)阻止此反应的势能是非常低的,反应温度也是低的。 Can be observed, on the nickel silicide boundary, an amorphous silicon tend to react, and occurs about the following reactions: Si (silicon A) + Nickel Silicide (silicon B) → Nickel Silicide (silicon A) + Crystalline silicon (Si B) (silicon A and B indicates the position of the silicon Si) prevents the potential energy of this reaction is very low, the reaction temperature is also low. 此反应式指明,在非晶硅被镍转变为晶体硅时,进行该反应。 This reaction formula indicates, the amorphous silicon is converted to nickel crystalline silicon when the reaction is carried. 可以发现,此反应实际上起始于580℃以下,即使在450℃也能观察到此反应。 Can be found, this reaction actually starts at below 580 ℃, even at 450 ℃ to the reaction can also be observed. 当然,温度越高,反应进展的速度越快。 Of course, the higher the temperature, the faster the progress of the reaction. 用上述的其它金属元素,也能看到相同的作用。 Other metal element described above, the same effect can also be seen.

根据本发明,先形成一个至少含有Ni、Fe、Co、Ru、Rh、Pd、Os、Ir、Pt、Sc、Ti、V、Cr、Mn、Cu、Zn、Au以及Ag之中的一种元素的膜、颗粒或团块,如岛状、条状、线状、点状或膜状的镍或上述其它单纯金属制底或它们的硅化物,用作起始点,再按上述反应,把那些金属元素从点扩展到四周,使晶体硅区域延展。 According to the present invention, the first comprising at least one element forming a Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag among a film, particles or agglomerates, such as an island, strip, wire, point-like or film-like nickel or the other pure metal substrate or a silicide, is used as the starting point, then the above reaction, those metal elements extend from a point to four weeks, the crystalline silicon area extended. 另外,氧化物不适于作含有那些金属元素的材料,因为氧化物是一种稳定化合物,不能启动前述反应。 Further, the oxide-containing material is not suitable for those metal elements, since the oxide is a stable compound, the reaction can not start.

从一特定点延展的晶体硅的结构,虽然不同于常规固相外延生长,但它接近于单晶硅,结晶的连续性好,因而适宜用作半导体器件,如TFT。 From a structural point of a particular extended crystalline silicon, although different from the conventional solid phase growth, but it is close to a single crystal silicon, a good continuity of crystallization, and thus suitable for use as a semiconductor device, such as a TFT. 然而,当包括加速结晶化的前述金属如镍等材料被均匀设置于衬底上时,会出现无数个结晶化的起始点,因此难以得到结晶性良好的膜。 However, when including accelerated crystallization of the metal material such as nickel is uniformly disposed on the substrate occurs when numerous crystallization starting point, it is difficult to obtain a film with good crystallinity.

当氢在作为结晶化起始材料的非晶硅中的浓度更低些,所得到的结果更好些。 When a lower concentration of hydrogen in the amorphous silicon crystallization starting material in some, the better the results obtained. 然而,因为当结晶进展时,会释放出氢,故没有看出在所得到的硅膜内的氢浓度和作为起始材料的非晶硅中的氢浓度之间的清楚的相互关系。 However, because when the crystallization progress, will release hydrogen, it is seen that there is no clear correlation between the hydrogen concentration in the hydrogen concentration of the obtained silicon film and amorphous silicon as a starting material in between. 本发明的晶体硅中的氢浓度一般高于0.001at%,低于5at%。 Crystalline silicon of the present invention is generally higher than the concentration of hydrogen 0.001at%, less than 5at%.

虽然Ni、Fe、Co、Ru、Rh、Pd、Os、Ir、Pt、Sc、Ti、V、Cr、Mn、Cu、Zn、Au以及Ag被用于本发明,但这些材料一般不适合作为半导体材料的硅,因而必须除去这些材料。 Although Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag is used in the present invention, but these materials are generally not suitable as a semiconductor silicon material, and thus is necessary to remove these materials. 关于镍,因为达到作为前述反应结果的结晶化的终止的硅化镍容易溶于氢氟酸或氢氯酸或它们的稀释液中,用那些酸处理,可使镍从衬底中减少。 On nickel, because of the reaction to achieve as a result of crystallization of the nickel silicide is easily dissolved in hydrofluoric acid or termination hydrochloric acid or a dilute solution, with those acid treatment, can reduce the nickel from the substrate. 再有,在结晶化工艺终了之后,在含氯的气氛中,经400-600℃的处理,确实可减少那些金属元素,含氯物,如氯化氢、变化的氯化甲烷(CH3Cl、CH2Cl2、CHCl3)、变化的氯化乙烷(C2H5Cl、C2H4Cl2、C2H3Cl3、C2H2Cl4、C2HCl5)或变化的氯化乙烯(C2H3Cl、C2H2Cl2、C2HCl3)。 Further, in the process after the end of crystallization, in an atmosphere containing chlorine, treated 400-600 ℃ indeed reduce those metal elements, chlorine-containing substance, such as hydrogen chloride, methyl chloride variation (CH3Cl, CH2Cl2, CHCl3 ), changes in chlorinated ethane (C2H5Cl, C2H4Cl2, C2H3Cl3, C2H2Cl4, C2HCl5) or ethylene chloride changes (C2H3Cl, C2H2Cl2, C2HCl3). 特别是三氯乙烯是一种容易使用的材料。 In particular TCE is a material easy to use. Ni、Fe、Co、Ru、Rh、Pd、Os、Ir、Pt、Sc、Ti、V、Cr、Mn、Cu、Zn、Au以及Ag在本发明的硅膜中的浓度一般高于0.005at%,低于1at%。 Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, and Ag concentration in the silicon film of the present invention is generally higher than 0.005at% below 1at%.

在根据本发明为半导体元件,例如TFT,制造的晶体硅膜的使用中,最好不在结晶的终端(也是从多个起始点开始的结晶化相互衔接的部位)制备半导体元件,从上面的说明可以明了,那是因为存在大的晶粒边界(晶性不连续的部位)并因为加速结晶化的金属元素,如镍的浓度高。 In accordance with the present invention is a semiconductor element, such as TFT, manufactured using the crystalline silicon film, it is preferable not crystallized terminal (also crystallized from a starting point of a plurality of interrelated parts) preparing a semiconductor device, from the above description will be apparent, it is because there is a large grain boundaries (crystalline discontinuous portion) and accelerate the crystallization because the metal element such as high concentration of nickel. 所以,在利用本发明形成半导体元件时,必须选择最佳的包含将成为结晶化起始点并加速结晶的金属元素,如镍的被覆膜的图形和半导体元件的图形。 Therefore, when using the present invention for forming a semiconductor device, comprising the best must be selected will be the starting point of crystallization and accelerates the crystallization of the metal element, such as a graphic pattern is coated semiconductor element and nickel.

在本发明中,大致有两种方法将加速结晶化的金属元素制成图形。 In the present invention, there are basically two ways to accelerate the crystallization of the metal element into the graphic. 第一种方法是在形成非晶硅膜之间,将那些金属有选择地形成膜和类似物,第二种方法是在形成非晶硅膜之后,有选择地使那些金属形成膜和类似物。 The first method is formed between the amorphous silicon film, those metals are selectively formed film and the like, the second method is, after forming an amorphous silicon film is selectively formed so that the metal film and the like .

第一种方法可用常规光刻法或剥离法来实现。 The first method by conventional photolithography or lift-off technique to achieve. 第二种方法或多或少有些复杂。 The second method is more or less complicated. 即,若所形成的加速结晶化的金属膜或类似物依附于非晶硅膜,当膜形成时,金属和非晶硅局部发生相互反应,产生硅化物。 That is, if the acceleration of crystallization of the formed metal film or the like attached to the amorphous silicon film, when the film is formed, the metal and the amorphous silicon occurs locally react with each other to produce a silicide. 因而,当形成金属膜或类似物之后制成图形时,必须全面腐蚀硅化物层。 Thus, when formed by patterning after forming a metal film or the like, must be fully etching the silicide layer.

按第二种方法,剥离方法比较容易实施。 According to the second method, the peeling method is relatively easy to implement. 在此情况下,有机材料,如光刻胶,或无机材料,如氧化硅或氮化硅可用作掩模材料。 In this case, an organic material, such as photoresist, or an inorganic material, such as silicon oxide or silicon nitride used as a mask material. 在选择掩模材料时,必须考虑处理温度。 When selecting a mask material, the treatment temperature must be considered. 另外,掩模的作用也因材料而异,必须全心关注它。 In addition, the role of the mask is also due to the material varies, must devote attention to it. 特别是,如果膜不是充分的厚,用各种CVD方法形成的氧化硅或氮化硅膜会有许多针孔,因而结晶化可能是从不希望的部位展开。 In particular, if the film is not sufficiently thick, a silicon oxide or silicon nitride film formed by various CVD methods have a lot of pinholes, and thus crystallization may be desired site never expanded.

一般地是在用这些掩模材料形成被覆膜之后,实施刻图,以便有选择地露出非晶硅的表面。 Generally these are in the masking material after forming the coating film, embodiments are patterned to selectively expose the surface of the amorphous silicon. 然后,形成加速结晶化的金属膜或类似物。 Then, a metal film to accelerate crystallization, or the like.

本发明中必须注意在硅膜中金属元素的浓度。 Care must be taken in the present invention, the concentration of the silicon film of metal elements. 再好莫过于金属含量小,但使含量总保持恒定也是至关重要的。 Better than the small metal content, but always remains constant so that the content is essential. 那是因为,如果金属元素的含量有明显的起伏,将导致所制造的各批格点的结晶度的显著起伏。 That is because, if the content of metallic elements have significant ups and downs, ups and downs will lead to a significant degree of crystallinity of the manufactured batches of grid points. 特别当要求金属元素的含量更小些时,就变得更难的减小含量的起伏。 Especially when the content of the metal element requires some time smaller, it becomes harder and downs reduce the content.

在第一方法中,因为选择形成的金属膜或类似物是被非晶硅膜覆盖的,则不能去掉后者去调节它的含量。 In the first method, a metal film or the like is selectively formed because amorphous silicon film is covered, the latter can not be removed to adjust its content. 依照本发明所要求金属元素的含量,金属膜或类似物的厚度薄到只有数至数+之薄,因而很难以良好的再现性来形成该膜。 In accordance with the content of the metal elements required by the present invention, the thickness of the thin metal film or the like to a few to several +   of thin, it is difficult to be formed with good reproducibility of the film.

这同样适用于第二方法。 The same applies to the second method. 不过,与第一种方法相比,第二种方法尚有改进的余地,因为在本方法中,加速结晶化的金属膜或类似物存在于表面。 However, compared with the first method, the second method still room for improvement, because in the present method, the accelerated crystallization of the metal film or the like present on the surface. 即,先形成一个足够厚的金属膜,在退火使非晶硅膜与金属膜局部发生反应,产生硅化物之前,在低于退火温度的温度下,实施一次热处理(预退火)。 I.e., first forming a sufficiently thick metal film, in annealing the amorphous silicon film and a metal film partially react, to produce before the silicide at a temperature lower than the annealing temperature, the implementation of a heat treatment (pre-annealing). 然后,腐蚀掉未经反应的金属膜。 Then, the metal film is etched away without reaction. 这虽然与所用的金属有关,特别是对Ni、Fe、Co、Ti和Cr没问题,因为,有一种对金属膜和硅化物的腐蚀速率都十分大的腐蚀剂。 Although this is related with the use of metal, especially Ni, Fe, Co, Ti, and Cr is no problem, because, there is a metal silicide film and the corrosion rate are very large etchant.

在此情况下,所得到的硅化物的厚度是由热处理(预退火)的温度和时间所决定的,而金属层的厚度几乎与它无关。 In this case, the thickness of the silicide is obtained by heat treatment (pre-annealing) temperature and the time of the decision, and the thickness of the metal layer is almost nothing to do with it. 因此,在非晶硅膜中所引入的金属元素的微小含量是可控制。 Therefore, the content of the amorphous silicon film in tiny introduced metal element is controllable.

本发明还应用,当半导体表面被氧化硅或氮化硅覆盖膜(保护膜)盖住时和使结晶硅TFT在450-1000℃最好在500-800℃在含氧、氢或氮的气氛中结晶化时表面未被覆盖时,结晶度存在差异的情况。 The present invention is also applicable, when the semiconductor surface is silicon oxide or silicon nitride cover film (protective film) when the cover and the crystalline silicon TFT preferably in an atmosphere containing oxygen, hydrogen or nitrogen at 450-1000 ℃ 500-800 ℃ When crystallized surface uncovered, the presence of differences in the degree of crystallinity. 该气氛可以是含氧的气氛,含氢的气氛,含氮的气氛、含氧和氢的气氛、含氧和氮的气氛、含氢和氮的气氛以及含氧、氢及氮的气氛。 The atmosphere may be an oxygen-containing atmosphere, a hydrogen-containing atmosphere, an atmosphere of a nitrogen-containing atmosphere an atmosphere containing oxygen and hydrogen, oxygen and nitrogen, hydrogen and nitrogen and an oxygen-containing atmosphere, hydrogen and nitrogen atmosphere. 前述结晶化可按下列条件进行:(1)在含氧的气氛中加热A小时,然后在含氢的气氛中加热B小时;(2)在含氧的气氛中加热C小时,再在含氮的气氛中加热D小时;(3)在含氢的气氛中加热E小时,再在含氧的气氛中加热F小时;(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时;(5)在含氮的气氛中加热I小时,再在含氧的气氛中加热J小时;(6)在含氮的气氛中加热K小时,再在含氢的气氛中加热L小时;(7)在含氧的气氛中加热M小时,在含氢的气氛中加热N小时,然后在含氮的气氛中加热P小时;(8)在含氧的气氛中加热Q小时,在含氮的气氛中加热R小时,再在含氢的气氛中加热S小时;(9)在含氢的气氛中加热T小时,在含氧的气氛中加热U小时,再在含氮的气氛中加热V小时;(10)在含氢的气氛中加热W小时、在含氮的气氛中加热X小时,再在含氧的气氛中加热Y小时;(11)在含氮的气氛中加热Z小时,在含氧的气氛中加热A′小时,再在含氢的气氛中加热B′小时;或(12)在含氮的气氛中加热C′小时,在含氢的气氛中加热D′小时,再在含氧的气氛中加热E′小时。 The crystallizing according to the following conditions: (1) A heated oxygen-containing atmosphere hours, then heated in the atmosphere containing hydrogen B h; (2) heated in an atmosphere containing oxygen C hours, and then in a nitrogen-containing D atmosphere heated hours; (3) heating in the atmosphere containing hydrogen E h, and then heated in an atmosphere containing oxygen F h; (4) heating in the atmosphere containing hydrogen G h, and then in an atmosphere containing nitrogen heating H hours; (5) were heated in an atmosphere containing nitrogen I h, and then heated in an oxygen-containing atmosphere J hour; (6) was heated in an atmosphere containing nitrogen K hour and then heated in a hydrogen-containing atmosphere L h; (7) is heated in an oxygen-containing atmosphere, M h, heated in the atmosphere containing hydrogen N hours, then heated in an atmosphere containing nitrogen P hour; (8) was heated in an oxygen-containing atmosphere, Q h, heated in an atmosphere containing nitrogen R h, and then heated in the atmosphere containing hydrogen S hours; (9) is heated in the atmosphere containing hydrogen T h, heated in an atmosphere containing oxygen U hours, and then in an atmosphere containing nitrogen heating V h; (10) was heated in the atmosphere containing hydrogen W h, heated in an atmosphere containing nitrogen X hours and then heated in an atmosphere containing oxygen Y hours; (11) was heated in an atmosphere containing nitrogen Z hours, heating in an oxygen containing atmosphere A 'hours and then heated in the atmosphere containing hydrogen B' h; or (12) was heated in an atmosphere containing nitrogen C 'hours, heated in the atmosphere containing hydrogen D' h , and then heated in an atmosphere containing oxygen E 'hours. 尤为可取的是(4)在含氢的气氛中加热G小时,再在含氮的气氛中加热H小时,(5)在含氮的气氛中加热I小时(例如4小时),再在含氧的气氛中加热J小时(例如1小时),或(6)在含氮的气氛中加热K小时(例如4小时),再在含氢的气氛中加热L小时(例如1小时)。 Particularly preferably (4) is heated in the atmosphere containing hydrogen G hour and then heated in an atmosphere containing nitrogen H hours, (5) were heated in an atmosphere containing nitrogen I hour (e.g., 4 hours), and then in an oxygen-containing J h heated in an atmosphere (e.g., one hour), or (6) is heated in an atmosphere containing nitrogen K hours (e.g., 4 hours), and then heated in the atmosphere containing hydrogen L h (e.g., 1 hour). 当存在覆盖膜时,一般来说结晶性是好的,因此可以得到高迁移率的TFT。 When there is a cover film, the crystallinity is generally good, it is possible to obtain a high mobility TFT. 然而,一般其漏电流变得显著。 Generally, however, the leakage current becomes significant. 另一方面,无覆盖膜的TFT的优点在于漏电流小,可是结晶性不好,其迁移率低,因为它依温度实现非晶态。 On the other hand, no cover film TFT advantage that the leakage current is small, but good crystallinity, its mobility is low, because it implements the amorphous according to temperature. 认为其特性是受渗入有源层的气氛中的氢、氧或氮所控制,结晶化可以在例如氮中,然后再在氢或氧中来实现。 Characteristics is considered to penetrate the active layer by an atmosphere of hydrogen, oxygen or nitrogen is controlled, for example, crystallization can be nitrogen, and then in the hydrogen or oxygen to achieve. 在同一衬底、同一时间以及同一工艺过程中形成特性不同的TFT。 Different characteristics of a TFT formed on the same substrate, at the same time and in the same process. 例如,前一种迁移率高的TFT可以用作矩阵中的驱动电路,而后一种漏电流小的TFT可以用作矩阵中的TFT。 For example, the former can be used as a high mobility TFT matrix driving circuit, the leakage current is small, the latter TFT may be used as the matrix TFT.

与PMOS的迁移率相比,或者可以相对降低NMOS的迁移率,在CMOS电路中,靠优选的条件,在NMOS区上不设置保护膜,而在PMOS区上设备保护膜,几乎可以消除两者间的差别。 Compared with the mobility of the PMOS or NMOS can be relatively reduced mobility in CMOS circuits, by preferred conditions are not set in the NMOS region protective film, and in the PMOS device protective film area, virtually eliminating both difference between.

热结晶化的温度是个重要参数,而TFT的结晶性在本发明是由温度决定的。 Thermal crystallization temperature is an important parameter, while the crystallinity of the TFT in the present invention are temperature-dependent. 一般,热退火的温度是受衬底和其它材料限制的。 In general, the thermal annealing temperature is subject to limitations of the substrate and other materials. 就衬底材料的限制而论,当用硅和二氧化硅用作衬底时,热退火温度可高至1100℃。 Limits in terms of the substrate material, when silicon and silicon dioxide used as the substrate, the thermal annealing temperature may be as high as 1100 ℃. 对于Coning7059玻璃,一种典型的无碱玻璃,要求退火温度低于650℃。 For Coning7059 glass, a typical non-alkali glass, require annealing temperatures below 650 ℃. 然而,在本发明基于上述原因,必须为每个TFT,而不是为衬底,设置所要求的重要特征。 However, in the present invention is based on the above-mentioned reasons, must each TFT, and wherein the substrate is not critical, provided the desired. 当退火温度高时,一般会促进晶体TFT的生长,迁移率提高,以及漏电流也提高。 When the annealing temperature is high, generally promote the growth of crystals of the TFT, the mobility increase, and the leakage current also increased. 所以退火温度应为450~1000℃,最好是500~800℃,以便在同一个类似本发明的衬底上得到不同特征的TFT。 Therefore, the annealing temperature should be 450 ~ 1000 ℃, preferably 500 ~ 800 ℃, in order to obtain different characteristics of TFT on the same substrate, similar to the present invention.

本发明的一个实施例是,在液晶显示器有源矩阵电路或类似电路的显示单元中,多晶硅TFT被用作开关晶体管,当使有源层结晶化时,在有源矩阵区不设置保护膜,另一方面,在外围电路区设置护膜,使前者转变成漏电流小的TFT,使后者转变成迁移率高的TFT。 One embodiment of the present invention is a liquid crystal display in an active matrix display unit circuit or the like, the polysilicon TFT is used as the switching transistor, when the active layer is crystallized, the active matrix section is not provided a protective film, On the other hand, in the peripheral circuit region set protective film, so that the former into a leakage current of the TFT, so that the latter into a high mobility TFT.

图8(A)表示如前面所述的具有一个显示电路部分(有源矩阵)和为它而设的驱动电器(外围电路)的一个装置的构思图。 Figure 8 (A) shows as previously described having a circuit portion (active matrix), and it is designed for the electrical drive (peripheral circuit) is a concept diagram of a display apparatus. 在图中,表示一个显示装置,其中安置一个数据驱动器101和门驱动器102,中间安置一个具有TFT的有源矩阵103,通过绝缘衬底107上的门线105和数字线106,将这些驱动器部分与有源矩阵相连接。 In the figure, showing a display device in which to place a data driver 101 and gate driver 102, the middle placement having an active matrix TFT 103 through the gate line insulating substrate 107 on 105 and digit line 106, these drive section is connected with the active matrix. 有源矩阵103是具有NMOS或PMOS TFT的象素单元的集合(图中的PMOS)。 The active matrix 103 is set (figure PMOS) having a pixel unit of NMOS or PMOS TFT.

对于区动部分的CMOS电路,在有源层内的杂质,如氧、氮和碳的浓度最好是低于1018/cm3,或优选低于1017/cm3,以便获得高迁移率。 For the movable portion of the CMOS circuit area, impurity in the active layer, such as the concentration of oxygen, nitrogen and carbon is preferably less than 1018 / cm3, or preferably less than 1017 / cm3, in order to obtain high mobility. 其结果是,TFT的阀值电压,例口在NMPS是0.5~2V,在PMOS是-0.5~-3V,而迁移率在NMOS为30~150cm2/Vs,在PMOS为20~100cm2/Vs。 As a result, the threshold voltage of the TFT, for example mouth in NMPS is 0.5 ~ 2V, the PMOS is -0.5 ~ -3V, and the mobility in NMOS is 30 ~ 150cm2 / Vs, in PMOS is 20 ~ 100cm2 / Vs.

另一方面,采用在1V的漏电压下其漏电流低至1pA的单个的或各个串联的元件,能降低并能进一步完全消除有源矩阵部分的辅助电容。 On the other hand, the use of the drain voltage of 1V low leakage current of 1pA single or individual elements in series, can be reduced and can completely eliminate the active matrix portion further storage capacitor.

本发明的第二个实施例涉及一个半导体存储器。 A second embodiment of the present invention relates to a semiconductor memory. 一个用单晶IC制成的半导体存储器件早已达到其速度极限。 A semiconductor memory device formed using the single crystal IC has already reached its limit speed. 虽然,必须增加晶体管的电流容量,以便使它以更高有速度工作,这将导致功耗的进一步增加,但不能以增加驱动电压来加以处理,因为对DRAM(来说),电容的容量不能再增加,它是靠电容器中存储电荷来执行记忆功能的。 Although, the current capacity of the transistor must be increased, so that it has a higher rate of work, which will lead to a further increase in power consumption, but can not increase the driving voltage to be dealt with, because DRAM (it), capacity of the capacitor can not further increase, it is by the charge stored in the capacitor to perform memory functions.

为什么说单晶IC已经达到了它的速度极限,原因之一是因为由衬底和布线的电容带来很大的损耗,如果用绝缘体做衬底,无须增加功耗即能以足够高的速度工作。 Why crystal IC has reached its speed limit, one of the reasons is because a great deal of loss from the substrate and the wiring capacitance, if done with an insulator substrate, ie, without increasing power consumption at high enough speed the work. 基于此原因,已经提出一种具有SOI(在绝缘体上的半导体)结构的IC。 For this reason, it has been proposed having an SOI (semiconductor on insulator) structure IC.

就1晶体管/单元的结构来说,一个DRAM的电路布局与前述的液晶显示装置的布局几乎相同,而在一个其结构不同于那种结构(例如3晶体管/单元)的DRAM中,当有源层晶体化时,在存储器存储单元(bit)部分不设置保护膜,相反,在驱动电路区域上设置保护膜,因为要求按照与前述液晶显示装置相同的方法,以足够高的速度工作,使前者转变为漏电流小的TFT,使后者转变为漏电流大的TFT。 On the structure of a transistor / cell, the layout of a DRAM circuit layout of the aforementioned liquid crystal display device is almost the same, but its structure is different from that in a structure (e.g., 3-transistor / cell) of the DRAM, when the active When the layer crystallization, the memory cell (bit) is not part of the protective film, on the contrary, a protective film disposed on the driving circuit region, because they require in the same apparatus and method of the aforementioned liquid crystal display, with a sufficiently high speed of work, so that the former into a leakage current of TFT, so that the latter into a leakage current of TFT.

这种半导体存储器件的基本组合结构与图8A所示的结构相同。 This semiconductor memory device of the basic structure of a combination of the same configuration as shown in FIG. 8A. 例如,在DRAM中,标号(101)可以是一个列解码器,(102)是个行解码器,(103)是个存储元件部分,(104)是个单位存储单元(bit),(105)是位(bit)线,(106)是字线以及(107)是(绝缘)衬底。 For example, in a DRAM, reference numeral (101) may be a column decoder (102) is a row decoder (103) is a memory element portion, (104) is a unit memory cell (bit), (105) is a bit ( bit) line (106) and a word line (107) is (insulating) substrate.

本发明的第三个应用例是个用于图象传感器或类似器件的驱动电路,图8(B)表示图象传感器的1位(比特)电路的实例,其中的触发电路108和缓冲电路109一般由CMOS电路构成,并要求响应速度高,以便跟上施加给扫描线的高速脉冲。 A third application example of the present invention is a driving circuit for an image sensor or the like, and Fig. 8 (B) shows an example of an image sensor (bits) of the circuit, wherein the trigger circuit 108 and buffer circuit 109 generally by CMOS circuits, and require high response speed to keep up with high-speed pulse applied to the scan line. 另一方面,位于信号输出级的TFT110 起一个控制作用,从移位寄存器108和109接收一个信号,经光电二级管,把积聚的电荷释放到数据线。 On the other hand, is located in the signal output from a control stage TFT110 effect, the shift registers 108 and 109 receives a signal from, via the photodiode, the accumulated charge is discharged to the data line.

对该TFT110不仅要求响应速度高,而且要求漏电流小。 TFT110 requires not only the high speed of response, and requires low leakage current. 所以,在该电路中,在电路108和109区域结晶时要设置保护膜,使它转变为高迁移率的TFT。 Therefore, in this circuit, when the circuit 108 and the crystallization region 109 to set a protective film, making it into a high mobility TFT. 相反,在TFT110区域结晶时不须设置保护膜,使它转变成低漏电流的TFT。 On the contrary, when the TFT110 region crystal protective film is not required, making it into a low leakage current TFT.

在本发明中,氧化硅、氮化硅或氧氮化硅(SiNxOy)可用作覆盖膜。 In the present invention, silicon oxide, silicon nitride or silicon oxynitride (SiNxOy) may be used as the cover film. 虽然膜越厚,覆盖性能越好,但必须权衡生产率和保护性能,以便确定厚度,因为欲形成厚膜,则须花费时间。 Although the film is thicker, the better the coverage, but must be weighed against productivity and protection performance in order to determine the thickness, because the desire to form a thick, shall take time. 尽管覆盖性能随膜的质量而异,一般来讲,对氧化硅厚度必须大于20nm,对氮化硅厚度必须大干10nm。 Although the coverage performance varies with the quality of the film, in general, must be greater than the thickness of the silicon oxide 20nm, the thickness of the silicon nitride to be big 10nm. 当综合考虑批量生产率和可靠性时,对氧化硅膜和氮化硅膜,其厚度最好都是20~200nm。 When considering mass productivity and reliability, the silicon oxide film and a silicon nitride film having a thickness preferably is 20 ~ 200nm.

本发明的上述和其它优点,通过下面的说明和附图,将变得更加清楚,在各个视图中,相同的标号代表相同的元部件。 The above and other advantages of the present invention, by the following description and the accompanying drawings, will become more apparent in the various views, identical reference numerals denote identical components.

图1(A)~1(C)是表示本实施例(TFT的结晶与布局)的顶视图;图2(A-1)、2(A-2)及2(B)~2(D)是表示实施例工艺(选择结晶工艺)的剖面图;图3(A)~3(C)是表示该实施例(见第一实施例)工艺的剖面图;图4(A)~4(C)是表示该实施例(见笫一实施例)工艺的剖面图;图5(A)~5(C)是表示该实施例(见第二实施例)工艺的剖面图;图6(A)~6(C)是表示该实施例(见第三实施例)工艺的剖面图;图7(A)~7(E)是表示该实施例(见第四实施例)工艺的剖面图;图8(A)是当本发明被用于一有源矩阵装置之案例的方柜图;图8(B)是当本发明被用于一图象传感器的驱动电路的一个电路图;图9(A)~9(C)是表示该实施例工艺的剖面图; Figure 1 (A) ~ 1 (C) shows the example (TFT crystallization and layout) is a top view of the present embodiment; FIG. 2 (A-1), 2 (A-2) and 2 (B) ~ 2 (D) is a sectional view of an embodiment process (selective crystallization process); FIG. 3 (A) ~ 3 (C) shows the embodiment (see the first embodiment) of a cross-sectional view showing the process; FIG. 4 (A) ~ 4 (C ) is a view showing the embodiment (see Example Zi) of a cross-sectional view showing the process; Fig. 5 (A) ~ 5 (C) shows the embodiment (see cross-sectional view of a second embodiment of the) process; Fig. 6 (A) ~ 6 (C) shows the embodiment (see the third embodiment) of a cross-sectional view showing the process; Fig. 7 (A) ~ 7 (E) is a sectional view of the embodiment (see the fourth embodiment) process; FIG. 8 (A) is a diagram when the present invention is the cabinet side for the case of an active matrix device; Figure 8 (B) is a circuit diagram when the present invention is applied to an image sensor driving circuit; FIG. 9 (A ) ~ 9 (C) is a sectional view of the embodiment of the process;

图10(A)~10(C)是表示该实施例工艺的剖面图;以及图11(A)~11(D)是表示该实施例工艺的剖面图。 Figure 10 (A) ~ 10 (C) is a sectional view of the embodiment of the process; and FIG. 11 (A) ~ 11 (D) is a sectional view showing a process of the embodiment.

实施例1在本实施例中将介绍,用在Coning7059玻璃衬底上形成的各个岛状镍膜作起始点,使非晶硅膜结晶化,用所得到的晶体硅膜制造TFT的方法。 Example 1 In the present embodiment will be described, each of the island-like nickel film as a start point on Coning7059 glass substrate formed of the amorphous silicon film is crystallized, the crystalline silicon film using a method of manufacturing a TFT obtained. 根据岛状镍膜是在非晶硅膜之上还是之下形成,则有两种形成岛状镍膜的方法。 According island nickel film is above or below the amorphous silicon film is formed, there are two methods of forming the island-like Ni film. 图2(A-1)表示在硅膜下形成镍膜的方法,而图2(A-2)表示在硅膜上形成镍膜的方法。 Figure 2 (A-1) shows a method of forming a nickel film in the silicon film, and Fig. 2 (A-2) represents a silicon film forming method of the nickel film. 对后一方法必须特别小心,因为在工艺中,有选择地腐蚀镍是在非晶硅膜的整个表面上形成镍之后,镍和非晶硅相互反应,尽管其量很少,将产生硅化镍。 For the latter method must be particularly careful, since in the process, the nickel is selectively etched after forming a nickel on the entire surface of the amorphous silicon film, amorphous silicon and nickel react with each other, in spite of its small amount, will produce nickel silicide . 因为如果硅化镍照原样留下来,则不能得到好的结晶硅膜,本发明目的之在于,必须用氢氯酸或氢氟酸完全去掉硅化镍。 Because if the nickel silicide to stay as it can not get a good crystalline silicon film, object of the present invention is to, with hydrochloric acid or hydrofluoric acid must completely remove the nickel silicide. 因此,非晶硅从原始状态变薄些。 Therefore, some of the amorphous silicon thin from its original state.

另一方面,对前一种情况,虽然没有引起这种问题,在此情况下,除岛状部分之外,也用腐蚀法完全去掉镍膜。 On the other hand, for the former case, although not cause such problems, in this case, in addition to the island shaped portion, also completely removed by etching nickel film. 用氧等离子或臭氧处理衬底,使岛区以外的镍氧化,可以排除残留镍的影响。 With oxygen plasma or ozone treatment of the substrate, the nickel oxide islands outside, you can exclude the impact of residual nickel.

不论哪一种情况,均用等离子CVD方法,在衬底1A(Coning7059)上形成厚度为2000的底层氧化硅膜1B。 In either case, both using a plasma CVD method, the substrate 1A (Coning7059) thickness was formed on the underlying silicon oxide film 2000 1B. 用等离子CVD方法或真空CVD法制备非晶硅膜1,厚200~3000,优选500~1500。 Plasma CVD method, etc., or vacuum CVD amorphous silicon films prepared by a thickness of 200 ~ 3000, preferably from 500 ~ 1500. 基350~450℃退火0.1~2小时去氢,把膜内氢的浓度保持在5at%以下之后,容易使非晶硅膜结晶化。 Group 350 ~ 450 ℃ annealing dehydro 0.1 to 2 hours, the hydrogen concentration of the membrane is maintained after 5at% or less, and is easy to make the amorphous silicon film is crystallized.

就图2(A-1)而论,是在形成非晶硅膜1之前,用溅射法使镍膜堆积到50-1000,优选10O-500。 On Figure 2 (A-1) is concerned, is the formation of an amorphous silicon film before, by sputtering a nickel film stack to 50-1000, preferably 10O-500. 再刻图形成岛状镍区2。 Then engraved nickel zone 2 Figure island formation.

就图2(A-2)而论,则相反,是在形成非晶硅膜1之后,用溅射法使镍膜堆积到50-1000,优选100-500,再刻图形成岛状镍区2。 After on Figure 2 (A-2) is concerned, on the contrary, an amorphous silicon film is formed by sputtering a nickel film stack to 50-1000, preferably 100-500, and then patterned to form an island Nickel zone 2. 图1A表示上述的状态。 1A shows the above state.

每个岛区镍是22μm的方形,间隔设定为5-50μm或例如20μm。 Each Island nickel is 2 2μm square, interval is set to 5-50μm or e.g. 20μm. 用硅化镍代替镍,也取得了同样的效果。 With nickel silicide instead of nickel, also achieved the same effect. 当要形成镍时,将衬底加热至100-500℃,优选180-250℃,能得到良好的结果。 When nickel is to be formed, the substrate is heated to 100-500 ℃, preferably 180-250 ℃, give good results. 那是因为改进了底层硅化镍层与镍膜的粘附,还因为由氧化硅与镍反应产生硅化镍,用氮化硅、碳化硅或硅代替氧化硅也能得到相同的效果。 That is because the underlying silicide to improve the adhesion of the nickel layer and the Ni film, but also because the reaction of silicon oxide and nickel nickel silicide, silicon nitride, silicon carbide, or silicon instead of silicon oxide can be obtained the same effect.

然后在氮气气氛中在450-580℃或例如在550℃退火8小时。 Then in a nitrogen atmosphere at 450-580 ℃ or e.g. annealed at 550 ℃ for 8 hours. 这退火也可以在氮和氢混合气氛中进行。 This annealing may also be carried out in a hydrogen and nitrogen mixed atmosphere. 或者,此退火可以在氢气气氛中进行X1小时,然后在氮气气氛中进行X2小时。 Alternatively, the annealing may be carried out in a hydrogen atmosphere X1 hours, then X2 hours in a nitrogen atmosphere. 图2(B)表示此工艺的中间状态,其中的镍从岛状镍区2推进到靠近中心的边缘,成为硅化镍3A,镍已通过的部位3已变成晶体硅。 Figure 2 (B) shows an intermediate state of this process, wherein the nickel from nickel island region 2 to advance to the edge near the center, becomes nickel silicide 3A, 3 parts of nickel has been adopted into crystalline silicon. 然后如图2(C)所示,从两个岛状镍膜起始的结晶化衔接,而硅化镍3A留在中间,从而结晶化结束。 And FIG 2 (C), the two island from the initial crystallization of the nickel film convergence, and nickel silicide 3A to stay in the middle, so that the crystallization was completed.

图1(B)表示从上看此状态中的衬底,其中图2(C)中的硅化镍是晶间的边界4。 Figure 1 (B) shows this state from the point of view of the substrate, wherein Fig. 2 (C) in the grain boundaries of the nickel silicide is between 4. 当继续退火时,镍沿晶间边界4移动,聚集岛状镍区的中间区5(虽然在此状态下未保持它们原来的形状)。 When continued annealing, between nickel 4 is moved along the grain boundary, the intermediate region 5 island-like nickel accumulation area (although in this state is not maintained their original shape).

用上述工艺可以得到晶体硅,但不希望镍从在此时产生的硅化镍扩散到半导体涂覆膜中。 With the above process can be crystalline silicon, but do not want the nickel from the nickel silicide diffusion generated at this time into the semiconductor coated film. 最好用氢氯酸或氢氟酸腐蚀,消除镍高度集聚的区域。 Preferably with hydrochloric acid or hydrofluoric acid, nickel eliminate highly concentrated areas. 再有,因为镍和硅化镍的腐蚀速度十分大,在用氢氯酸或氢氟酸腐蚀时,硅膜不受影响。 Further, since the etching speed of nickel and nickel silicide is very large, when etching with hydrochloric acid or hydrofluoric acid, the silicon film is not affected. 同时去掉原设置镍的生长点的区域。 At the same time remove the area of the original set of nickel growing point. 图2(D)表示腐蚀后的状态。 Figure 2 (D) shows the state after etching. 原来是晶间边界的部位转变为一个槽4A。 Originally intergranular boundary portion into a groove 4A. 这对形成半导体TFT的区域(有源层或类似层)是不希望的,以致要收缩该槽。 This region (active layer or the like) forming semiconductor TFT is not desirable, so that the groove to shrink. 如图1(C)所示,不使半导体区6跨过晶间边界4来布局TFT。 Figure 1 (C) as shown, without the semiconductor region 6 across the intergranular boundary 4. layout TFT. 即,在平行衬底的水平方向,不在涂覆膜的厚度方向,在镍作用下的晶体生长区内形成TFT。 That is, in the horizontal direction parallel to the substrate, not on the coating film thickness direction, the crystal growth in the area under the effect of nickel is formed TFT. 应均匀安排晶体生长方向,还应尽量缩小残留的镍。 Arrangements should be uniform direction of crystal growth, but also to minimize the residual nickel. 另一方面,栅线7可以跨越晶间边界4。 On the other hand, the gate line across the grain boundary between 7 4.

图3和图4表示用上述工艺得到的晶体硅制作TFT的方法实施例。 Figures 3 and 4 shows a method for forming a TFT of crystalline silicon using the process described above obtained in Example. 在图3(A)中,中间的标号字符X指示图2中原来是槽4A的地方,如图所示,在布局半导体TFT区域时,不能跨过X部位。 In Figure 3 (A), the intermediate reference numerals indicate the character X in Figure 2 where the original groove 4A, as shown, when the layout of the semiconductor TFT region, can not cross the X site. 即,将图2所示工艺所得到晶体硅膜构图形成岛状半导体区11a和11b。 That is, the process shown in Figure 2 to obtain the crystalline silicon film is patterned to form an island semiconductor region 11a and 11b. 然而,用诸如RF等离子CVD、ECR等离子CVD或溅射形成作为栅绝缘膜的氧化硅膜12。 However, as the gate insulating film such as a silicon oxide film 12 by the RF plasma CVD, ECR plasma CVD or sputtering.

进一步,用真空CVD方法掺杂11020~51020/cm3的磷,形成厚3000~6000的多晶硅膜,然后将它构成图(图3(A)),形成栅电极13a和13b。 Further, using a vacuum CVD method doped 1 1020 ~ 5 1020 / cm3 of phosphorus, a polysilicon film 3000 ~ 6000 thick is formed, then it will form (Fig. 3 (A)), forming the gate electrodes 13a and 13b.

然后,用等离子掺杂方法掺入杂质。 Then, by plasma doping method adulterated. 至于掺杂气体,对N型TFT,使用磷化氢(PH3),对p型TFT,使用乙硼烷(B2H6)。 As for the doping gas, on the N-type TFT, using phosphine (PH3), the p-type TFT, using diborane (B2H6). 对磷化氢加速电压是80KeV,对乙硼烷是65KeV。 Phosphine accelerating voltage is 80KeV, for diborane is 65KeV. 在550℃退火4小时,激活杂质,以形成杂质区14a到14b。 Annealed 4 hours at 550 ℃, activation of the impurity to form impurity regions 14a to 14b. 用光能,如激光退火或闪光灯退火的方法,也可以用于激活(图3(B))。 Light energy, such as laser annealing or flash lamp annealing method can also be used to activate (Fig. 3 (B)).

最后,淀积一层厚5000的氧化硅膜作为层间绝缘体15,与正常制作TFT的情况类似,通过该层形成接能孔,在源和漏区形成布线和电极16a~16d。 Finally, a thick silicon oxide film is deposited as an interlayer insulator 5000 15, and similar to the case of the normal production of TFT, forming holes through the layer can be connected, the source and drain regions are formed in the wiring and the electrodes 16a ~ 16d.

TFT(图中N沟型)就是按上述工艺制备的。 TFT (N channel type in Fig.) Is prepared according to the above process. 所得到的TFT的场效应迁移率,在N沟型是40~60cm2/Vs,在P沟型是30~50cm2/Vs。 TFT's field effect mobility obtained in the N channel type is 40 ~ 60cm2 / Vs, the P-channel type is 30 ~ 50cm2 / Vs.

图4表示如何制备铝栅TFT的工艺。 Figure 4 shows how the process of preparing an aluminum-gate TFT. 在图4(A)中,中间的标号字符X指明原是图2中槽4A的地方。 In FIG. 4 (A), the intermediate reference numerals character X in FIG. 2 was originally specified places grooves 4A. 对半导体TFT区域的设置不应跨过X部位。 Set on the semiconductor region should not cross the X TFT portion. 即,将按图2所示工艺得到的晶体硅膜3构图形成岛状半导体区21a和21b。 That is, the process will be the crystalline silicon film shown in Figure 2 was patterned to form island-shaped semiconductor region 3 21a and 21b. 然后,用诸如RF等离子CVD、ECR等离子CVD或测射方法形成作为栅绝膜的氧化硅膜22。 Then, as the gate oxide film, a silicon film is absolutely 22 emitted by the plasma CVD method or measurement, such as RF plasma CVD, ECR, or the like. 当用TEOS(四乙氧硅烷)和氧化原始气体掺杂等离子CVD方法时,能得到满意的效果。 When the plasma CVD method using TEOS (tetraethoxysilane) and oxidation of the original gas doping, etc., can be satisfied with the results. 然后,溅射淀积含1%硅的铝膜(厚5000)再构图形成栅导线和电极23a和23b。 Then, sputter deposition of an aluminum film containing 1% of Si (thickness 5000) and then patterned to form gate conductors and electrodes 23a and 23b.

接着,将衬底浸入3%酒石酸的乙烯乙二醇溶液中,设置镍作为阴极,铝线作阳极,再在二者间通以电流,实施阳极氧化。 Next, the substrate was immersed in a 3% tartaric acid ethylene glycol solution, a nickel as a cathode, aluminum as the anode, and then in between the two energized, anodic oxidation. 起初按2V/分增高其电压来施加电流,当达到220V时,将电压固定。 Initially by 2V / min increased the voltage to current is applied, when it reaches 220V, the voltage is fixed. 当电流变成小于10μA/M2,停止通电,结果,如图4(A)所示形成厚2000的阳极氧化层24a和24b。 When the current becomes less than 10μA / M2, energization is stopped, the results, shown in Figure 4 (A) to form an anode oxide layer having a thickness 2000 24a and 24b of FIG.

然后用等离子体掺杂方法掺入杂质。 Then using plasma doping method adulterated. 关于掺杂气体,对N型TFT用磷化氢(PH3),对P型TFT用乙硼烷(B2H6)。 On the doping gas, on the N-type TFT using phosphine (PH3), of P-type TFT with diborane (B2H6). 附图表示N型TFT。 The drawing shows N type TFT. 对磷化氢加速电压是80KeV,对乙硼烷是65KeV。 Phosphine accelerating voltage is 80KeV, for diborane is 65KeV. 用激光退火激活杂质,形成杂质区25a至25d。 Impurity activation by a laser annealing to form the impurity regions 25a to 25d. 所用的激光是KrF激光(波长248nm),用能量密度为250~300mJ/cm2的激光脉冲辐照5次(图4(B))。 KrF laser is used in laser (wavelength 248nm), with an energy density of the laser pulse irradiation 250 ~ 300mJ / cm2 5 times (Fig. 4 (B)).

最后,淀积厚5000的氧化硅膜,作为层间绝缘体26,类似于正常制备TFT的情况,通过该层形成接触孔,以便形成源和漏区的布线和电极27a~27d(图4(C))。 Finally, a silicon oxide film is deposited to a thickness of 5000, as an interlayer insulator 26, similarly to the case of the normal preparation TFT, forming a contact hole through the layer, so as to form the source and drain electrodes and the wiring regions 27a ~ 27d (FIG. 4 ( C)).

所得到的TFT的场迁率是,在N沟型为60~120cm2/Vs,在P沟型TFT为50~90cm2/Vs。 Field moved rate of the obtained TFT is in an N-channel type is 60 ~ 120cm2 / Vs, the P-channel type TFT is 50 ~ 90cm2 / Vs. 在用此种TFT制作的移位寄存器中,确认在17V的漏电压,工作在6MHz,在20V漏电压工作在11MHz。 In the production of TFT using such a shift register, it is confirmed in the drain voltage of 17V, working at 6MHz, the drain voltage at 20V at 11MHz.

实施例2图5表示一种制作铝栅TFT的情况,与图4所示相似。 Example 2 Figure 5 shows the case of a method of fabricating an aluminum-gate TFT, similar to that shown in Fig. 4. 然而,在此实施例中,非晶硅被用作有源层。 However, in this embodiment, amorphous silicon is used as the active layer. 如图5(A)所示,在衬底31上淀积一层厚2000~3000的非晶硅膜33。 FIG 5 (A), on the substrate 31 is deposited in a thickness of 2000 ~ 3000 amorphous silicon film 33. 在非晶硅膜中可以混入适量的P型或N型杂质。 In the amorphous silicon film may be incorporated an appropriate amount of a P-type or N-type impurities. 按上所述形成岛状镍或硅化镍涂覆膜34A和34B,在此状态下,在550℃退火8小时,或在600℃退火4小时,使非晶硅膜横向生长而结晶化。 The island is formed by the nickel or nickel silicide coating film 34A and 34B, in this state, annealing at 550 ℃ 8 hours, or four hours at 600 ℃ annealed, the lateral growth of the amorphous silicon film is crystallized.

然后,将如此得到的晶体硅膜构成如图5(B)所示的图形,此时,因为在图中的中部(镍或硅化镍膜34A和34B之间的中间部位)的硅膜含有大量有镍,实施刻图时,要去掉此部位,以形成岛状硅区35A和35B。 Then, the thus obtained crystalline silicon film constituting 5 (B) pattern, this time, since the middle in the figure (nickel or nickel silicide films 34A and 34B between the intermediate portion) of the silicon film contains a large amount nickel, the implementation of patterning, to remove this site to form an island silicon regions 35A and 35B. 然后,在其上再淀积基本上本征的非晶硅膜36。 Then, on which is deposited substantially intrinsic amorphous silicon film 36.

此后,如图5(C)所示,用诸如氮化硅或氧化硅之物质形成一层涂覆膜,作这栅绝缘膜37。 Thereafter, 5 (C), the use of substances such as silicon nitride or silicon oxide coating film layer is formed as shown, for which the gate insulating film 37. 用铝形成栅电极38,再用与图4情况相同的方法实施阳极氧化。 A gate electrode 38 is formed of aluminum, and then with the same method as the case of FIG. 4 anodic oxidation. 然后用离子掺杂方法扩散杂质,以形成杂质区39A和39B。 Then diffusion of the impurity by ion doping method to form impurity regions 39A and 39B. 然后再淀积层间绝缘体40,形成接触孔以及在源的漏区形成金属电极41A和41B,完成TFT。 Then depositing an interlayer insulator 40, a contact hole is formed in the drain region and the source of a metal electrode 41A and 41B, complete TFT. 该TFT的特征在于,在源和漏部位的半导体膜是厚的,其阻抗是小的。 Characterized in that the TFT, the source and drain in the semiconductor film portion is thick, its impedance is small. 其结果,降低了源和漏区的阻抗,改进了TFT的特征。 As a result, reducing the impedance of the source and drain regions, to improve the characteristics of the TFT. 再有,接触可能容易形成接触孔。 Further, exposure may easily form the contact holes.

实施例3图6表示制作CMOS型TFT的工艺过程。 Example 3 Figure 6 shows a process of making a CMOS-type TFT. 如图6(A)所示,在衬底51上淀积一底层氧化硅膜52,再在其上淀积一层厚1000~1500的非晶硅膜53。 FIG. 6 (A), on the substrate 51 is deposited a layer of silicon oxide film 52, and then depositing a layer thickness of the amorphous silicon film 1000 ~ 1500 53 thereon. 然后如上所述,形成岛状镍或硅化镍涂覆膜54,在此状态在550℃实施退火。 Then as described above, nickel or nickel silicide is formed the island-like coating film 54, in this state, annealing at 550 ℃. 硅化镍区55沿涂覆膜的平面方向,而不是厚度方向移位,以此工艺推进结晶化。 Nickel silicide region 55 along the coating film plane direction rather than the thickness direction of displacement, in order to promote the crystallization process. 退火4小时,使非晶硅膜变成如图6(B)所示晶体硅。 Annealing for 4 hours allows the amorphous silicon film becomes 6 (B) crystalline silicon as shown in FIG. 硅化镍区59A和59B随着结晶化的推进被推向边缘。 Nickel silicide region 59A and 59B with the advance of crystallization is pushed to the edge.

将如此得到的晶体硅膜构图形成如图6(B)所示的岛状硅区56。 The thus obtained crystalline silicon film is patterned is formed as shown in Figure 6 (B) shown in the island-like silicon region 56. 这里应特别小心,镍被高度集聚在岛区的两端。 Here should be particularly careful, nickel is highly concentrated at both ends of the island area. 在形成岛状硅区之后,形成栅绝缘膜57以及栅电极58A和58B。 After the formation of the island silicon region, a gate insulating film 57 and the gate electrode 58A and 58B.

然后,用离子掺杂方法扩散杂质形成N型杂质区60A和P型杂质区60B,如图6(C)所示。 Then, an impurity by ion doping method to form an N-type impurity diffusion region 60A and P type impurity region 60B, as shown in Figure 6 (C) in Fig. 此时,可以用磷作为N型杂质(掺杂气体是磷化氢PH3)进行掺杂,用60~110KeV的加速电压使掺杂遍布整个表面,然后用光刻胶覆盖N沟型TFT区,之后再,例如,用硼作为P型杂质(掺杂气体是乙硼烷B2H6),再用40~80KeV的加速电压进行掺杂。 In this case, phosphorus may be used as an N-type impurity (dopant gas is phosphine PH3) is doped with an acceleration voltage of 60 ~ 110KeV allows doping throughout the entire surface, and then covering the N-channel type TFT region with photoresist, After then, for example, using boron as a P-type impurity (dopant gas is diborane B2H6), and then an acceleration voltage of 40 ~ 80KeV be doped.

掺杂后,用类似于图4情况的激光辐照,使源和漏区激活。 After doping, similar to Figure 4 with the case of laser irradiation, so that activation of the source and drain regions. 然后,再淀积层间绝缘体61形成接触孔以及在源和漏区形成金属电极62A、62B和62C,制成TFT。 Then, an interlayer insulator 61 is deposited to form a contact hole and a metal electrode formed in the source and drain regions 62A, 62B and 62C, formed TFT.

实施例4图7表示第四个实施例。 Example 4 Figure 7 shows a fourth embodiment. 本实施例涉及一种方法,其中,用第一次热处理(预退火)使镍膜与非晶硅膜的一部分反应,在去掉未反应的镍膜后,再退火使非晶硅膜化,产生硅化物。 The present embodiment relates to a method in which, with the first heat treatment (pre-annealing) to make part of the reaction of the nickel film and the amorphous silicon film, after removing the unreacted nickel film, and then annealing the amorphous silicon film of, generating silicide.

用溅射法在衬底(Coning No7059)701上形成一底层氧化硅膜702(厚2000)。 A bottom layer is formed by sputtering a silicon oxide film 702 (thickness 2000) on the substrate (Coning No7059) 701. 然后,形成一层厚300~800,例如厚500的硅膜703。 Then, the formation of a thick 300 ~ 800, e.g. 500 thick silicon film 703. 再用等离子CVD法形成一层氧化硅膜704。 Plasma CVD method and then a silicon oxide film 704 is formed. 该氧化硅膜704用作掩膜材料,其厚度优选在500~2000。 The silicon oxide film 704 as a mask material, the thickness thereof is preferably at 500 ~ 2000. 若太薄,因针孔使结晶化从意外的地方展开,若太厚,为形成厚膜要花更多时间,这不适于批量生产。 If too thin, because the pinhole makes crystallized from an unexpected place to start, if too thick, it takes more time to form a thick film, it is not suitable for mass production. 因而这里设在1000。 Thus here in 1000.

之后,用公知的光刻工艺,将氧化硅膜704构图。 Thereafter, by a known photolithography process, the silicon oxide film 704 is patterned. 然后用溅射法形成一层镍膜705(厚500)。 Then forming a layer of nickel film 705 (thickness 500) by sputtering. 镍膜705的厚度最好比100厚[图7(A)]。 The thickness of the nickel film 705 is preferably thicker than 100 [FIG 7 (A)].

然后,使它在氮气气氛内,在250~450℃(一种预退火工艺)退火10~60分钟。 Then, make it in a nitrogen atmosphere at 250 ~ 450 ℃ (a pre-annealing process) Annealing 10 to 60 minutes. 例如,在450℃退火20分钟。 For example, annealing at 450 ℃ 20 minutes. 结果,在非晶硅内形成一层硅化镍706。 As a result, in the nickel silicide layer 706 formed of amorphous silicon. 该层的厚度由预退火的温度和时间决定,而几乎与镍膜的厚度无关(图7(B))。 The thickness of the layer is determined by the pre-annealing temperature and time, and almost nothing to do with the thickness of the nickel film (FIG. 7 (B)).

之后,腐蚀该镍膜。 After that, the corrosion of the nickel film. 硝酸或氢氯酸溶液适用于此腐蚀。 Nitric acid or hydrochloric acid solution applicable to this corrosion. 在用这些腐蚀剂腐蚀镍膜过程中,硅化镍层几乎不被腐蚀。 In these etchant Ni film process, the nickel silicide layer is hardly etched. 在本实施例中,使用一种在硝酸中加入作为缓冲剂的乙酸的腐蚀剂。 In the present embodiment, the use of a buffer of acetic acid was added as an etchant in nitric acid. 其配比是:硝酸∶乙酸∶水=1∶10∶10。 Its ratio is: nitric acid: acetic acid: water = 1:10:10. 在去掉镍膜之后,在550℃退火4~8小时(一种结晶化退火工艺)。 After removing the nickel film, annealing at 550 ℃ 4 to 8 hours (a crystallization annealing process).

在结晶化退火工艺中,试过数种方法。 In crystallization annealing process, tried several methods. 第一种方法,如图7(C)所示,在实施此工艺时,同时保留掩模材料704。 The first method, as shown in Figure 7 (C), in the practice of this process, while preserving the mask material 704. 结晶化按图7(C)箭头所指方向推进。 Crystallization Figure 7 (C) of the arrow forward. 第二种方法是在去掉所有的掩模露出硅膜之后进行退火。 The second method is a mask after removing all the exposed silicon film is annealed. 第三种方法是在去掉掩模材料之后,在硅膜上形成由氧化硅或氮化硅组成的作为保护膜的新的涂覆膜707之后,进行退火,如图7(D)所示。 A third method is to remove the mask after the material is formed by the silicon film composed of silicon oxide or silicon nitride as a protective film after the new coating film 707 is annealed, as shown in Figure 7 (D) in Fig.

虽然第一种方法简单,但掩模材料704的表面在预退火步骤与镍的反应,并在更高温度的结晶化退火工艺中变成硅化物,几乎不能腐蚀。 While the first method is simple, but the surface of the mask material 704 in the pre-annealing step and the reaction of nickel, and at a higher temperature becomes silicide crystallization annealing process, hardly etched. 即,因为硅膜和掩模材料704的腐蚀速率几乎相等,为掩模材料去掉后,硅膜被露出的部位也大量被腐蚀,在衬底上产生台阶。 That is, since the silicon film 704 and the mask material corrosion rate almost equal, the mask material is removed after the silicon film is exposed a large number of parts can also be corrosion, a step is generated on the substrate.

第二种方法很简单,很容易进行腐蚀,因为在结晶化退火工艺之前,掩模材料与镍的反应轻微。 The second method is very simple, it is easy to corrosion, because before crystallization annealing process, the mask material and nickel was mild. 然而,当进行结晶化退火时,硅表面完全被暴露,后来制造的TFT或类似物的特性要变坏。 However, when the crystallization annealing, the silicon surface is exposed completely, then producing a TFT characteristics or the like to deteriorate.

虽然第三种方法可以稳定地得到优质晶体硅膜,但很复杂,因为增加一些工艺过程。 Although the third method can stably obtain high quality crystalline silicon film, but it is complicated, because of the increased number of processes. 至于第四种方法,是第三种方法的一种改型,该方法包括:在硅表面被暴露的状态下,放入一个炉内,先通氧在500~550℃加热大约1小时,以便在表面形成厚20~60的薄氧化硅膜,作为对结晶化退火条件的探讨改为通氮。 As the fourth method, the third method is a modification, the method comprising: in a state of the silicon surface is exposed, placed in a furnace, heated in the first pass oxygen 500 ~ 550 ℃ for about 1 hour, in order to on the surface of a thin silicon oxide film thickness of 20 ~ 60 formation, as crystallization annealing conditions to investigate nitrogen. 根据该方法,在结晶化起始阶段形成氧化膜。 According to this method, at the initial stage of crystallization to form an oxide film. 但在此氧化阶段只在硅化镍膜的附近被结晶化,后来将用作TFT的区(图中右侧部位),没有被结晶化。 However, in the oxidation stage is only crystallized in the vicinity of the nickel silicide film, and later will be used as the TFT regions (right portion), not crystallized. 因此,在远离硅化镍层706的区域硅膜的表面是很平坦的。 Accordingly, in the surface region of the silicon film remote from the nickel silicide layer 706 is very flat. 特性比第二种方法改进许多,与第三种方法几乎相等。 Feature many improvements over the second method, the third method is almost equal.

晶体硅膜是这样得到的。 Crystalline silicon film is thus obtained. 从此以后,将硅膜703构图,同时去掉镍浓度高的部位(设置生长起始区的区域)和生产点(在图中箭头末端的斜线部位),同时只保留镍浓度低的区域。 Since then, the patterned silicon film 703, while a high concentration of nickel to remove a portion (region growing disposed initiation region) and the production points (hatched portion in the figure of the end of the arrow), while retaining only low nickel concentration regions. 按上所述,形成将用于TFT有源层的岛状硅区708。 Press said, will be used to form an island silicon region 708 of a TFT active layer. 然后用等离子CVD形成厚1200由氧化硅构成的栅绝缘膜709,覆盖住区域708。 Is then formed by plasma CVD 1200 thick gate insulating film 709 made of silicon oxide, covering the area 708. 再用厚6000的掺磷硅膜形成栅电极710和第一层的布线711,用栅电极710作掩模,以自对准方式,将杂质注入有源层708,形成源/漏区712。 Then the thick P-doped silicon film 6000 forming a gate electrode wiring 711 and the first layer 710, the gate electrode 710 as a mask, self-aligning manner, the impurity implantation of the active layer 708 to form the source / drain regions 712 . 然后用可见或近红外强光辐照,对改进结晶化是有效的。 Then the visible or near infrared light irradiation, is effective for improving the crystallization. 再用等离子CVD法形成厚6000的氧化硅膜做层间绝缘体713。 And then the plasma CVD method to form a silicon oxide film having a thickness 6000 do interlayer insulator 713. 最后,在层间绝缘体中制出接触孔,再用厚6000的铝膜形成第二布线714、源/漏电极兼布线715。 Finally, an interlayer insulator prepared in contact holes, and then forming an aluminum film thickness 6000 second wiring 714, the source / drain electrodes and a wiring 715. 以上述的工艺完成TFT(图7(E))。 In the above-described process is completed TFT (FIG. 7 (E)).

实施例5图9表示本实施例。 Embodiment 5 Figure 9 shows the present embodiment. 在本实施例中,在TFT型液晶显示装置的有源矩阵区和外围电路中,形成多晶硅TFT。 In the present embodiment, the TFT active matrix type liquid crystal display device and the peripheral circuit region, forming a polysilicon TFT.

首先,在有耐热性质的玻璃衬底如石英玻璃120上,用溅射法,淀积厚20~200nm的一底层氧化膜121。 First, on a 120 heat-resistant properties of glass such as quartz glass substrate by sputtering, depositing a thickness of 20 ~ 200nm underlying oxide film 121. 再用甲硅烷或乙硅烷作原材料,用等离子VCD法或真空CVD法,在其上淀积30~50nm的非晶硅膜。 And then a silyl or disilane as raw materials, with a plasma VCD method or a vacuum CVD method, an amorphous silicon film deposited thereon of 30 ~ 50nm. 这里,氧或氮在非晶硅膜中的浓度低于1018/cm3,最好低于1017/cm3。 Here, oxygen or nitrogen concentration in the amorphous silicon film is less than 1018 / cm3, preferably less than 1017 / cm3. 本实施例中,将氧的浓度设置在低于1017/cm3。 In this embodiment, the oxygen concentration set lower than 1017 / cm3. 用溅射法在非晶硅膜上形成厚100-150nm的氧化硅膜或厚30-100nm的氮化硅膜作为覆盖膜。 Amorphous silicon film by sputtering a silicon oxide film having a thickness of 100-150nm or 30-100nm thick silicon nitride film is formed as the coating film. 然后构图,仅留下外围电路区域的覆盖膜122。 Then patterned, leaving only the cover film 122 of the peripheral circuit region. 然后,在含20-100Vol%的氧或氢的氩成氮的气氛中(600℃)保存4-100小时,使它结晶。 Then, stored in argon containing 20-100Vol% of oxygen or hydrogen to nitrogen atmosphere (600 ℃) 4-100 hours, it crystallized. 结果,外围电路区的硅膜123A的结晶性是好的,而象素区的硅膜123B的结晶性不好。 As a result, the crystalline silicon film of the peripheral circuit region 123A is good, and the crystalline silicon film 123B of the pixel region is not good. 图9(A)示出此状态。 Figure 9 (A) shows this state.

接下来,将硅膜构成如图9(B)所示的用于形成外围电路TFT区124A和用于形成象素TFT区124B的岛状。 Next, the silicon film in FIG. 9 (B) for a peripheral circuit TFT island region 124A and 124B for forming a pixel TFT forming region shown. 然后用溅射法或类似方法形成栅氧化膜125。 Then forming a gate oxide film 125 by a sputtering method or the like. 这可用TEOS(四乙氧硅烷)的等离子CVD法代替溅射法形成。 This can be formed TEOS (tetraethoxysilane) plasma CVD method instead of the sputtering method. 当用TEOS形成该膜时,最好在形成当中或之后,在高于650℃的温度退火0.5-3小时。 When the film is formed using TEOS, preferably during or after the formation, at a temperature higher than 650 ℃ annealed 0.5-3 hours.

在此之后,用LPCVD法形成厚0.2-2μm的N-型硅膜,并将它构成图形,在每个岛区形成栅电极126A-126C。 After that, by LPCVD silicon film having a thickness of 0.2-2μm is N-, and it constitutes patterning to form a gate electrode 126A-126C on each island region. 具有较好耐热性能的金属材料,诸如钽、铬、钛、钨和钼可用来代替。 Metallic material having good heat resistance, such as tantalum, chromium, titanium, tungsten and molybdenum can be used instead.

然后,用栅电极部分作掩模,以自对准方式,用离子掺杂法,把杂质注入每个TFT的岛状硅膜。 Then, using the gate electrode portion as a mask, a self-aligning manner by ion doping, the impurity implantation of the island silicon film of each TFT. 此时,首先采用磷化氢(PH3)作掺杂气体,把磷注入整个表面,然后用光刻胶覆盖图中右侧的岛区124A和矩阵区,之后采用乙硼烷(B2H6)作掺杂气体,把硼注入到左侧的岛区124A。 In this case, first using phosphine (PH3) as the doping gas, flooding the entire surface of the phosphor, and then covered with a photoresist islands 124A and FIG matrix area on the right, after the use of diborane (B2H6) for doping miscellaneous gas, the boron is injected into the left side of the island portion 124A. 磷的剂量设置为2-81015/cm2,而硼的剂量是4-101015/cm3,因此硼的剂量应超过磷的剂量。 The dose of phosphorus is set to 2-8 1015 / cm2, while the boron dose is 4-10 1015 / cm3, so the boron dose should exceed the phosphorus dose. 这样就产生一个P型区127A和N-型区127B及127C。 This produces a P-type region 127A and 127B and N- type region 127C.

在550和750℃间的温度退火2-4小时进行激活它。 Temperatures between 550 and 750 ℃ annealed 2-4 hours to activate it. 本实施例中,在600℃进行热退火24小时。 In this embodiment, the thermal annealing carried out at 600 ℃ 24 hours. 该退火工艺激活了离子注入区。 The annealing process to activate the ion-implanted region.

用激光退火可以完成此工艺。 This can be done with a laser annealing process. 因为用激光退火时,对衬底的热损伤小,所以可以用普通无碱玻璃,例如,Conign7059。 Because the laser annealing, thermal damage of the substrate is small, so you can use ordinary E-glass, for example, Conign7059. 另外,可用耐热性差的材料如铝作栅电极材料。 In addition, poor heat resistance of the available material such as aluminum as the gate electrode material. 按上述的工艺产生了P型区127A及N-型区127B和127C。 The process described above produced a P-type region 127A and N- type region 127B and 127C. 这些区的薄层电阻是200-800Ω/□。 The sheet resistance of these regions are 200-800Ω / □.

此后,用溅射法在整个表面形成厚300-1000nm的氧化硅膜,作为层间绝缘体128。 Thereafter, the entire surface by sputtering in a thickness of 300-1000nm silicon oxide film is formed, as an interlayer insulator 128. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film by plasma CVD method. 用等离子CVD法,特别是用TEOS作原材料,可以得到阶梯覆盖良好的氧化硅膜。 By plasma CVD method, in particular using TEOS as a raw material, a good step coverage can be obtained a silicon oxide film.

然后用溅射法产生一层ITO膜,再构图形成象素电极129。 Then produce a layer by sputtering an ITO film, and then patterned to form the pixel electrode 129. 在TFT源/漏(杂质区)产生接触孔,以形成氮化钛或铬制成的布线130A-130E。 In the TFT source / drain (impurity region) generating contact holes to form wirings 130A-130E made of titanium nitride or chromium. 图9(C)表示用左侧的NTFT和PTFT产生反向器电路。 Figure 9 (C) shows the left-side inverter circuit generating the NTFT and PTFT. 布线130A-130E可以是氮化钛或铬为底层的铝多层布线,以便降低薄层电阻。 Wiring 130A-130E may be titanium nitride or chromium as the underlying aluminum multilayer wiring, in order to reduce sheet resistance. 最后,在氢气中,在200-350℃退火0.5-2小时,以减少硅有源层的悬空键。 Finally, in hydrogen annealing at 200-350 ℃ 0.5-2 hours to reduce the dangling bonds of the silicon active layer. 外围电路和有源矩阵电路可一起集成。 Peripheral circuit and active matrix circuit may be integrated together. 在本实施例中,在外围电路部,典型的迁移率对NMOS为80cm2/Vs,对PMOS为50cm2/Vs,而在象素TFT(NMOS)中,迁移率是5-30cm2/Vs。 In the present embodiment, in the peripheral circuit portion, the typical mobility of NMOS is 80cm2 / V s, on the PMOS of 50cm2 / V s, and the pixel TFT (NMOS), the migration rate is 5-30cm2 / V s.

实施例6图10表示本实施例。 Example 6 Figure 10 shows the present embodiment. 在本实施例中,采用本发明减少CMOS电路中的NMOS和PMOS的迁移率之差。 In the present embodiment, the present invention reduces the difference between the mobilities of the CMOS circuit of the NMOS and PMOS.

首先,用溅射法在Coning7059衬底131上淀积厚20-200nm的底层氧化膜132。 First, 20-200nm thick was deposited by sputtering of the underlying oxide film 132 on the substrate 131 Coning7059. 用甲硅烷或Z硅烷作原材料,用等离子CVD法或真空CVD法,再在其上淀积厚50-250nm的非晶硅膜。 With a silyl or Z silanes as raw materials, with a plasma CVD method or a vacuum CVD method, and then 50-250nm amorphous silicon film deposited thereon thick. 在非晶硅膜中氧或氮的浓度底低于1018/cm3或最好低于1017/cm3。 The concentration of the amorphous silicon film in an oxygen or nitrogen bottom below 1018 / cm3 or preferably less than 1017 / cm3. 为此目的,真空CVD法是适宜的。 For this purpose, the vacuum CVD method is suitable. 本发明中,氧浓度被设置为低于1017/cm3。 The present invention, the oxygen concentration is set to less than 1017 / cm3.

在PMOS区上设置覆盖膜133(厚50-150nm的氧化硅膜)。 PMOS region disposed on the cover film 133 (silicon oxide film thickness of 50-150nm). 然后在氩气或在含50%以上的氧或氢的氮的气氛中,在600℃退火4-100小时使之结晶化。 Then in an argon or nitrogen atmosphere containing 50% or more of oxygen or hydrogen, when annealed at 600 ℃ 4-100 hours for crystallization. 其结果,在覆盖膜之下的区域134A的结晶性虽好,但无覆盖膜的区域134B结晶性却不好。 As a result, under the cover film region 134A of crystallinity is good, but no coating film has poor crystallinity region 134B. 图10(A)表示出此种状态。 Figure 10 (A) shows such a state.

接着,将硅膜构成岛状,以便形成PMOS区135A和NMOS区135B,构图10(B)所示。 Next, the island-like silicon film to form a PMOS region and the NMOS region 135A 135B, composition 10 (B).

然后用溅射法形成厚50-150nm的氧化硅膜125,覆盖这些岛区作为栅绝缘膜136。 Is then formed to a thickness 50-150nm silicon oxide film 125 by sputtering, covering the islands as a gate insulating film 136. 然后用溅射法形成厚0.2-2um的铝膜,并构图形成栅电极。 Then an aluminum film having a thickness of 0.2-2um by sputtering and patterned to form gate electrodes. 在电解液中给它输送电能,在栅电极之上和侧面形成阳极氧化膜。 In the electrolytic solution supplying electric power to it, the anodized film over the gate electrode and the side surface is formed. 用上述的工艺在每个岛状区形成栅电极部分137A和137B。 Using the above process at each of the island-like region is formed the gate electrode portions 137A and 137B.

然后,用离子掺杂法,用栅电极部分作掩膜以自对准方式,将杂质注入每个TFT的岛状硅膜。 Then, by ion doping method, using the gate electrode portion as a mask in a self-aligning manner, the impurity implantation of the island silicon film of each TFT. 此时,首先用磷化氢(PH3)作掺杂气体,把磷注入整个表面,用光刻胶仅覆盖图中的岛区135B,用乙硼烷(B2H6)作掺杂气体,将硼注入岛区135A。 At this time, first as Phosphine (PH3) doping gas, flooding the entire surface of the phosphor, with the photoresist covers only figure Island 135B, as a dopant gas of diborane (B2H6), boron is implanted Island 135A. 磷的剂量设置为2-81015/cm2,硼的剂量设置为4-101015/cm2,以使硼的剂量超过磷的剂量。 The dose of phosphorus is set to 2-8 1015 / cm2, boron dose is set to 4-10 1015 / cm2, so that the boron dose over phosphorus dose.

虽然掺杂过程破坏了硅膜的结晶性,但它的薄层电阻仍可保持在1KΩ/□左右。 Although the doping process destroys the crystalline silicon film, but it can remain in the sheet resistance 1KΩ / □ or so. 然而,若此种程度的薄层电阻还高,再在600℃退火2-4小时,可降下薄层电阻。 However, if such a sheet resistance of higher degree, and then annealed at 600 ℃ 2-4 hours, the sheet resistance can be lowered. 用强光或激光辐照可得到相同效果。 With a light or laser irradiation can be obtained the same effect.

这样就形成了P型区138A和N-型区138B。 Thus forming a P-type region 138A and N- type region 138B. 这些区的薄层电阻为200-800Ω/□。 The sheet resistance of these regions was 200-800Ω / □. 然后用溅射法在整个表面上形成厚300-1000nm的氧化硅膜作层间绝缘体139。 Then by sputtering on the entire surface is formed between 300-1000nm thick silicon oxide film as an insulator layer 139. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film by plasma CVD method. 用等离子CVD方法特别是用TEOS作原材料,可得到阶梯覆盖良好的氧化硅膜。 By plasma CVD method using TEOS as a raw material in particular, a good step coverage can be obtained a silicon oxide film.

然后在TFT的源/漏(杂质区)形成接触孔,以形成铝布线140A-140D。 Then the TFT source / drain (impurity region) forming a contact hole, to form an aluminum wiring 140A-140D. 最后,在氢气中在250-350℃的温度退火2小时,以减少硅膜的悬空键。 Finally, an annealing in a hydrogen atmosphere for 2 hours at a temperature of 250-350 ℃ to reduce the dangling bonds of the silicon film. 用上述工艺得到的TFT的典型迁移率,对PMOS和NMOS均为60cm2/vs。 Typically the mobility of the TFT obtained by the above process, both of PMOS and NMOS 60cm2 / v s. 当用本发明的工艺制作移位寄存器时,证实在20V的漏电压下,工作在10MHz以上。 When the shift register with the production process of the present invention, the confirmed 20V drain voltage, working in more than 10MHz.

实施例7图11表示本实施例。 Example 7 Figure 11 shows the present embodiment. 本实施例涉及晶体管和硅电阻相结合的电路。 This embodiment relates to a silicon transistor and resistor combination circuit. 用杂质掺杂的硅可用作晶体管的保护电路。 With an impurity doped silicon may be used as a protection circuit transistor. 首先,用溅射法在Coning7059衬底140上淀积厚20-200nm的底氧化膜。 First, 20-200nm thick was deposited by sputtering the oxide film on the bottom substrate 140 Coning7059. 在其上,再用等离子CVD法或真空CVD法,以甲硅烷或乙硅烷作原材料,淀积厚100-250nm的非晶硅膜。 Thereon, and then the plasma CVD method or a vacuum CVD method, monosilane or disilane as a raw material, an amorphous silicon film deposited to a thickness 100-250nm. 这里,在非晶硅膜中,氧或氯的浓度层低于1018/cm3,或最好低于1017/cm3。 Here, the amorphous silicon film, the concentration of oxygen or chlorine level is less than 1018 / cm3, or preferably less than 1017 / cm3.

淀积厚20-200nm的氧化硅覆盖143,并在氩或氮的气氛中,在600℃退火4-100小时,使其结晶化。 Silicon oxide deposited to a thickness 20-200nm cover 143, and in an argon or nitrogen atmosphere at 600 ℃ annealing 4-100 hours to allow crystallization. 图11(A)表示出此状态。 Figure 11 (A) shows this state.

下面,将硅膜构成岛状,以形成晶体管区144A和电阻区144B,如图11(B)所示。 Next, the island-like silicon film to form a transistor region 144A and the resistor region 144B, shown in Figure 11 (B). 然后用溅射法形成厚50-150nm的氧化硅膜覆盖那些岛区作栅绝缘膜145。 50-150nm thick silicon oxide film is then formed to cover those islands as a gate insulating film 145 by sputtering. 然后,用溅射法形成厚0.2-2um的铝膜,再构图形成棚电极。 Then, by sputtering an aluminum film having a thickness 0.2-2um, and then patterned to form the shed electrode. 给在电解液内的铝膜输送电能,在栅电极的上部和侧面形成阴极氧化膜。 Aluminum in the electrolyte to transport electrical energy, in the upper and side surfaces of the gate electrode of the cathode oxide film is formed. 用上述的工艺,在每个岛区上,形成栅电极部分146。 Using the above process, on each island region, forming a gate electrode portion 146.

然后,用栅电极部分作掩膜,以自对准方式,用离子掺杂法,把杂质,如磷注入到每个TFT的岛状硅膜。 Then, using the gate electrode portion as a mask, self-aligning manner by ion doping method, an impurity, such as phosphorus implanted into the island silicon film of each TFT. 磷的剂量为2-81015/cm2。 Phosphorus dose of 2-8 1015 / cm2.

用上述的掺杂工艺形成杂质区147A和147B。 Forming an impurity region above the doping process 147A and 147B. 因为相同的杂质量被注入到两个掺杂区,当按照实际的要求热退火时,它们表示出相同的电阻率。 Because the same amount of impurities is injected into the two doped regions which, when annealed according to the actual requirements of heat, which shows the same resistivity. 然而,情况却是,例如当对后者要求较高的电阻时,而前者反倒要求较低的电阻。 However, it is the case, for example when the latter require a higher resistance, the former actually require lower resistance. 然后,仅在晶体管区,如图11(C)所示,形成厚50-150nm的氧化硅覆盖膜148。 Then, only in the transistor region, shown in Figure 11 (C), forming a thick silicon oxide film 148 covering 50-150nm. 然后在含大于50Vol%的氧或氢的氮或氩的气氛中,在550-650℃的温度,退火4-20小时。 Then in an atmosphere containing more than 50Vol% of oxygen or hydrogen in nitrogen or argon, at a temperature of 550-650 ℃, the annealing 4-20 hours. 可用磷化氢代替氧或氢。 Available phosphine instead of oxygen or hydrogen. 然而,退火温度最好低于800℃,因为倘若退火温度太高,磷化氢将被热分解,并扩散到半导体中,反而降低了电阻率。 However, the annealing temperature is preferably below 800 ℃, because if the annealing temperature is too high, the phosphine is thermally decomposed and diffused into the semiconductor, but lower resistivity. 当杂质的电阻区是P-型时,可以用乙硼烷(B2H6)。 When the resistance of the impurity region is a P- type, can be reduced with diborane (B2H6).

用上面的工艺,当晶体管的杂质区的薄层电阻是20-800Ω/□时,电阻的杂质区的薄层电阻是2K-100KΩ/□。 Using the above process, when the sheet resistance of the impurity region of the transistor is 20-800Ω / □, the sheet resistance of the resistance of the impurity region is 2K-100KΩ / □. 用溅射法在整个表面上形成厚300-1000nm的氧化硅膜,作为层间绝缘体149。 By sputtering on the entire surface of the silicon oxide film thickness of 300-1000nm formed, as an interlayer insulator 149. 这可以是用等离子CVD法形成的氧化硅膜。 This may be a silicon oxide film by plasma CVD method. 用等离子CVD法,特别是用TEOS作原材料,可以得到覆盖阶梯良好的氧化硅膜。 By plasma CVD method, in particular using TEOS as a raw material, the step coverage can be obtained excellent silicon oxide film.

在TFT的源/漏(杂质区)形成接触孔,以形成铝布线150A-150C。 In the TFT source / drain (impurity region) forming a contact hole, to form an aluminum wiring 150A-150C. 最后,在氢气中在250-350℃温度退火0.5-2小时。 Finally, an annealing in a hydrogen atmosphere at a temperature of 250-350 ℃ 0.5-2 hours. 以便减少膜悬空键。 Dangling bonds in order to reduce film. 经上述工艺可区分其厚度相同,杂质注入量相同的区域的薄层电阻。 Following the above processes can be distinguished which is the same thickness, the same amount of sheet resistance of impurity implantation region.

如上所述,在某种意义上说,本发明是个划时代的发明,这促进了非晶硅在较低温度和较短时间实现结晶化,并为工业提供不可估量的效益,因为所用的设施、仪器和技术很普通的,而对批量生产则是极为优良的。 As described above, in a sense, the present invention is an epoch-making invention, which promotes the amorphous silicon at lower temperatures and shorter times to achieve crystallization, and for industry inestimable benefit, because the use of the facilities, instruments and techniques are common, while the mass is extremely excellent. 虽然在前述的实施例中,着重对镍进行了解释,而同样的工艺可适用于另一些加速结晶化的金属元素,例如Fe、Co、Ru、Rh、Pd、Os、Ir、Pt、Sc、Ti、V、Cr、Mn、Cu、Zn、Au和Ag中的任一元素。 Although in the foregoing embodiment, focusing on the nickel has been explained, and the same process applied to accelerate the crystallization of other metal elements, such as Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag in any of the elements.

例如,假定处理一片衬底须花两分钟,而在常规固相生长方法中需要15个退火炉,因为至少需要24小时的退火。 For example, assume that processing a substrate to spend a minute or two, but need 15 annealing in conventional solid-phase growth method because it requires at least 24 hours of annealing. 本发明可使退火炉的数减到小于1/6,因为退火时间可缩短到4小时或更短的时间。 The present invention can be reduced to less than 1/6 of the number of the annealing furnace, as the annealing time can be shortened to 4 hours or less. 由于衬底加工成本的下降,以及TFT成本的下降,以此生产率的提高、设备投资的降低以及因此而来的新需求的上升。 Due to lower manufacturing cost of the substrate, and a decline in the cost of TFT, in order to improve productivity, reduce the equipment investment and the consequent rise of new demands. 所以,本发明对工业是很有利的,理所当然地应获得专利。 Therefore, the present invention is very beneficial for industry, of course, should be patented.

另外,本发明以TFT有源层结晶条件的最小改动-有或者无覆盖膜,解决了常规的结晶硅TFT生产工艺中的难题。 Further, the present invention is to minimize changes to a TFT active layer crystallization conditions - with or without a cover film, to solve the conventional crystalline silicon TFT production process problems.

本发明尤其可改进动态电路和具有该电路的装置的可靠性和性能。 In particular, the present invention can improve the reliability and performance of dynamic circuits and devices with this circuit. 一般,虽然对液晶显示的有源矩阵来说,结晶硅TFT的ON/OFF比是低的,并无论如何均难以投入实用,本发明认为这类问题已被解决。 In general, although the active matrix liquid crystal display, the crystalline silicon TFT of the ON / OFF ratio is low, and in any event are difficult to put into practice, the present invention that such problems have been resolved. 虽然未以实施例表明,很清楚,当实施本发明时,将TFT用作实施立体单晶半导体集成电器的装置会是有效的。 Although not showed in Example, it is clear that when practicing the present invention, the TFT is used as the single crystal semiconductor integrated implementation perspective electrical device may be effective.

例如,可用半导体电路知单晶半导体上做成外围逻辑电路,并通过层间绝缘体中介物,在其上设置TFT,来构成存储元件部分。 For example, a semiconductor circuit can be used to make known peripheral logic circuitry on a single crystal semiconductor, and through the intermediary of an interlayer insulator, on which the TFT, to form a memory element portion. 在此情况下,存储元件部分可以是利用本发明的TFT的DRAM电路,而它们驱动电路是由被做成单晶半导体电路的CMOS构成。 In this case, the memory element portion may be a TFT of the present invention is the use of a DRAM circuit, and a driving circuit which is formed by a CMOS circuit constituting the single crystal semiconductor. 再有,当此种电路被用于微处理机时,可节省其面积,因为可把存储器部分在上层制造,认为本发明对工业是很有用的发明。 Further, when such a circuit is used for microprocessor, it can save the area, since the memory can be manufactured in the upper part, that the invention is useful for industrial invention.

虽然参照其优选实施例已特别表示和介绍了本发明,但本领域的技术人员应了解到,在形式和细节上可以进行上述的和其它的改变,仍不应脱离本发明的精神和范畴。 While the reference to its preferred embodiments have been particularly shown and described the invention, those skilled in the art would understand that, in form and details can be and other changes mentioned above, is still to be departing from the spirit and scope of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN100456497C28 Feb 200328 Jan 2009株式会社日立制作所Thin-film semiconductor device, manufacturing method of the same and image display apparatus
International ClassificationH01L21/77, H01L21/336, H01L21/20, H01L21/84
Cooperative ClassificationH01L21/2022, H01L27/1277, G09G2300/0408, H01L29/66757
European ClassificationH01L29/66M6T6F15A2, H01L27/12T, H01L21/20D
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28 May 1997C10Request of examination as to substance
25 Jun 1997C06Publication
2 Oct 2002C14Granted
5 Feb 2014C17Cessation of patent right