CN106449547A - 晶圆级半导体封装件及其制造方法 - Google Patents

晶圆级半导体封装件及其制造方法 Download PDF

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Publication number
CN106449547A
CN106449547A CN201610879713.9A CN201610879713A CN106449547A CN 106449547 A CN106449547 A CN 106449547A CN 201610879713 A CN201610879713 A CN 201610879713A CN 106449547 A CN106449547 A CN 106449547A
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layer
semiconductor package
package part
breakover element
semiconductor
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约翰·R·杭特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提供了一种晶圆级半导体封装件及其制造方法。半导体封装件包括半导体芯片、导通元件、封装体以及上重布层。半导体芯片具有主动面。导通元件位于该半导体芯片周围，且该导通元件具有第一表面及相对于该第一表面的第二表面。封装体包覆部分的该半导体芯片及部分的该导通元件，该封装体具有第三表面及相对该第三表面的第四表面，其中该导通元件突出于该第四表面。上重布层形成于该第一表面及该第三表面，且电性连接该导通元件与该半导体芯片。

Description

晶圆级半导体封装件及其制造方法
本申请是2011年2月22日申请的申请号为201110051621.9，发明名称为“晶圆级半导体封装件及其制造方法”的发明专利申请的分案申请
技术领域
本发明是有关于一种半导体封装件及其制造方法，且特别是有关于一种晶圆级半导体封装件(wafer level semiconductor package)及其制造方法。
背景技术
半导体装置日渐复杂，且半导体装置被要求有更小尺寸及更快的处理速度。为了支持增加的功能，包括此些组件的半导体封装件具有大量的接触垫以作为对外电性连接之用，例如作为输入或输出之用。此些接触垫将占据一半导体封装件的大量的表面积。
在过去，晶圆级封装可能受限于扇入型(fan-in)结构，其中，最终半导体装置封装件的电性触点及其它组件被限制于由半导体装置的周缘所定义的一面积。为了满足接触垫的增加，晶圆级封装不再限制于扇入型结构，而是支持一扇出型(fan-out)结构。例如，在一扇出型结构，此些接触垫可至少部分地位于由半导体装置的周缘所定义的一面积之外。此些接触垫位于一半导体封装件的多面，例如是半导体封装件的顶面及底面。
然而，形成及改善一半导体装置的电性连接方式以增加大量的接触垫可能导致更复杂的工艺。以下描述改善传统技术以发展晶圆级封装件及其制造方法。
发明内容
根据本发明的第一方面，提出一种半导体封装件。半导体封装件包括半导体芯片、导通元件、封装体以及上重布层。半导体芯片具有主动面。导通元件位于该半导体芯片周围，且该导通元件具有第一表面及相对于该第一表面的第二表面。封装体包覆部分的该半导体芯片及部分的该导通元件，该封装体具有第三表面及相对该第三表面的第四表面，其中该导通元件突出于该第四表面。上重布层形成于该第一表面及该第三表面，且电性连接该导通元件与该半导体芯片。
根据本发明的第二方面，提出一种形成方法。形成方法包括以下步骤。提供半导体芯片，该半导体芯片具有主动面及相对于该主动面的背面；形成导通元件邻近于该半导体芯片；以封装体包覆部分的该半导体芯片及部分的该导通元件，其中该导通元件突出于该封装体；以及形成重布层于该封装体上以电性连接该半导体芯片及该导通元件。
为了对本发明的上述及其它方面有更佳的了解，下文特举至少一实施例，并配合附图，作详细说明如下：
附图说明
图1绘示依照本发明的堆栈半导体组件的剖视图。
图2绘示依照本发明一实施例的图1的半导体封装件中A-A面的剖视图。
图3绘示中介层的多种导通孔实施例的剖视图。
图4A至4B绘示依照本发明的一实施例的包括中介层的半导体封装件的局部的剖视图。
图5绘示依照本发明的一实施例的中介层的一底面的示意图。
图6绘示依照本发明一实施例的包括邻近半导体装置的背面的数个导通孔的半导体装置的剖视图。
图7绘示依照本发明的实施例的半导体封装件的上视剖面图。
图8A至图8G绘示依照本发明一实施例的形成半导体封装件的一方法。
主要组件符号说明：
100：堆栈封装组件
102、402、602、702：半导体装置
104：主动面
116、172、472、872：下表面
106、118、173：上表面
108：侧面
111：芯片接合垫
114、714：封装体
130、132、133：介电层
136、137、138、139、146、171：开孔
150、152：图案化导电层
151、153：重布层
170、470、770、870：中介层
174、174A、174B、608、774、874、874A、874B：导通孔
175：封装接合垫
176：上接触垫
190、193、193A、193B：导电凸块
192、194：半导体封装件
202：芯片
275、275A、275B、275C、275D：内导电机制
282：外介电层
440、610：导电机制
500：电阻
502：电感
504：电感
606：背面
800：中介层晶圆
810、820、830：封胶结构
814：黏贴层
832：实质上共面
890：虚线
具体实施方式
请参照图1，其绘示依照本发明的堆栈半导体组件100的剖视图。堆栈半导体组件100包括一半导体封装件192及一半导体封装件194，半导体封装件194位于半导体封装件192之上。半导体封装件194通过数个导电凸块(conductive bump)193电性连接于半导体封装件192。半导体封装件194也可以半导体封装件的任一型式，例如是晶圆级封装件、一BGA封装件及一基板级封装件(substrate-level package)。半导体封装件194可包括一或更多半导体封装件与/或一或更多被动电性组件(passive electrical component)的组合。半导体封装件192包括一半导体装置102，半导体装置102包括一下表面104、一上表面106及侧面108，下表面104于本实施例中一主动面，例如是具有多个接合垫(bond pad)的主动面。侧面108邻近半导体装置102的一周缘(periphery)且延伸于下表面104与上表面106之间。在本实施例中，表面104、106及108中至少一者实质上平面(planar)，侧面108具有相对于下表面104或上表面106实质上垂直的方位，然而表面104、106及108亦可变化成其它实施方面。在一实施例中，上表面106半导体装置102的一背面，而下表面104半导体装置102的一主动面。下表面104包括数个芯片接合垫111，其提供半导体装置102与半导体封装件192的导电结构电性输入及输出之用，导电结构例如是一图案化导电层150(于后续说明)。本实施例中，半导体装置102整合电路(integrated circuit)，然而，一般而言，半导体装置102亦可为任何主动装置(active device)、任何被动装置(passive device)或其组合，主动装置例如是一光学或其它种类的感知器、一微机电系统(MEMS)。半导体装置102可以是主动芯片。即使半导体装置绘示如半导体封装件192，然而其它实施方面中的半导体封装件192可包括超过一个半导体装置。
如图1所示，半导体封装件192亦可包括一封装体114，其邻近半导体装置102设置。本实施例中，封装体114覆盖或包覆部分的半导体装置102及一个或更多之中介层170(于后续说明)的一部分，中介层170例如是数个中介层组件170。封装体114可提供机械稳定性(mechanical stability)及抵抗氧化、湿度及其它环境条件的保护。本实施例中，封装体114实质上覆盖上表面106及半导体装置102的侧面108，且半导体装置102的下表面104实质上曝露出来或未被封装体114覆盖。封装体114包括一下表面116及一上表面118。本实施例中，下表面116与上表面118中每一者实质上平面，然而下表面116与上表面118亦可变化为其它实施方面。
在一实施例中，封装体114可由一封装材料(molding material)形成。该封装材料可包括酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或其它适当的包覆剂。该封装材料亦可包括适当的填充剂(filler)，例如是粉状的二氧化硅。该封装材料可以是预浸渍材料(pre-impregnated(prepreg)material)，例如是预浸渍介电材料。
半导体封装件192更包括一个或更多中介层170。中介层170可邻近半导体装置102的一周缘177(例如是侧周缘，如图2所示)。中介层170可以是接触式中介层(contiguousinterposer)，其环绕半导体芯片(如图7所示)的周缘177延伸或如图2所示的非接触式分离之中介层组件。每个中介层170包含一基板材料，例如是玻璃、硅(silicon)、金属、金属合金、聚合物(polymer)或另一适当结构材料所形成。半导体封装件192之中介层170可由相同材质或不同材质所形成。在一实施例中，每个中介层170可定义一个或更多开孔171，其从中介层170的下表面172伸至中介层170的上表面173。一导通孔174形成于每个开孔171。
如第1及2图所示，中介层170可包括数个导通孔174。在一实施例中，导通孔174A形成于每个开孔171且可从下表面172及上表面173露出。在另一实施例中，导通孔174B可突出超过下表面172及上表面173。导通孔的其它实施例绘示于图3。导通孔174可直接地连接于图案化导电层150。导通孔174可包括一内导电机制(inner conductive interconnect)275。内导电机制275一电性组件，其可由金属材料形成，传统上以电镀、电性贴附(conductive paste)或其它本技术领域熟知此技艺者所知道的方法完成。视中介层170的介电层282的基板材料而定，导通孔174可包括介电材料的一外介电层282，其形成于内导电机制275与基板271(如第2及3图所示)之间。外介电层282可以是环状介电质的形式。
在一实施例中，导通孔174的直径可以介于10微米(μm)与50μm之间，例如是从约10μm至约20μm之间及从约20μm至约50μm之间。对于直径介于约10μm至约20μm的导通孔174，导通孔174B的结构可被使用。对于直径介于约20μm至约50μm的导通孔174，导通孔174A的结构可被使用。
封装件192可包括一或更多重布层(RDL)151，每个RDL包括图案化导电层150及一介电层(或保护层)130。图案化导电层可由铜、铜合金或其它金属形成。重布层151可邻近(例如是设于、接近于或连接于)半导体装置102的主动面104及封装体114的下表面116设置。重布层151可仅包括图案化导电层150或可以是多层(multi-layered)结构。例如，除了介电层130及图案化导电层150外，重布层151可包括一介电层130，使图案化导电层150设于介电层130与131之间。然于其它实施例中，可使用更多或更少的介电层。介电层130与131中每一者可由介电材料所形成，该介电材料聚合体或非聚合体。例如，介电层130与131中至少一者可由聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole，PBO)、苯环丁烯(benzocyclobutene)或其组合所形成。介电层130与131可由相同或不同介电材质所形成。于一实施例中，介电层130与131中至少一者可由介电材料所形成，该介电材料光成像性(photoimageable)或感旋光性(photoactive)。当图案化使用微影工艺(photolithography)。
图案化导电层150可经由介电层130的开孔136延伸至电性连接于导通孔174，且经由介电层130的开孔146电性连接于接合垫111。用以电性连接堆栈封装组件100的外部的封装接合垫175可由部分的图案化导电层150所形成，部分的图案化导电层150从介电层130的开孔137露出。
在一实施例中，半导体封装件192可提供一二维扇出型结构，其图案化导电层150实质上侧向地延伸至半导体装置102的一周缘177(如图2所示)之外。例如，图1绘示电性触点(electrical contact)，其包括导电凸块190，至少部分地半导体装置102的侧周缘(lateral periphery)177(如图2所示)之外。导电凸块190可从封装件192的一下周缘195露出。此允许半导体封装件192通过重布层151及导电凸块190电性连接至半导体封装件192的外部的装置。导电凸块190可通过图案化导电层150电性连接于半导体装置102且邻近封装接触垫175设置。导电凸块190通过图案化导电层150可电性连接于中介层170。
中介层层170包含导通孔174，经由提供从半导体装置102到包括导电凸块193的电性触点之间的电性路径，导通孔174容易地从二维扇出结构延伸至三维扇出及/或扇入结构。导电凸块193可从封装件192的上周缘196延伸。此允许半导体封装件192通过重布层153及导电凸块193电性连接至半导体封装件192的外部的装置。导电凸块193可电性连接至上接触垫176。上接触垫176由图案化导电层152的一部分所构成，重布层153包括图案化导电层152且邻近封装体114的上表面设置。图案化导电层152可设于介电层(或保护层)132与介电层133之间。图案化导电层152可经过介电层132的开孔139延伸至电性连接于导通孔174。上接触垫176由图案化导电层152中从介电层133的开孔138曝露出的部分所构成。重布层153可具有与前面描述的重布层152相似的结构特征。
在一实施例中，重布层153可不包括介电层132，使图案化导电层152及介电层133可邻近封装体114的上表面118设置。本实施例中，图案化导电层152亦可邻近中介层170，如此，在此实施例中，中介层170应由非导电材料制成，例如是玻璃。有利地，只要图案化导电层152邻近中介层170的非导电部分，中介层170可包括第一部分及第二部分，第一部份由例如是硅(silicon)的材质所形成，而第二部分由例如是玻璃或其它介电材料的非导电材料所形成。
在一实施例中，经由通过图案化导电层152、导通孔174及图案化导电层150电性连接导电凸块193A与半导体装置102，可制出三维扇出结构。有利地或此外，一三维扇入结构过导电凸块193B经由图案化导电层152、导通孔174及图案化导电层150电性连接于半导体装置102而建立。此些三维扇入及/或扇出。相较于二维扇出结构，三维扇出及/或扇入结构大幅地增加对封装体114的上表面的上以及封装体114的下表面116之下的电性触点在配置及分隔上的灵活性。如此可降低对半导体装置102的接触垫在配置与分隔上的依赖性。依照具有一扇出结构，导电凸块193A侧向地设于半导体装置102的周缘之外的至少一部分，依照一扇入结构，导电凸块193A侧向地至少设于半导体封装件102的周缘。一般来讲导电凸块190及193亦可设于周缘以内、周缘以外侧或周缘的内外，使封装件100可具有一扇出结构、一扇入结构或一扇出结构与一扇入结构的组合。本实施例中，导电凸块190及193可以是锡凸块(solder bump)，例如是回焊后的焊球(solder ball)。
图案化导电层150、导通孔174及图案化导电层152可由例如是金属合金、具有金属或散布的金属合金的基体(matrix)或适当的导电材料。例如，图案化导电层150、导通孔174与图案化导电层152中至少一者可由铝、铜、钛或其组合所形成。图案化导电层150、导通孔174与图案化导电层152可由相同或不同的导电材质形成。
图2绘示图1半导体封装件192的A-A面的剖视图。根据本发明一实施例，剖视图绘示分离之中介层组件170，其设于半导体芯片102及封装体114的四侧的每者。分离之中介层组件170可从封装体114的一侧周缘115往内设置。封装体114可环绕每个中介层170的一侧周缘178延伸，以使每个中介层170的一侧周缘178埋入封装体114。此外，内导电机制275及外介电层282邻近同一实施例的内导电机制275设置。外介电层282可环状介电质的形式。内导电机制275可由类似于形成部分的导通孔174的导电材料所形成，如描述图1时所述。外介电层282可由类似于形成介电层130及131的材料所形成，如描述图1时所述。剖视图亦显示芯片102的上表面106。在此实施例中，不使用的导通孔174可保留不电性连接。
分离之中介层组件170可以切割自中介晶圆(interposer wafer)，依据任一半导体封装件(如图8B所示)所需的贯孔连接(through via connection)的数量及位置，使中介层组件170具有多种尺寸及外形。此提供了从同一中介晶圆中取得具有不同贯孔连接的数量及位置的多种封装件的制造弹性。此外，中介层组件170可形成对应每种封装类型的尺寸，使得未使用的贯孔连接减少或消除。因为没有需求，例如，形成每一封装类型的一客制化基板去降低未使用的基板面积，故此方法可降低制造成本及复杂度。
此外，因为分离之中介层组件170相对封装体114可以是小的，因此分离之中介层组件170对封装件192的热膨胀系数(CTE)小的或不影响。反而，封装体114的热膨胀系数可调整与半导体装置102的热膨胀系数较佳配合，以增加可靠度。例如，用以形成封装体114的封胶的填入物(filler content)可被调整至使封装体114的热膨胀系数更接近半导体装置102的热膨胀系数。
图3绘示中介层组件170内的多种导通孔实施例的剖视图。在一实施例中，中介层组件170定义开孔171且包括导通孔174A，导通孔174A至少部分地设于开孔171内，其中导通孔174A包括内导电机制275A。导通孔174A可以是硅穿孔(through silicon via,TSV)。导通孔174A包括内导电机制275A及外介电层282，导电机制275A从中介层组件170的上表面173及下表面172露出，外介电层282环绕内导电机制275A。外介电层282可邻近开孔171的一侧面381设置。在此实施例中，外介电层282及内导电机制275A可实质上填满开孔171。
在另一实施例中，导通孔174B包括一内导电机制275B，其突出超过中介层170的上表面173及下表面172。在此实施例中，外介电层282亦可突出超过上表面173及下表面172。一导通层(conductive layer)383可邻近内导电机制275B及外介电层282的突出部分设置。
在其它实施例中，一导通孔174C包括一内导电机制275C及外介电层282，内导电机制275C环状电镀层。内导电机制275C可定义一开孔384。此外，内导电机制275C可被一内介电层(未绘示)填满。
在其它实施例中，一导通孔174D包括一内导电机制275D。内导电机制275D直接地邻近中介层组件170的基板271设置。在此实施例中，中介层组件170由非导电材料制成，非导电材料例如是玻璃。内导电机制275D可定义相似于开孔384的一开孔(未绘示)。
在其它实施例中，导通孔174A、174B、174C及174D相似于导通孔174且执行相似的从顶部封装件194至底部封装件192及至导电凸块190以分配封装件100的外部的I/O至其它装置(如图1所示)的绕线I/O功能。
中介层170的实施例提供邻近于半导体封装件的上表面的重布层(例如是图1的重布层153)与邻近于半导体封装件的下表面的重布层(例如是图1的重布层151)之间的电性连接性的优点，可导致导通孔直径的降低。例如，导通孔174可具有一介于约10微米(μm)与50μm之间的直径，例如是从约10μm至约20μm之间、从约20μm至约30μm之间，或从约30μm至约50μm之间。此直径小于传统的硅穿孔的直径(大于75μm)，其可以激光钻孔穿过封胶而形成。因为导通孔174的直径降低，对应的撷取焊垫(capture pad)，例如是图1的图案化导电层150及152的一部分可降低尺寸及间距。如此导致较高密度的重布绕线(redistributionrouting traces)的空间，例如是芯片102与中介层170之间的空间，且于执行绕线(routing)时不用增加额外的重布层。相较于以激光穿过封胶而钻出尺寸较大的导通孔，每个导通孔174的较小直径可允许较高的连接密度。此外，由于较小直径，导通孔280可更快地被导电及/或非导电材质填满，以避免例如是处理器的问题(processor solution)、聚合物泄漏及诱捕(entrapment)等不受欢迎的问题。
图4A至4B绘示依照本发明的一实施例的包括中介层470的半导体封装件400的局部的剖视图。半导体封装件400及中介层470相似于图1的半导体封装件192及中介层170，除了中介层470包括一导电机制440之外。如图4A所示，在半导体封装件400A的一实施例中，导电机制440可设置于且沿中介层470A的下表面472A实质上侧向地延伸。在此实施例中，一介电层441设于导电机制440与中介层470A的基板271之间。如图4A所示，在半导体封装件400A的一实施例中，导电机制440可设于且沿中介层470B的一下表面472B实质上侧向地延伸。在此实施例中，导电机制440邻近于中介层470B的基板271，如此中介层470B应由非导电材料制成，例如是玻璃。有利地，只要导电机制440邻近中介层470B的非导电部分，中介层470B可包括一第一部分及一第二部分，第一部份由例如是硅(silicon)的材质所形成，而第二部分由例如是玻璃或其它介电材料的非导电材料所形成。
导电机制440的一优点导电机制440可做为重布绕线的额外走线层，其可降低半导体封装件400的重布层的数量。半导体封装件400的重布层的数量的降低，可降低制造复杂性及制造成本。此外，由于导电机制440可被重布层埋入，因此不会占用半导体封装件402的一外表面的空间。
在图4A及4B的实施例中，一半导体装置(例如是图1的半导体装置102)通过图案化导电层150电性连接于上重布层153，图案化导电层150包括一下重布层151、导电机制440及中介层组件470的导通孔174。下重布层151可覆盖导电机制440。另外，一保护层(未绘示)可设于导电机制440与下重布层151之间。在一实施例中，导电机制440可电性连接半导体装置102至一被动电性组件(如图5所示)。
如图4B所示，在一实施例中，介电层132(如图1所示)可省略上重布层153，使图案化导电层152邻近中介层470B的基板271设置。在本实施例中，中介层470B由非导电材料制成，非导电材料例如是玻璃。
图5绘示。图5绘示依照本发明的一实施例的中介层470的底面的示意图。中介层470包括数个导通孔174(例如是导通孔174A及174E)及数个导电机制440。导电机制440可形成一绕线层。在一实施例中，绕线层在中介层470的下表面。导电机制440可连接导通孔174D至导通孔174E。在一实施例中，尽管导通孔174B可提供电性连接于图案化导电层，例如是图案化导电层150，导通孔174D可通过一半导体封装件提供电性连接，该半导体封装件例如是图4A及4B的半导体封装件400。在经由绕线横跨中介层470至中介层470的一表面的过程中，重布层绕线，导通孔440可允许横跨导体上方。
在一实施例中，导电机制440可电性连接于导通孔174至一或多个本技术领域中习知技艺的一已知的被动电性组件，例如是电阻500、电感502及电容504。此些被动电性组件设于中介层470的下表面472，如同导电机制440。
图6绘示依照本发明一实施例的包括邻近半导体装置602的背面606露出的数个导通孔608的半导体装置602的剖视图。半导体装置602大部分相似于图1的半导体装置102，除了导通孔608之外。导通孔608相似于导通孔174。导通孔608的一优点导通孔608形成于半导体装置602。如此可降低或消除分离之中介层的需求，其可节省半导体封装件的空间，例如是节省图1的半导体封装件192的空间。在一实施例中，导通孔608可电性连接于半导体装置602与重布层，例如是图1的重布层153。导通孔608可电性连接一芯片接合垫611至半导体装置602的外部的电路，例如重布层153的导电层152(如图1所示)。此外，导通孔608可电性连接半导体装置602内的电路610至导体装置602外的电路，例如是重布层153的导电层152。
图7绘示依照本发明的实施例的半导体封装件700的上视剖面图。该剖视图绘示中介层770环绕封装体714，封装体714包覆半导体装置102。该剖视图绘示中介层770的导通孔774。半导体封装件700大部分相似于如描述图1时所述的半导体封装件192，除了中介层770的外形。在本实施例中，中介层770接触中介层，其环绕半导体芯片102的侧周缘177延伸。特别地，导通孔774及封装体714相似于如图1所示的导通孔174及封装体114。
中介层770定义一开孔772，开孔772实质上被封装体714填满。封装体714可减低或吸收(decouple)中介层770对半导体封装件700作用的应力。在此实施例，未使用的导通孔774可维持未电性连接。
图8A至图8G绘示依照本发明一实施例的形成一半导体封装件的一制造方法。为不使说明清楚，以下以图1的封装件192描述制造过程。然而，制造方法亦可应用于与封装件192不同的半导体封装件。此外，制造方法可应用于连接数个半导体封装件的一数组，可应用例如是切割(singulation)以形成多个分离的半导体封装件。
图8A绘示一中介层晶圆(或中介层面板(interposer panel))800。中介层晶圆800可由玻璃、硅、金属、金属合金、聚合物或另一适当的结构材料所形成。中介层晶圆800包括导通孔804，其相似于图1至3的导通孔174及导通孔280。在一实施例中，导通孔804可整个延伸经过中介层晶圆800，且可突出超过一中介层870。中介层870可以是一分离、非接触之中介层组件。有利地，导通孔804可曝露于中介层晶圆800的下表面806，但仅部分地延伸经过中介层晶圆800。中介层晶圆800的外形可以是圆形、矩形、正方形或任何本技术领域熟知此技艺者以可行制造方法所决定的外形。
接着，图8B绘示中介层870。中介层870可例如经由包含本技术领域熟知此技艺者所知晓的切割方法，例如是锯切割(saw singulation)，与中介层晶圆800隔离。分离中介层870与中介层晶圆800的一优点，可使用一标准尺寸之中介层晶圆或面板800。可依据任何已知半导体封装件对导通孔的数量及位置的需求，切割中介层晶圆800成为多种尺寸及外形的数个中介层。导通孔804可整个延伸经过中介层870，且可突出超过中介层870。有利地，如图8A所述之中介层晶圆800及导通孔804可仅部分地延伸经过中介层870。
然后，图8C绘示封胶结构810。在一实施例中，芯片102及一或多个中介层870，该些中介层870邻近载板812设置。有利地，使用商业上可利用的拿取(pick)及放置(place)及/或芯片设置设备，芯片102及中介层870放置或定位于在载板上。芯片102及中介层870可经由黏贴层814设置于载板812。在一实施例中，中介层870包括一导通孔874A，其从中介层870的下表面872露出。在另一实施例中，中介层870包括一导通孔874B，其突出超过下表面872至黏贴层814。然后，芯片102及中介层870被封胶材料(molding material)包覆以形成封胶结构810。封装材料可环绕中介层870的一侧周缘878。封胶结构810由相似于形成图1的封装114的材料所形成。封胶结构810可经由使用数种封装方法中任一种形成，例如是转注成型(transfer molding)、注射成型(injection molding)。或压缩成型(compressionmolding)。为了使封胶结构810在后续的切割步骤中在定位上更适当，可通过多种方法，例如是激光标记形成定位标记(fiducial mark)于封胶结构810。
接着，图8D绘示封胶结构820。封胶结构820以下步骤形成：首先，从图8C的载板820上移除封胶结构810；然后，邻近芯片102的主动面104、封装体817的下表面816及每个中介层870的下表面872形成一重布层包括重布层151(如图1所示)。可经由数种技术形成一介电材料，该些技术例如是印刷(printing)、旋涂(spinning)或喷涂(spraying)，然后图案化形成一介电层130(如图1所示)。图案化后，形成具有数个开孔的介电层130，该些开孔包括对齐主动面104及形成至少部分地曝露半导体封装件102的芯片接合垫111的尺寸的开孔。在一实施例中，介电层更更包括数个开孔，其对齐且形成至少部分地曝露导通孔874A的尺寸。在另一实施例中，介电层包括数个开孔，导通孔874B延伸通过该开孔。形成介电层130而对介电材料的图案化可应用数种方法的任一种完成，例如微影工艺(photolithography)、化学蚀刻(chemical etching)、激光钻孔(laser drilling)或机械钻孔(mechanicaldrilling)。且形成的开口可具有数种外形的任一种，例如是柱形或非柱形，柱形例如是圆形柱(circular cylindrical shape)、椭圆形柱(elliptic cylindrical shape)、方形柱(square cylindrical shape)或矩形柱(rectangular cylindrical shape)，而非柱形例如是锥形(cone)、漏斗(funnel)或另一锥形。开口的侧面边界亦可考虑呈曲形(curved)或粗糙结构(roughly textured)。
接着使用数种技术的任一种涂布一电性导电材料于介电层130且到达被介电层130定义的该些开孔，该些技术例如是化学气相沈积、无电镀法(electroless plating)、电解电镀(electrolytic plating)、印刷、旋涂、喷涂、溅镀(sputtering)或真空沈积法(vacuum deposition)。接着，图案化电性导电材料以形成包括图案化导电层150(如图1所示)的电性导电层。图案化之后，图案化导电层150、沿介电层130的特定方向侧向地延伸的电性机制与曝露出介电层130的其它部分的数个电性机制之间的间距(gap)一起形成。包含于重布层151的图案化导电层150可电性连接至芯片接合垫111及导通孔874。电性导电层150的图案化可由数种方法的任一种完成，该些方法包括微影工艺(photolithography)、化学蚀刻(chemical etching)、激光钻孔(laser drilling)或机械钻孔(mechanicaldrilling)。
接着使用数种技术的任一种涂布介电材料于图案化导电层150上，该些技术例如是印刷、旋涂或喷涂。然后，图案化介电材料以形成包括介电层131(如图1所示)的介电层。图案化后，形成具有数个开孔的介电层130，该些开孔对齐电性导电层150且包括对齐以至少部分地曝露出电性导电层150且形成以容纳锡焊凸块(solder bump)的尺寸的开孔。介电层131的图案化可应用数种方法的任一种完成，例如微影工艺、化学蚀刻、激光钻孔或机械钻孔。且形成的开口可具有数种外形的任一种，例如是柱形或非柱形，柱形例如是圆形柱、椭圆形柱、方形柱或矩形柱，而非柱形例如是锥形、漏斗或另一锥形。开口的侧面边界亦可考虑呈曲形或粗糙结构。
然后，图8E绘示封胶结构830。在一实施例中，移除中介层870的一部分以形成中介层170及封胶结构的一部分。传统上经由背面磨削(backgrinding)、化学平面研磨(CMP)或其它产生一实质上共面832的技术。
在图8E、8F的另一实施例中绘示一封装结构840。除了执行额外的背面磨削或其它移除技术以露出半导体芯片602的背面606而导致芯片602、封装体114及中介层170之间的一实质上共面836外，封装结构840相似于图8E的封装结构830。在一实施例中，若芯片对应于图6的芯片602，足够的封胶结构被移除以曝露芯片602的背面606及导电机制610(如图6所示)。
然后，图8G绘示图2的半导体封装件192。为了形成半导体封装件192，邻近封胶结构830(如图8E所示)的上表面832形成重布层153。重布层153的形成相似于重布层151，且重布层153电性连接于导电机制174。在一实施例中，接着沿虚线890执行切割，以分离该些半导体封装件192。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (13)

1.一种半导体封装件，包括：
半导体芯片，具有主动面；
导通元件，位于该半导体芯片周围，且该导通元件具有第一表面及相对于该第一表面的第二表面；
封装体，包覆部分的该半导体芯片及部分的该导通元件，该封装体具有第三表面及相对该第三表面的第四表面，其中该导通元件突出于该第四表面；以及
上重布层，形成于该第一表面及该第三表面，且电性连接该导通元件与该半导体芯片。
2.如权利要求1所述的半导体封装件，其中该第一表面及该第三表面形成一共平面。
3.如权利要求1所述的半导体封装件，其中更包括一装置电性连接该上重布层。
4.如权利要求1所述的半导体封装件，其中该导通元件的直径介于10微米至50微米。
5.如权利要求1所述的半导体封装件，其中该导通元件包含选自铝、铜、钛及其组合之材料。
6.如权利要求1所述的半导体封装件，其中更包括介电层位于该第四表面上，且包围该突出部。
7.如权利要求6所述的半导体封装件，更包括下重布层，形成于该介电层上，且电性连接该导通元件与该半导体芯片。
8.如权利要求1所述的半导体封装件，其中该导通元件包含基板材料。
9.如权利要求8所述的半导体封装件，其中该基板材料包括金属、聚合物、金属合金、玻璃或硅。
10.如权利要求8所述的半导体封装件，其中该导通元件包括内导电机制及外介电层，该外介电层环绕该内导电机制，并位于该中介层元件的该基板材料与该内导电机制之间，使该内导电机制不与该封装体直接接触。
11.一种半导体封装件的形成方法，包括：
提供半导体芯片，该半导体芯片具有主动面及相对于该主动面的背面；
形成导通元件邻近于该半导体芯片；
以封装体包覆部分的该半导体芯片及部分的该导通元件，其中该导通元件突出于该封装体；以及
形成重布层于该封装体上以电性连接该半导体芯片及该导通元件。
12.如权利要求11所述的形成方法，更包括：
形成介电层于该封装体上，该介电层包围该突出部。
13.如权利要求12所述的形成方法，其中该重布层形成于该介电层上且电性连接该半导体芯片与该导通元件。
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