CN1061191C - Real-time two-dimention discrete cosine conversion/anti-discrete cosine conversion circuit device - Google Patents
Real-time two-dimention discrete cosine conversion/anti-discrete cosine conversion circuit device Download PDFInfo
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- CN1061191C CN1061191C CN95105094A CN95105094A CN1061191C CN 1061191 C CN1061191 C CN 1061191C CN 95105094 A CN95105094 A CN 95105094A CN 95105094 A CN95105094 A CN 95105094A CN 1061191 C CN1061191 C CN 1061191C
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Abstract
The present invention relates to a real-time two-dimensional discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) circuit which comprises a group of variable-velocity dual-port buffer devices, a selecting device, a group of one-dimensional DCT/TDCT arithmetic devices, a row-column transform buffer device and an inverse variable-velocity dual-port buffer device. Data is input into a real-time DCT/IDCT circuit by a first velocity, after the DCT/IDCT calculation of a second velocity is finished, the data is output according to the first velocity, wherein the second velocity is double of the first velocity.
Description
The invention relates to digital signal processing device, particularly relevant for a kind of real-time (real time) 2-D discrete cosine conversion (Dis-crete Cosine Transform that is applicable to ultra-large type integrated circuit VLSI, below be generally called DCT)/anti-discrete cosine conversion (InverseDiscrete Cosine Transform below is generally called IDCT) circuit arrangement.
DCT/IDCT belongs to one of quadrature (orthogonal) switch technology.Because of it has high conversion rate, often apply in the systems such as image compression and bandwidth of video signal compression, in order to the work of treatment conversion coding.It is by by a two-dimensional dct arithmetic unit, and with the digitized video unit (element) or pixel (pixel) data of a block (block), (the discrete cosine matrix of N * N) for example makes the image data of time domain be converted to the data of frequency domain to be multiplied by one group of two dimension.Decoding end needs in addition with the reduction of data of IDCT with frequency domain thus.
Because two-dimensional dct/IDCT has been applied in some international vision signals or the image processing standard, for example JPEG, H.261 with MPEG etc., and become indispensable major part in this class standard, play the part of the pivotal player of developer, comprise hd-tv (HDTV), advanced television (ATV) and vision signal phone (Visdeo comference) etc. with the vision signal product.Therefore, how the operation efficiency with DCT/IDCT promotes, and actual disposition has become an important topic in integrated circuit.
Because real-time effect is stressed in transmission, computing and the broadcast of video signal data, particularly above-mentioned commercial vision signal product is particularly like this.Circuit part as the DCT/IDCT calculation function, it satisfies the high efficiency utilization except need, outside the real-time processing data, more must simplify circuit as far as possible and form, reach the purpose of fast operation with minimum hardware configuration, and meet the requirement of ultra-large type integrated circuit really.
Real-time two-dimensional dct/idct circuit structure in the past, for keeping the continuity of data operation, make next-door neighbour's block be able to continuous computing, all adopt the series connection of two groups of one dimension DCT/IDCT circuit or directly finish with one group of two-dimensional dct/idct circuit, make whole change-over circuit quite numerous and jumbled, need a large amount of hardware configuration, against in the manufacturing principle of integrated circuit high-density multifunction; Some is with one group of one dimension DCT/IDCT circuit, relies on feedback system to satisfy the demand of two-dimensional transformations, but can't gain to some extent on efficient, and can not reach the purpose of instant conversion.
Structure shown in Figure 1 is the two-dimensional dct/idct circuit that in the past utilizes two groups of one dimension DCT/IDCT series connection to form.Wherein, one-dimensional discrete cosine translation operation device (1D DCT/IDCTprocessor) 15 and 17 carries out the DCT computing to the row (or row) of input data matrix respectively, and the conversion buffered device of ranks (Transpose buffer) 16 and 18 then is responsible for the data matrix is done ranks conversion (transpose) computing.Therefore after two-dimensional data matrix X input structure shown in Figure 1, earlier row (or row) is wherein done one dimension DCT computing, procession conversion then, making becomes transposed matrix Z.Then input matrix Z to remaining one dimension, promptly with respect to the row (or row) of Z, does one dimension DCT computing, ranks conversion is returned at last again, and becomes matrix Y output.
In this two-dimensional dct conversion equipment, one dimension DCT arithmetic unit 15 and 17 circuit structure be more than conversion buffered device 16 of ranks and 18 complexity, and generally speaking, the former required hardware group is into about being ten times of the latter.And the function of two groups of one dimension DCT arithmetic units is identical as shown in the above description, and so configuration causes waste to hardware resource undoubtedly.
Moreover, if only directly handle the computing that above-mentioned district is converted to Y with one group of two-dimensional dct arithmetic unit, huge by its data volume, its required circuit complexity are ought more above-mentioned one group of DCT arithmetic unit much higher, also do not meet the seek quickness requirement of refinement of integrated circuit.
Therefore, main purpose of the present invention is to provide a kind of real-time two-dimensional dct/idct circuit device, satisfies the requirement of high-speed computation with the circuit structure of simplifying most, and saves the hardware composition.
Above order of the present invention is by finishing with lower device:
A kind of real-time 2-D discrete cosine conversion (to call DCT in the following text)/anti-discrete cosine conversion (to call IDCT in the following text) circuit comprises:
One variable Rate dual-port buffer unit writes with a first rate in order to the block with one group of two dimension N * N word (word) size, after adjusting this block, exports one first one dimension data with one second speed;
One choice device, have two input ports, the one input end mouth described variable Rate dual-port buffer unit that is coupled providing the circulation of this first one-dimensional data in the cycle very first time, and provides the one second one-dimensional data circulation from another input port in one second time cycle;
One one dimension DCT/IDCT arithmetic unit, the described choice device that is coupled carries out the DCT/IDCT computing in order to the described one-dimensional data that this choice device is provided;
The conversion buffered device of one ranks, the described DCT/IDCT arithmetic unit that is coupled is in order to forming described second one-dimensional data and be supplied to this choice device through this first one-dimensional data ranks conversion of DCT/IDCT computing; And
One contravariant speed dual-port buffer unit, the described DCT/IDCT arithmetic unit that is coupled will be in order to exporting with described first rate through described second one-dimensional data of DCT/IDCT computing.
In the said apparatus, described second speed can be two times of described first rate;
The data throughput rate of described one dimension DCT/IDCT arithmetic unit (throughput rate) can be more than or equal to described variable Rate dual-port buffer unit, and can finish the DCT/IDCT computing of the one-dimensional data of one group of N word in 2N-1 the execution cycle based on described second speed;
Described variable Rate dual-port buffer unit can be a dual-port sram device;
Described variable Rate dual-port buffer unit can be controlled its input and output operation with the pulse of two different rates respectively; The two counter addressing that described variable Rate dual-port buffer unit also can utilize the pulse of different rates to control are to produce the I/O operation of described first rate and described second speed; Described variable Rate dual-port buffering can also be utilized the arrangement of addressing signal line and adjust described input block piece, produces the effect of ranks reorganization.
Above-mentioned variable Rate dual-port buffer unit is because of exporting its input data by double-speed, and addressing is carried out in output on demand in proper order, cooperation can be finished the one dimension DCT/IDCT arithmetic unit of the DCT/IDCT computing of one group of one dimension N input in 2N-1 execution cycle (latency), and satisfy the condition of real-time operation, and with each better simply nextport hardware component NextPort, reduce extra winding space, significantly save hardware and form, be fit to very much the practical application of ultra-large type integrated circuit.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 illustrates the block diagram of knowing two-dimensional dct/idct circuit.
Fig. 2 illustrates according to a preferred embodiment of the present invention circuit structure.
Fig. 3 illustrates the sequential relationship according to Fig. 2 one variable Rate dual-port buffer unit I/O.
Fig. 4 illustrates the output timing relation according to Fig. 2 one choice device.
Fig. 5 illustrates the sequential relationship according to I/O between each device of Fig. 2.
Fig. 6 illustrates the sequential relationship according to Fig. 2 one contravariant speed both-end buffer unit I/O.
Fig. 7 illustrates according to a preferred embodiment of the present invention variable Rate dual-port buffer unit detailed circuit and forms.
See also the circuit structure according to a preferred embodiment of the present invention shown in Figure 2.Comprising one group of variable Rate dual-port buffer unit (Rate buffer), 10, one choice device 11, one group of one dimension DCT/IDCT arithmetic unit 12, the conversion buffered device 13 of ranks and contravariant speed port buffer unit (IRate buffer) 14.
If if input area blocks of data X is N * N size, be example with N=8, then the X block data can be expressed as:
So, through the two-dimensional dct calculated result, output area blocks of data Y can be expressed as:
Therefore block X can be according to X
00, X
01, X
02, X
03, X
04, X
05, X
06, X
07, X
10, X
11, X
12, X
13..., X
20, X
21..., X
70, X
71, X
72, X
73, X
74, X
75, X
76, X
77, row order, input variable Rate dual-port buffer unit 10; And block Y is also with Y
00, Y
01, Y
02, Y
03, Y
04, Y
05, Y
06, Y
07, Y
10, Y
11, Y
12, Y
13..., Y
20, Y
21, Y
70, Y
71, Y
72, Y
73, Y
74, Y
75, Y
76, Y
77, 14 outputs of row order self-reversal speed dual-port buffer unit.
So, at variable Rate dual-port buffer unit 10 shown in Figure 2 can be the dual-port buffer of the size word I/O simultaneously that is N * N, the speed of its dateout can be the twice of input data rate, and its input/output end port can the addressing respectively according to the input demand of the order of input block and double-speed one dimension DCT/IDCT arithmetic unit 12.
Choice device 11 is one 2 and selects 1 selector, can select input data by 11a and two inputs of 11b, from 12a data is delivered to one dimension DCT/IDCT arithmetic unit 12 again.
The one dimension DCT/IDCT arithmetic unit 12 of double-speed is the DCT/IDCT arithmetic unit of an one dimension N input, its computing throughput rate (throughput rate) is more than or equal to the output speed of variable Rate dual-port buffer unit 10, and its execution cycle (1atency) then is less than or equal to 2N-1.
The size of the conversion buffered device 13 of ranks also is a N * N word, and it is listed as conversion except providing to the input data, more can be according to the demand of one dimension DCT/IDCT arithmetic unit with different output port addressing modes.
The size of contravariant speed dual-port buffer unit 14 is a N * N word, it is the dual-port buffer of an I/O simultaneously, its input port can be imported one or N word simultaneously according to the way of output of one dimension DCT/IDCT arithmetic unit 12, and output port then can the addressing according to the output order of dateout Y.
According to the circuit of above-mentioned configuration, its function mode is described as follows:
At first, the block data district is according to aforementioned row order, with the input 10a input by variable Rate dual-port buffering 10 of the set speed of f.Cooperating aforementioned N=8 is example, then through 56 execution cycles, i.e. 56 1/f week after dates, this moment data X
70Variable Rate dual-port buffer unit 10 just to be written please refer to the timing diagram of Fig. 3, so X will export choice device 11 to by variable Rate dual-port buffer unit 10 with the speed of row order, 2f.The purpose of exporting in proper order with row is to serve as the output order that cooperates block Y required, and as shown in Figure 2, if the one dimension DCT/IDCT first time is the column operations with X, then one dimension DCT/IDCT adopts the conversion of Z to put matrix Z for the second time
tColumn operations, just be row operation to Z, its output just in time meets the required output of Y in proper order.As for behind 56 execution cycles, just data being sent, be to get for the mistake that prevents data.
Secondly, when carrying out first time one dimension DCT/IDCT computing, choice device 11 selects the input 11a that connects variable Rate dual-port buffer units 11 to import data.Please refer to sequential relationship shown in Figure 4.And when second time one dimension DCT/IDCT computing, then change buffer unit 13 sense datas from ranks.
When the first time, one dimension DCT/IDCT was in 12 computings of one dimension DCT/IDCT arithmetic unit, the data of being imported by input 12a were the row order X of X
0C, X
1C, X
2C, X
3C, X
4C, X
5C, X
6C, X
7C: C=0 ..., 7; And when the second time, one dimension DCT/IDCT was in 12 computings of one dimension DCT/IDCT arithmetic unit, change the row order Z of Z into by the data of input 12a input
R0, Z
R1, Z
R2, Z
R3, Z
R4, Z
R5, Z
R6, Z
R7: R=0 ..., 7, the data of being exported by output 14a then are the row order Y of Y
R0, Y
R1, Y
R2, Y
R3, Y
R4, Y
R5, Y
R6, Y
R7: R=0 ..., 7.
Operation result Z as the one dimension DCT/IDCT first time
0C, Z
1C, Z
2C, Z
3C, Z
4C, Z
5C, Z
5C, Z
7C: C=0 ..., 7 by the conversion buffered device 13 of input 13a input ranks, has crossed 64 1/2f week after dates, through ranks data converted Z
R0, Z
R1, Z
R2, Z
R3, Z
R3, Z
R4, Z
R5, Z
R6, Z
R7: R=0 ..., 7 selections by choice device 11, i.e. 12a input one dimension 1D DCT/IDCT arithmetic unit 12 carries out the computing of one dimension DCT/IDCT for the second time, and its operation result can be exported by 14a at last.Its sequential is closed as shown in Figure 5.
Fig. 5 has illustrated for a block X from importing variable Rate buffer unit 10 to being treated to the sequential relationship of block Y from all data modes of contravariant speed to buffer device 14 outputs.Rely on the continuous processing of twice one dimension DCT/IDCT computing input, can reach the purpose of real-time two-dimensional dct/IDCT computing, be less than or equal 2N-1 and its primary condition is the execution cycle of the one dimension DCT/IDCT arithmetic unit 12 of double-speed, in above-mentioned example, N is 8, so its execution cycle must not be greater than 15.
Two-dimensional dct/IDCT operation result Y
R0, Y
R1, Y
R2, Y
R3, Y
R4, Y
R5, Y
R6, Y
R7: R=0 ..., 7, import contravariant speed to buffer device 14 with the speed of 2f by output 14a, export with the speed of f from output 14b in the cycle in an inferior 1/f.Please refer to timing diagram shown in Figure 6.
As variable Rate dual-port buffer unit 10, a preferred embodiment is formed by a dual-port static RAM (dual-portSRAM) as shown in Figure 7 in the present invention.In Fig. 7, dual-port static random access memory 102 provides input and output to be subjected to counter 101 and 103 controls respectively, wherein, the pulse ckf of counter 101 operations has a first rate, and the pulse ck2f of counter 103 then produces with one second speed.Based on aforementioned operation logic, second speed is the double of first rate, so output speed will be twice in input rate.
And when making 2-D data export this dual-port buffer unit, the effect that the tool ranks are recombinated in proper order by counter 101 and 103 addressing signals that produce, is holding wire 101c through painstakingly adjusting and 103c and addressing dual-port static random access memory 102.Various addressing modes are arranged and are produced when reseting holding wire according to need.
Therefore, circuit of the present invention is compared with well known, adopting one a group of variable Rate dual-port buffer unit and a choice device with after replacing one dimension DCT/IDCT arithmetic unit, because of the former hsrdware requirements amount is about the latter 1/10th, whole hardware quantity can reduce to know 60 percent, variable Rate dual-port buffer unit of the present invention in addition, ranks commutation pulse device and contravariant speed dual-port buffer unit possess I/O may command addressing function, when can more whole hardware space being reduced to 1/2nd of about prior art, saving hardware greatly and form.
Though the present invention with preferred embodiment explanation as above; right its is not in order to limiting the present invention, anyly knows this operator, without departing from the spirit and scope of the present invention; when more available change and modify, so protection scope of the present invention limits and is as the criterion when looking the accompanying Claim book.
Claims (7)
1, a kind of real-time 2-D discrete cosine conversion (hereinafter to be referred as DCT)/anti-discrete cosine conversion (to call IDCT in the following text) circuit arrangement comprises:
One variable Rate dual-port buffer unit writes with a first rate in order to the block with one group of two dimension N * N word (word) size, after adjusting this block, exports one first one-dimensional data with one second speed;
One choice device, have two input ports, the one input end mouth described variable Rate dual-port buffer unit that is coupled providing the circulation of this first one-dimensional data in the cycle very first time, and provides the one second one-dimensional data circulation from another input port in one second time cycle;
One one dimension DCT/IDCT arithmetic unit, the described choice device that is coupled carries out the DCT/IDCT computing in order to the described one-dimensional data that this choice device is provided;
The conversion buffered device of one ranks, the described DCT/IDCT arithmetic unit that is coupled is in order to forming described second one-dimensional data and be supplied to this choice device through this first one-dimensional data ranks conversion of DCT/IDCT computing; And
One contravariant speed dual-port buffer unit, the described DCT/IDCT arithmetic unit that is coupled will be in order to exporting with described first rate through described second one-dimensional data of DCT/IDCT computing.
2, circuit arrangement as claimed in claim 1, wherein, described second speed is to be twice in described first rate.
3, circuit arrangement as claimed in claim 1, wherein, the data throughput rate of described one dimension DCT/IDCT arithmetic unit (throughput rate) can be more than or equal to described variable Rate dual-port buffer unit, and it is the DCT/IDCT computing of finishing the one-dimensional data of one group of N word in 2N-1 the execution cycle based on described second speed.
4, circuit arrangement as claimed in claim 1, wherein, described variable Rate dual-port buffer unit can be a dual-port sram device.
5, circuit arrangement as claimed in claim 1, wherein, described variable Rate dual-port buffer unit can be controlled its input and output operation with the pulse of two different rates respectively.
6, circuit arrangement as claimed in claim 1, wherein, described variable Rate dual-port buffer unit is the two counter addressing that utilize the pulse of different rates to control, to produce the I/O operation of described first rate and described second speed.
7, circuit arrangement as claimed in claim 1, wherein, described variable Rate dual-port buffering is still utilized the arrangement of addressing signal line and is adjusted described block, produces the effect of ranks reorganization.
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| CN95105094A CN1061191C (en) | 1995-05-05 | 1995-05-05 | Real-time two-dimention discrete cosine conversion/anti-discrete cosine conversion circuit device |
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| CN95105094A CN1061191C (en) | 1995-05-05 | 1995-05-05 | Real-time two-dimention discrete cosine conversion/anti-discrete cosine conversion circuit device |
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| CN1061191C true CN1061191C (en) | 2001-01-24 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5249146A (en) * | 1991-03-27 | 1993-09-28 | Mitsubishi Denki Kabushiki Kaisha | Dct/idct processor and data processing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5249146A (en) * | 1991-03-27 | 1993-09-28 | Mitsubishi Denki Kabushiki Kaisha | Dct/idct processor and data processing method |
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