CN105049203A - Configurable 3DES encryption and decryption algorism circuit capable of supporting multiple work modes - Google Patents
Configurable 3DES encryption and decryption algorism circuit capable of supporting multiple work modes Download PDFInfo
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Abstract
The invention belongs to the technical field of the design of cryptographic integrated circuits, and specifically relates to a configurable 3DES encryption and decryption algorism circuit capable of supporting multiple work modes. The 3DES encryption and decryption algorism circuit is formed by an AHB bus interface, a data transmission module, an execution module, and a core encryption module. According to the circuit, the structure of ping-pong buffer is employed, the clock consumption for waiting data input between adjacent encryption and decryption operations in the processes of encryption and decryption of the whole circuit is avoided, and the encryption efficiency and the decryption efficiency are improved; the bus interface is provided so that the circuit can be integrated to a system on chip regarding an AMBA bus as the interconnection mechanism; selective single DES encryption and decryption or 3DED encryption and decryption can be realized, the encryption and decryption of DES or 3DES in four different modes can be realized, and the four modes refer to electronic code books, cipher block chaining, cipher feedback, and output feedback; the overall operating efficiency is high, the area is small, and the circuit can be well applied to systems with high safety performance requirement.
Description
Technical field
The invention belongs to cryptography integrated circuit (IC) design technical field, be specifically related to a kind of configurable 3DES enciphering and deciphering algorithm circuit supporting multi-operation mode.
Background technology
In recent years, along with fast development and the popularization and application of computer and information technology, the scale of the application system of industry-by-industry expanded rapidly, along with and the application data that produces presents explosive growth.More application message is exposed on network undoubtedly by the generation of big data quantity and transmission while promotion industry development.In order to ensure the fail safe of the data produced and transmit, the software and hardware that industry-by-industry all studies effective encryption/decryption module in oneself application system realizes.
Des encryption algorithm is the symmetric cryptography be most widely used, and it uses the grouping of 64 and the key of 56.DES is relatively fragile under exhaustive attack, and a kind of improved plan adopts multi-enciphering technology, as triple des (3DES) cryptographic algorithm.3DES cryptographic algorithm uses DES algorithm at three phases, and by using different keys respectively at des encryption, DES deciphering and des encryption stage are encrypted data.This technology expands the use width of key, greatly reduces the possibility attempting taking Brute Force cryptographic algorithm.Up to the present, 3DES cryptographic algorithm is considered to safe on violence cracks.Therefore, needing to ensure that in the application of high security performance, 3EDS cryptographic algorithm is widely accepted.If data are not high to data security requirement, double DES or des encryption algorithm can be adopted to reduce and to realize cost, improve arithmetic speed.
Summary of the invention
The object of this invention is to provide a kind of configurable 3DES enciphering and deciphering algorithm circuit supporting multiple-working mode, can be widely used in needing to ensure safety in the system of performance.
The configurable 3DES enciphering and deciphering algorithm circuit of support multiple-working mode provided by the invention, adopt a kind of structure of ping-pong buffer, make whole circuit avoid in encryption process adjacent encryption and decryption operate between etc. the clock consumption of data to be entered, improve encryption and decryption efficiency.
3DES cryptographic algorithm circuit provided by the invention, entire block diagram as shown in Figure 1, comprises as lower module:
(1) ahb bus interface DES_ahb module is in the SOC (system on a chip) of interconnected mechanism for being integrated into AMBA bus;
(2) top-level module DES_mode module, connects for the signal realizing data transmission interface DES_io module, DES_3DES Executive Module and core encryption DES module.Whole DES_mode module can be used for realizing selecting substance DES encryption and decryption or 3DES encryption and decryption; And realize the encryption and decryption of DES or 3DES of four kinds of different modes, four kinds of patterns are: code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedack (OFB);
(3) data transmission interface DES_io module, the function that this module mainly realizes is, in units of 32 bits, transfer of data is carried out with external module, by deposit data in register, pattern as required carries out different scheduling again, will the data of encryption and decryption be needed to import DES_3DES module in units of 64 bits;
(4) DES_3DES Executive Module, can realize DES and 3DES two kinds of encryption and decryption modes according to control register;
(5) core encryption DES module, the syndrome matrix process of this module as shown in Figure 2.Wherein, if Li-1, Ri-1 refer to one respectively take turns the high 32 and low 32 of the cryptographic data transformations module input of iteration; It is high 32 and low 32 that Li, Ri refer to that a cryptographic data transformations module of taking turns iteration exports respectively, and input as the data of next round iteration; Ki is the required round key of often taking turns iterative cryptographic data transformation; Ci-1, Di-1 refer to take turns the high 28 and low 28 of corresponding round key generation module input in iteration respectively; Ci, Di refer to take turns that corresponding round key generation module in iteration exports is high 28 and low 28 respectively, and as the input of next round iteration.
The intermediate data of 64 is divided into independently left and right 32 bit data Li-1 and Ri-1, and the process of often taking turns iterated transform can be classified as following formula:
Wherein,
computing between second XOR input.Namely first Ri-1 expands to 48 bit data through expansion displacement, then carries out XOR with the round key Ki of 48, and result is sent in S box, the output of S box carry out a replacement operator again and and Li-1 carry out secondary xor operation.See the left-half of Fig. 2.
Round key Ki generates, and first Ci, Di are moved to left 1 or 2, and then carry out displacement squeeze operation, result is the round key Ki often taking turns iteration, see the right half part of Fig. 2.
Carry out under whole iterative data path encryption iteration in figure 3 controls the control of submodule.
As shown in Figure 3, main submodule comprises core encryption DES module frame chart:
Encryption iteration controls submodule, and this submodule comprises key initial permutation module, and the effect of this module is the data of 56 by displacement selection operational transformation by the initial key of 64, and as the input of round key generation module in Fig. 2; Sub-key generation module, the data path of this module is the right half part in above-mentioned Fig. 2;
Data initial permutation submodule, expressly rearranges by original input, and as the input of cryptographic data transformations module in Fig. 2;
Round function submodule, is above-mentioned data path
;
Data inverse initial permutation submodule, operates reciprocal computing with initial permutation, and this module is that replacement operator is carried out in the output of the data after 16 take turns encryption iteration, and result is final ciphertext and exports.
Circuit integrity operation efficiency of the present invention is high, and area is little, can be applied to preferably in the system of high safety performance requirement.
Accompanying drawing explanation
Figure 13 des encryption algorithm circuit integrity block diagram.
Fig. 2 core encryption DES module syndrome matrix process.In figure, Li-1, Ri-1 and Li, Ri refer to the high 32 and low 32 of the data input and output taking turns iteration respectively; Ci-1, Di-1 and Ci, Di refer to take turns the high 28 and low 28 of corresponding round key input and output in iteration respectively.
Fig. 3 core encryption DES module frame chart.
The explanation of Fig. 4 DES_io module controls register field.In figure, start_bit: start control signal; Endec_bit: encrypting and decrypting selects signal, low is encryption, and high is deciphering; Des_tdes_bit:DES or 3DES selects signal, and height is 3DES, and low is DES; Mode_bits: mode select signal, " 00 " is ECB, and " 01 " is CBC, and " 10 " are CFB, and " 11 " are OFB.
The structure diagram of Fig. 5 ping-pong buffer.In figure, register data_in_reg and data_in_reg2 is used to realize interleaved enciphered data, and the object of signal cnt is the storage control signal realizing external encryption data, is used for the register object of Choice encryption.
Fig. 6 DES_io module schedules conceptual scheme.In figure, des_data_in: data-in port; Endec: encryption or decrypt operation control signal; Mode_bit: mode select signal.
Fig. 7 DES_io inside modules state machine diagram.State description: IDLE: initial condition; DES: encrypted state; NOACTIVE: encryption completion status.Signal instruction: start_bit: signal for 1 time show encrypt needed for data ready, encryption start; Des_data_valid: show that encryption completes when signal is 1.
Fig. 8 DES_3DES inside modules state machine diagram.State description: IDLE: initial condition; The first time encrypted state of DES1:DES encrypted state or 3DES encrypted state; The decrypted state of DES2:3DES encrypted state; The second time encrypted state of DES3:3DES encrypted state.
Signal instruction: triple_active: show when signal is 1 that encryption effectively; Des_tdes: be shown to be 3DES encryption mode when signal is 1 is 0 be shown to be des encryption pattern; Single_data_valid: show when signal is 1 that single-wheel encryption and decryption completes.
Embodiment
The function that data transmission interface DES_io module mainly realizes is, in units of 32 bits, transfer of data is carried out with external module, by deposit data in register, then pattern as required carries out different scheduling, will the data of encryption and decryption be needed to import DES_3DES module in units of 64 bits.
Data transmission interface DES_io module deposits the control register of the control signal of software merit rating, and as shown in Figure 4, this register is for realizing different encryption and decryption mode and different working modes configuration schedules.Different control fields is as follows:
Start_bit: start control signal.
Endec_bit: encrypting and decrypting selects signal, low is encryption, and high is deciphering.
Des_tdes_bit:DES or 3DES selects signal, and height is 3DES, and low is DES.
Mode_bits: mode select signal, " 00 " is ECB, and " 01 " is CBC, and " 10 " are CFB, and " 11 " are OFB.
Busy_bit: busy signal, when for time high, illustrates that this takes turns encryption and decryption and does not also complete; For low, expression completes.
Adopt the structure of ping-pong buffer in this module, the clock consumption of data to be entered such as whole circuit is avoided between the operation of adjacent encryption and decryption in encryption process, improve encryption and decryption efficiency.This modular structure block diagram as shown in Figure 5.It comprises a state of a control machine, a data processing and memory module, counter, two register data_in_reg and data_in_reg2, and two register data_in_reg and data_in_reg2 are used for coming interleaved enciphered data; Data processing and the memory module data path that gating is different under the control of state of a control machine realize processing different enciphered datas and the storage of result; Counter produces signal cnt under the control of state of a control machine, and signal cnt is the storage control signal realizing external encryption data, is used for the register object of Choice encryption.This structure realizes interleaved enciphered data by increase by one group of register (data_in_reg2), improves the efficiency of whole encryption and decryption by increasing very little hardware spending.
Under DES encryption and decryption mode, encryption clock utilization (encryption clock utilization refer to encryption and decryption in whole encryption process perform the clock periodicity that occupies and encryption and decryption data be input to encryption and decryption complete between the ratio of clock periodicity that occupies of whole process) be promoted to 92% by 82%; Under 3DES encryption and decryption mode, encryption clock utilization is promoted to 97% by 93%.
As shown in Figure 6, the state machine of its inside as shown in Figure 7 for data transmission interface DES_io module schedules scheme.
After start_bit is set to height by outside, illustrates outside needing the data of encryption to put into data_in_reg, the key that encryption needs is put into key_reg.State machine enters DES state, arranges des_active for high, starts DES_3DES and start working.
When detecting that des_data_valid is high, show that encryption terminates, state machine enters NOACTIVE state, is set to by des_active low, once encrypts end.
DES_3DES Executive Module can realize DES and 3DES two kinds of encryption and decryption modes according to control register.
The internal state machine of DES_3DES Executive Module as shown in Figure 8.It performs flow process:
Initial condition is IDLE.When triple_active is high, show that encryption starts, enter DES1 state.
DES1 state: set high by single_active, single_endec=triple_endec, key is triple_key1, starts a des encryption.Until single_data_valid is high, first round encryption terminates.If des_tdes is low, illustrates and just need substance des encryption and decryption, next state is IDLE state.If des_tdes is high, illustrate and need triple_des encryption and decryption, next state is DES2.
Triple_endec, key is triple_key2, starts a des encryption.Until single_data_valid is high, second takes turns encryption terminates.Next state is DES3.
DES3 state: set high by single_active, single_endec=triple_endec, key is triple_key3, starts a des encryption.Until single_data_valid is high, third round encryption terminates.Next state is IDLE.
Wherein, there is some process change over clock three centres due to each triple_des encryption and decryption, so the result of each encryption and decryption needs to preserve, in order to save the register of 64 bits.After des encryption is each time complete, result is outputted to DES_io module by port triple_data_out [63:0], temporarily be stored in register des_data_out [63:0], when to encrypt beginning next time, inputted by port triple_des_in [63:0].
Whole 3DES enciphering and deciphering algorithm circuit VerilogHDL designs, and under SMIC65nmCMOS process synthesis, obtaining corresponding area is 0.01429mm
2, power consumption when being operated in 500MHz is 2.688mW.This 3DES enciphering and deciphering algorithm circuit can perform well in the application scenario of high safety performance requirement, low cost, low-power consumption.
Claims (4)
1. support a configurable 3DES enciphering and deciphering algorithm circuit for multiple-working mode, it is characterized in that comprising as lower module:
(1) ahb bus interface DES_ahb module is in the SOC (system on a chip) of interconnected mechanism for being integrated into AMBA bus;
(2) top-level module DES_mode module, connects for the signal realizing data transmission interface DES_io module, DES_3DES Executive Module and core encryption DES module; Whole DES_mode selects substance DES encryption and decryption or 3DES encryption and decryption for realizing; And realize the encryption and decryption of DES or 3DES of four kinds of different modes, four kinds of patterns are: code book, cipher block chaining, cipher feedback, output feedack;
(3) data transmission interface DES_io module, its function mainly realized is, in units of 32 bits, transfer of data is carried out with external module, by deposit data in register, pattern as required carries out different scheduling again, will the data of encryption and decryption be needed to import DES_3DES module in units of 64 bits;
(4) DES_3DES Executive Module, it realizes DES and 3DES two kinds of encryption and decryption modes according to control register;
(5) core encryption DES module, the syndrome matrix process of this module is as follows:
If Li-1, Ri-1 refer to one respectively and take turns the high 32 and low 32 of the cryptographic data transformations module input of iteration; It is high 32 and low 32 that Li, Ri refer to that a cryptographic data transformations module of taking turns iteration exports respectively, and input as the data of next round iteration; Ki is the required round key of often taking turns iterative cryptographic data transformation; Ci-1, Di-1 refer to take turns the high 28 and low 28 of corresponding round key generation module input in iteration respectively; Ci, Di refer to take turns that corresponding round key generation module in iteration exports is high 28 and low 28 respectively, and as the input of next round iteration;
The intermediate data of 64 is divided into independently left and right 32 bit data Li-1 and Ri-1, and the process of often taking turns iterated transform is classified as following formula:
Wherein,
computing between second XOR input, namely first Ri-1 expands to 48 bit data through expansion displacement, then carry out XOR with the round key Ki of 48, result is sent in S box, the output of S box carry out a replacement operator again and and Li-1 carry out secondary xor operation;
Round key Ki generates: first Ci, Di are moved to left 1 or 2, and then carry out displacement squeeze operation, result is the round key Ki often taking turns iteration.
2. the configurable 3DES enciphering and deciphering algorithm circuit of support multiple-working mode according to claim 1, it is characterized in that described data transmission interface DES_io module comprises the control register of the control signal of software merit rating, this control register is for realizing different encryption and decryption mode and different working modes configuration schedules.
3. the configurable 3DES enciphering and deciphering algorithm circuit of support multiple-working mode according to claim 2, it is characterized in that described data transmission interface DES_io module adopts the structure of ping-pong buffer, it comprises a state of a control machine, a data processing and memory module, counter, two register data_in_reg and data_in_reg2, and two register data_in_reg and data_in_reg2 are used for coming interleaved enciphered data; Data processing and the memory module data path that gating is different under the control of state of a control machine realize processing different enciphered datas and the storage of result; Counter produces signal cnt under the control of state of a control machine, and signal cnt is the storage control signal realizing external encryption data, is used for the register object of Choice encryption.
4. the configurable 3DES enciphering and deciphering algorithm circuit of support multiple-working mode according to claim 3, is characterized in that the internal state machine of described DES_3DES Executive Module performs flow process and is:
Initial condition is IDLE, when triple_active is high, shows that encryption starts, enters DES1 state;
DES1 state: single_active is set high, single_endec=triple_endec, key is triple_key1, starts a des encryption; Until single_data_valid is high, first round encryption terminates; If des_tdes is low, illustrates and just need substance des encryption and decryption, entering next state is IDLE state; If des_tdes is high, illustrate and need triple_des encryption and decryption, entering next state is DES2;
Triple_endec, key is triple_key2, starts a des encryption; Until single_data_valid is high, second takes turns encryption terminates; Entering next state is DES3;
DES3 state: single_active is set high, single_endec=triple_endec, key is triple_key3, starts a des encryption, until single_data_valid is high, third round encryption terminates; Entering next state is IDLE.
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Cited By (4)
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| CN111901115A (en) * | 2020-07-27 | 2020-11-06 | 合肥工业大学 | SIMON algorithm encryption circuit in multi-configuration mode |
| CN112199325A (en) * | 2020-10-27 | 2021-01-08 | 南京大学 | Reconfigurable computing implementation device and reconfigurable computing method for 3DES encryption and decryption algorithm |
| CN113918117A (en) * | 2020-06-24 | 2022-01-11 | 美光科技公司 | Dynamic precision bit string accumulation |
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