CN104917784A

CN104917784A - Data migration method and device, and computer system

Info

Publication number: CN104917784A
Application number: CN201410086085.XA
Authority: CN
Inventors: 褚力行
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-03-10
Filing date: 2014-03-10
Publication date: 2015-09-16
Anticipated expiration: 2034-03-10
Also published as: CN104917784B; WO2015135383A1

Abstract

The embodiment provides a data migration method, a data migration device and a computer system. Based on the data migration method, the data migration speed can be increased, and the system performance can be improved. The data migration method comprises the steps of: determining a physical address of data, accessed by a progress P0, at a logic node j according to a virtual address of the data, accessed by the progress P0, at a logic node i when the progress P0 migrates from the logic node i to the logic node j; copying the data accessed by the progress P0 from a first internal storage of the logic node i to a cache of the logic node j according to the physical address of the data, accessed by the progress P0, at the logic node j; and migrating the data accessed by the progress P0 from the cache of the logic node j to the first internal storage of the logic node i if it is determined that the data accessed by the progress P0 meets a migration condition. The data migration method is applicable to the field of computer technologies.

Description

A kind of data migration method, device and computer system

Technical field

The present invention relates to field of computer technology, particularly relate to a kind of data migration method, device and computer system.

Background technology

Non Uniform Memory Access access (Non Uniform Memory Access Architecture, NUMA) framework is the one of server architecture, in logic whole server system is divided into multiple node, each logical node is assigned with a central processing unit (Central Processing Unit, CPU) and one section of corresponding physical memory, each logical node can access this node memory source (local internal memory), also the memory source (remote memory) of other nodes can be accessed, but the speed of local resource access is far away faster than access remote memory, general under NUMA framework, the time delay of access remote memory is 3-20 times that accesses local internal memory.

NUMA framework have be easy to management; the advantage that expandability is good; but; at existing operating system (Operating System; OS) in mechanism; usual meeting carries out load balancing according to the state of CPU, thus by the one or more thread/process migrations in the CPU of heavier loads on other CPU.Such as when the load of CPU is very high, OS from the task of this CPU is lined up, will select specific process/thread, during the task of being moved to other CPU is lined up.But after operating system is by this process migration to other logical nodes, the data usually this process can not accessed also move to the internal memory of other logical node.Like this, the data of accessing due to this process are still in the internal memory of original logical node, like this when this process visit data, need cross-node to access, thus cause a large amount of remote access, increase access time delay, reduce systematic function.

In the prior art, for the problems referred to above, following solution is proposed: after the process/thread of source logical node is moved to object logical node by OS, when the data that this process is accessed meet the condition of Data Migration, the data of this process being accessed move to object logical node from source logical node.But the time directly data that this process is accessed being moved to object logical node from source logical node is longer, the expense brought is comparatively large, improves systematic function still very undesirable.

Summary of the invention

The embodiment provides a kind of data migration method, device and computer system, the speed of Data Migration can be improved, thus achieve the raising of entire system performance.

For achieving the above object, embodiments of the invention adopt following technical scheme:

First aspect, embodiments provide a kind of data migration method, NUMA framework is by multiple physical node, node control chip and NUMA manager are formed, wherein, each physical node is divided into one or more logical node, and each logical node is assigned with first processor, first internal memory, first processor cache memory and buffer memory; Described node control chip, for connecting two physical nodes, carries out copying of data between described two physical nodes; Described NUMA manager, by bus, the second processor be connected with bus and the second internal memory be connected with bus form, wherein, described second processor is connected with all described physical nodes, for managing described physical node, and the instruction that described second internal memory needs to call for storing described second processor, the method is applied to described NUMA manager, and the method comprises:

After process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine data that described process P0 the accesses physical address at described logical node i;

The data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory of described logical node j by the data of accessing according to described P0 from first internal memory of described logical node i;

If determine, the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to first internal memory of described logical node j from the buffer memory of described logical node j.

In the execution mode that the first is possible, in conjunction with first aspect, it is described when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, the method also comprises:

Judge that whether described logical node i and described logical node j is at Same Physical node;

If described logical node i and described logical node j is not at Same Physical node, send a notification message to described node control chip, described notification message comprises the physical address of data at described logical node i of described process P0 access, described node control chip is connected with the physical node at described logical node j place with the physical node at described logical node i place respectively, and the data of being accessed by described process P0 to make described node control chip copy to the buffer memory of described logical node j from first internal memory of described logical node i;

If described logical node i and described logical node j is at Same Physical node, by the buffer memory of the data Replica of described process P0 access to described logical node j.

In the execution mode that the second is possible, in conjunction with first aspect or the first possible execution mode, it is described when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, the method also comprises:

If described logical node i and described logical node j is not at Same Physical node, send a notification message to node control chip, the physical address of data at described logical node i of described process P0 access is comprised in described notification message, the data in the first processor cache memory of described logical node i of being accessed by described process P0 to make described node control chip, copy in the first processor cache memory of described logical node j from the first processor cache memory of described logical node i;

If described logical node i and described logical node j is at Same Physical node, the data in the first processor cache memory of described logical node i of described process P0 access, copy in the first processor cache memory of described logical node j from the first processor cache memory of described logical node i;

Send the first notification message to all logical nodes, described first notification message is copied in the first processor cache memory of described logical node j for the data in the first processor cache memory of described logical node i notifying described process P0 and access.

In the execution mode that the third is possible, in conjunction with any one in the execution mode that first aspect, the first possible execution mode or the second are possible, determine that if described the data that described process P0 accesses meet transition condition, the data of described process P0 access migrated to after first internal memory of described logical node j from the buffer memory of described logical node j, the method also comprises:

Set up the data of described process P0 access in the described virtual address of logical node j and the mapping relations of physical address.

Second aspect, embodiments provides a kind of data migration device, and this device comprises: determining unit, copied cells and migration units;

Described determining unit, for after process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determines data that described process P0 the accesses physical address at described logical node i;

The data of described process P0 access, for the data of accessing according to the described P0 physical address at described logical node i, are copied to the buffer memory of described logical node j by described copied cells from the internal memory of described logical node i;

The data of described process P0 access, if for determining that the data that described process P0 accesses meet transition condition, are migrated to the internal memory of described logical node j from the buffer memory of described logical node j by described migration units.

In the execution mode that the first is possible, in conjunction with second aspect, this device also comprises: judging unit;

Described judging unit, for judging that whether described logical node i and described logical node j is at Same Physical node;

Described copied cells specifically for:

If described logical node i and described logical node j is not at Same Physical node, send a notification message to node control chip, described notification message comprises the physical address of data at described logical node i of described process P0 access, described node control chip is connected with the physical node at described logical node j place with the physical node at described logical node i place respectively, and the data of being accessed by described process P0 to make described node control chip copy to the buffer memory of described logical node j from the internal memory of described logical node i;

In the execution mode that the second is possible, in conjunction with second aspect or the first possible execution mode, optionally, described copied cells also for:

If described logical node i and described logical node j is not at Same Physical node, send a notification message to node control chip, the physical address of data at described logical node i of described process P0 access is comprised in described notification message, the data in the processor high speed buffer storage of described logical node i of being accessed by described process P0 to make described node control chip, copy in the processor high speed buffer storage of described logical node j from the processor high speed buffer storage of described logical node i;

If described logical node i and described logical node j is at Same Physical node, the data in the processor high speed buffer storage of described logical node i of described process P0 access, copy in the processor high speed buffer storage of described logical node j from the processor high speed buffer storage of described logical node i;

Concrete, this device also comprises: transmitting element;

Described transmitting element, for sending the first notification message to all logical nodes, described first notification message is copied in the processor high speed buffer storage of described logical node j for the data in the processor high speed buffer storage of described logical node i notifying described process P0 and access.

In the execution mode that the third is possible, in conjunction with second aspect, any one in the first possible execution mode or the possible execution mode of the second, this device also comprises: set up unit;

Describedly set up unit, for setting up data that described process P0 accesses in the described virtual address of logical node j and the mapping relations of physical address.

The third aspect, embodiments provides a kind of computer system, comprising:

Multiple physical node, wherein, each physical node is divided into one or more logical node, and each logical node is assigned with first processor, the first internal memory, first processor cache memory and buffer memory;

Node control chip, for connecting two physical nodes, carries out copying of data between described two physical nodes;

NUMA manager, by bus, the second processor be connected with bus and the second internal memory be connected with bus form, wherein, described second processor is connected with all described physical nodes, for managing described physical node, the instruction that described second internal memory needs to call for storing described second processor;

Described second processor calls the execution instruction in described second internal memory by described bus, for: after process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine data that described process P0 the accesses physical address at described logical node i;

In the execution mode that the first is possible, in conjunction with the third aspect, described processor specifically for:

In the execution mode that the second is possible, in conjunction with the third aspect or the first possible execution mode, described processor also for:

In the execution mode that the third is possible, in conjunction with any one in the execution mode that the third aspect, the first possible execution mode or the second are possible, described processor also for:

Embodiments provide a kind of data migration method, device and computer system, the method comprises: when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine data that described process P0 the accesses physical address at described logical node i; The data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory of described logical node j by the data of accessing according to described P0 from first internal memory of described logical node i; If determine, the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to first internal memory of described logical node j from the buffer memory of described logical node j.Based on technical scheme of the present invention, can after process be migrated to object logical node from source logical node, before the data of accessing in this process meet transition condition, the data Replica of first this process being accessed is in the buffer memory of object logical node, once the data of this process access meet transition condition, the data that can this process be accessed fast move to the internal memory of this object logical node from the buffer memory of object logical node, thus improve the speed of the migration of the data of described process access, and then improve entire system performance.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 a is a kind of NUMA configuration diagram;

Fig. 1 b is another kind of NUMA configuration diagram;

Fig. 2 is another NUMA configuration diagram;

Fig. 3 is a kind of data migration method flow chart;

Fig. 4 is another NUMA configuration diagram;

Fig. 5 is another kind of data migration method flow chart;

Fig. 6 is another data migration method flow chart;

Fig. 7 is a kind of data migration device schematic diagram;

Fig. 8 is another kind of data migration device schematic diagram;

Fig. 9 is another data migration device schematic diagram;

Figure 10 is another data migration device schematic diagram;

Figure 11 is a kind of computer system schematic diagram.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

NUMA framework is a kind of multi node server framework, and by multiple physical node, node control chip and NUMA manager three part are formed, concrete:

Part I: multiple physical node.In the hardware configuration of reality, in each physical node, there is one or more processor, the corresponding one section of physical memory of each processor, and the cache memory that each processor is corresponding.

Composition graphs 1a, when only having a processor in a physical node, described physical node can only be divided into a logical node, described logical node is assigned with processor, internal memory and processor high speed buffer storage.

When there being multiple processor in described physical node, according to described physical memory, described physical node can be divided into multiple logical node.Like this, there are two kinds of situations, the first situation is assigned with a processor and one section of physical memory corresponding to this processor in a logical node, and the second situation is assigned with two or more processor and physical memory corresponding to each processor in a logical node.

It should be noted that, in the latter case, for example, if be assigned with two processors in a logical node, wherein, each processor has corresponding physical memory.Now, the time delay of the data stored in the physical memory that the time delay of the data stored in the physical memory of one of them its correspondence of processor access is corresponding with another processor of access is the same.A process/thread can not produce access time delay and become large problem from one of them processor migration described to another processor described, therefore, in the present invention, can regard these two processors as same processor, the physical memory 2 that these two processors are corresponding respectively regards same section of physical memory as.Composition graphs 1b, a physical node is divided into two or more logical node.

Part II: node control chip.Concrete: in the multi node server of NUMA framework, when the physical node number of server increases, if each physical node can be confined to the number of ports of node by the mode of cable direct interconnection or be confined to interconnected communication agreement, for example, when four physical nodes need to interconnect between two, each physical node needs three interfaces, when N number of physical node needs to interconnect between two, each physical node needs N-1 interface, therefore, when using cable direct interconnection, the number of ports of physical node can limit the connection of physical node.

Because chip can have multiple interface, therefore, by node control chip, each node server can be interconnected, namely, two adjacent physical nodes are connected by a node control chip, and described node control chip is mainly used in the high-speed interconnect between physical node, as communication interconnect between processor and processor, the copying of data between physical node, and the functions such as buffer consistency inspection, message repeating can be realized.

It should be noted that, composition graphs 2, a node control chip only can connect two physical nodes, and also can connect multiple physical node, realize the interconnection between two of physical node, the embodiment of the present invention does not limit this simultaneously.

Certainly, whether for adopting node control chip to be connected between two physical nodes, the present invention does not limit.

Part III: NUMA manager.Described NUMA manager is made up of processor, internal memory and bus, and the processor in described NUMA manager is connected with all physical nodes in described Part I, for managing described all physical nodes.

After logical node i process P0 is moved to logical node j according to the non-load balanced case distributing to each logical node processor by the operating system of NUMA framework, the internal memory of the data of during general difference, this process being accessed simultaneously from the internal memory migration of logical node i to described logical node j, to avoid unnecessary expense.Such as, if described process P0 does not visit again the data of having moved to the described process P0 access of destination node internal memory after being migrated to logical node j, or after described process P0 is migrated to logical node j, other logical nodes that described P0 is moved back logical node i according to the non-load balanced case of the processor of each logical node or moves to except logical node i and logical node j by operating system, now, while described process P0 is moved to logical node j, the internal memory of the data that described P0 is accessed from the internal memory migration of logical node i to described logical node j, unnecessary expense can be caused, the performance of reduction system.But, if after described process P0 is moved to logical node j from logical node i, the Data Migration of not accessed by P0 is to logical node j, when process P0 accesses the data of oneself, cross-node will be caused to access, namely remote access, now, the time delay that P0 accesses the data of oneself is very large, reduces the performance of system.

Therefore, after process P0 is migrated to logical node j from logical node i, when the data of described process P0 access meet the condition of migration, the data of described process P0 access just can be moved to logical node j from logical node i by operating system, but, in the prior art, the speed directly data that process P0 accesses being moved to logical node j from logical node i cross-node is slower, the expense of Data Migration may balance out the effect of Data Migration, for example, when process P0 is moved to after logical node j from logical node i by operating system, the data of P0 access logic node i need 3s, the data of access logic node j need 1s, but the time that the data that P0 accesses by operating system move to logical node j from logical node i may be 3s, like this, when P0 waits for that the Data Migration that P0 accesses by operating system is accessing these data after the internal memory of logical node j, total time be 4s, also longer than the data delay of direct access logic node i, the expense of migration counteracts the effect of migration.

For this problem, the present invention proposes a kind of data migration method, based on the method, logical node j can be moved to by operating system from logical node i at a process P0, and after the data of described process P0 access meet the condition of migration, the migration of expedited data.Composition graphs 3, the method is applied to described NUMA manager, and the method comprises:

301, after process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, data that described process P0 the accesses physical address at described logical node i is determined.

After a process P0 is established, operating system can set up the virtual address of data and the mapping relations of physical address of a P0 access, when operating system is according to the principle of load balancing, by described process P0 from after logical node i moves to logical node j, described operating system can according to the virtual address of the data of described process P0 access, and the virtual address of data of described process P0 access and the mapping relations of physical address, determine data that described process P0 the accesses physical address at described logical node i.

Concrete, great majority use the system of virtual memory all to use one to be called the mechanism of paging (paging).Virtual address space is divided into the space being called page (page), and corresponding physical address space is also divided, and unit is page frame (frame).In the machine of 32 bit address, it can virtual composition 4G Virtual Space, its virtual address range is from 0 ~ 0xFFFFFFFF, and therefore he can run the program of 4G.And this machine only has the memory headroom of 256M, run so the program being greater than 256M disposablely can not call in internal memory.The external memory storage (such as disk or flash memory FLASH) that this machine must have one can deposit to be greater than 256M program, to ensure that usability of program fragments can be called in internal memory when needed.In this example, the size of page is 4K, and page hardwood size is identical with page---this point must ensure, because the transmission between internal memory and peripheral storage is always in units of page.The corresponding virtual address of 4G and the physical storage of 256M, they contain 1M page and 64K page frame respectively.

Page table embodies the virtual address of data and the mapping relations of physical address of a process access, and realize from page number, namely virtual address is to page frame, i.e. the mapping of physical address.Operating system safeguards a page table to each process, and page table gives the position of every page frame corresponding to one page in process.

Based on this, operating system can according to the virtual address of the data of described process P0 access at logical node i, by inquiry page table, determines data that described process P0 the accesses physical address at logical node i.

Concrete, the virtual address of a process and the mapping relations of physical address can be the forms of page table, and can be also other forms, the embodiment of the present invention limit this.

The data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory of described logical node j by the data of 302, accessing according to described P0 from the internal memory of described logical node i.

Due in the prior art, when the data of described process P0 access meet the condition of migration, the time directly data of described process P0 access being moved to logical node j used from described logical node i is longer, and the expense of migration is comparatively large, may balance out the effect of migration.For this problem, a buffer memory is increased in each logical node of the embodiment of the present invention in the server system of described NUMA framework, concrete, described buffer memory can be a part for the internal memory of described logical node j, also can be a part for the processor high speed buffer storage of described logical node j, as shown in Figure 4, can also be an independent buffer memory device, the embodiment of the present invention limit this.

Concrete, because great majority use the system of virtual memory all to use one to be called paging (paging) mechanism, the data of described P0 access are stored in multiple pages of described logical node i, therefore, described operating system at described process P0 from after described logical node i moves to logical node j, by the data of described process P0 access from the page of described logical node i, copy to the hardware cache of described logical node j, i.e. in the page of described buffer memory.

Concrete, for example, such as, some data in described process P0 visit data, be page m in the virtual address of described logical node i, be page n at the physical address of described logical node i, the data Replica of the page n described process P0 accessed when described operating system in the page k of described buffer memory after, the described operating system data of accessing for described process P0, at the virtual address of described logical node i, physical address and the corresponding relation between the address of the buffer memory of described logical node j, set up a following mapping relations table:

Table one

The virtual address of logical node i	The physical address of logical node i	The address of the buffer memory of logical node j
			Page m	Page n	Page k

Concrete, the corresponding relation between described address can be the form as above table, such as page table, and can be also other forms, the embodiment of the present invention limit this.

Further, such as described process P0 accesses some data, be page m+1 in the virtual address of described logical node i, corresponding, be page n+1 at the physical address of described logical node i, further, when the data in described page n+1 are copied to after in the buffer memory of described logical node j, be stored in the page k+1 of described logical node j.The data of described process P0 access in such a manner, are got up at the virtual address of described logical node i, physical address and the address one_to_one corresponding at described logical node j by described operating system.

After described process P0 is moved to logical node j by operating system from described logical node i, the data that described process P0 accesses by described operating system copy to the buffer memory of described logical node j from the internal memory of described logical node i, like this, when the data of described process P0 access meet the condition of migration, described operating system can by inquiry page table as shown in Table 1, the data of directly being accessed by described P0 move to the internal memory of described logical node j from the buffer memory of described logical node j, improve the speed of migration, and then improve the overall performance of system.

It should be noted that, after the data of described process P0 access are copied to the buffer memory of described logical node j by described operating system in the process from the internal memory of described logical node i, the data of described process P0 access are before meeting transition condition, the time delay of accessing the buffer memory of described logical node j due to described process P0 is longer, described P0 is still accessed by cross-node under normal circumstances, the data that described in the internal memory visiting described logical node i, logical node P0 accesses.Therefore, the data that described process P0 accesses still are retained in the internal memory of now described logical node i, and after the buffer memory data of described process P0 access being copied to described logical node j from the internal memory of described logical node i, the internal memory of data shared by described logical node i of described process P0 access can not be discharged.

If 303 determine that the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to the internal memory of described logical node j from the buffer memory of described logical node j.

Concrete, in different systems, judge whether data meet the condition of moving different.For example, in linux system, when turn-on data shift function, when each tick interrupt arrives, the interruption of system processing clock can check the non-load balanced case of current system, and whether differentiation process has remote memory to access.During inspection, when the data in the page that first time finds in a logical node internal memory are by process remote access, can mark this page; During subsequent clock interrupt processing, being labeled remote access when finding that there is the page, will the data in this page having been moved.

Certainly, judge whether the data in internal memory meet the known technology that the condition of moving is those skilled in the art, the embodiment of the present invention repeats no more this.

When after the buffer memory data of described process P0 access being copied to described logical node j from the internal memory of described logical node i, operating system judges whether data that described process P0 accesses meet the condition of Data Migration, if meet, the data of described process P0 access are migrated to the internal memory of described logical node j from the buffer memory of described logical node j, afterwards, the data that described P0 accesses oneself are local IP access, and time delay is less, and then the performance of elevator system.

When the data of described process P0 access are migrated to after the internal memory of described logical node j from the buffer memory of described logical node j, described operating system can discharge the data of the described process P0 access in the internal memory of described logical node i, further, described operating system re-establishes the data of described process P0 access in the described virtual address of logical node j and the mapping relations of physical address.

Embodiments provide a kind of data migration method, the method comprises: when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine data that described process P0 the accesses physical address at described logical node i; The data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory of described logical node j by the data of accessing according to described P0 from the internal memory of described logical node i; If determine, the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to the internal memory of described logical node j from the buffer memory of described logical node j.Based on the present invention, can after a process be migrated to object logical node from source logical node, when the data that described process is accessed meet transition condition, the data of this process being accessed fast move to the internal memory of described object logical node from the buffer memory of object logical node, thus promote the speed of Data Migration, and then improve entire system performance.

Further, the embodiment of the present invention additionally provides a kind of data migration method, and the method is the detailed description to above-described embodiment, composition graphs 5, and the method is applied to NUMA manager, and the method comprises:

501, when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, data that described process P0 the accesses physical address at described logical node i is determined.

Concrete, the detailed implementation process of step 501 please refer to the step 301 in above-described embodiment, and the embodiment of the present invention repeats no more this.

502, judge that whether described logical node i and described logical node j is at Same Physical node.

Composition graphs 1 and Fig. 2, in the server system of NUMA framework, a logical node may be had in a physical node, also two or more logical node may be had, based on this, when described process P0 is moved to logical node j from logical node i according to the non-load balanced case of the processor of each logical node by operating system time, described logical node i and described logical node j may at Same Physical node, also may at different physical nodes.In both cases, the data that described process P0 accesses by described operating system copy to the buffer memory of described logical node j method from the internal memory of described logical node i is different, therefore, described operating system, before the buffer memory data of described process P0 access being copied to described logical node j from the internal memory of described logical node i, needs to judge that whether described logical node i and described logical node j is at Same Physical node.

If 503 described logical node i and described logical node j are not at Same Physical node, send a notification message to node control chip, described notification message comprises the physical address of data at described logical node i of described process P0 access, described node control chip is connected with the physical node at described logical node j place with the physical node at described logical node i place respectively, and the data of being accessed by described process P0 to make described node control chip copy to the buffer memory of described logical node j from the internal memory of described logical node i.

Composition graphs 1, if described logical node i and described logical node j is not at Same Physical node, be connected by a node control chip between the physical node at described logical node i place and the physical node at described logical node j place, the data of described process P0 access directly cannot be copied to the buffer memory of described logical node j by described operating system across physical node from the internal memory of described logical node i, but the buffer memory of data from the internal memory migration of described logical node i to described logical node j that described process P0 can be accessed by the node control chip of the physical node at the physical node at described connection logical node i place and described logical node j place by described operating system, detailed process is:

Described operating system judges that described logical node i and described logical node j is not after Same Physical node, send a notification message to the node control chip linking the physical node at described logical node i place and the physical node at logical node j place, described notification message comprises the physical address of data at described logical node i of described process P0 access.Now, the data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory of described logical node j by the data that described node control chip is accessed according to described process P0 from the internal memory of described logical node i.

It should be noted that, according to the Process Migration Mechanism of existing operating system, described process P0 is moved to logical node j from logical node i according to the non-load balanced case of the processor in each logical node by described operating system, if described logical node i and described logical node j is not at Same Physical node, described process P0 needs the data being carried out process P0 described in remote access logical node i by the node control chip of the physical node of the physical node and logical node j place connecting described logical node i place or cable, based on this, when described process is moved to described logical node j from described logical node i by described operating system, physical node and the physical node at described logical node j place at described logical node i place must be two physical nodes having node control chip or cable to be connected, otherwise when described process P0 is from after described logical node i moves to logical node j, described process P0 cannot access the data of the described P0 of described logical node i, cause the failure of process visit data.

If 504 described logical node i and described logical node j are at Same Physical node, by the buffer memory of the data Replica of described process P0 access to described logical node j.

If described logical node i and described logical node j is at Same Physical node, after described process P0 is moved to described logical node j from described logical node i, described process P0 accesses the time delay of the data of the described P0 of described logical node i, be less than when described logical node i and described logical node j is not at Same Physical node, described process P0 is across the time delay of physical node visit data, but be still greater than the time delay that described process P0 accesses the internal memory of the logical node at its place, the performance of system can be reduced.Adopt data migration method provided by the present invention, when the data of described process P0 access meet transition condition, the speed of Data Migration can be improved, and then the overall performance of elevator system.

Concrete, if described logical node i and described logical node j is at Same Physical node, the data of described process P0 access directly can be copied to the buffer memory of described logical node j by described operating system from the internal memory of described logical node i.

If 505 determine that the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to the internal memory of described logical node j from the buffer memory of described logical node j.

Concrete, the detailed process of step 505 can see the step 303 in above-described embodiment, and the embodiment of the present invention repeats no more.

Embodiments provide a kind of data migration method, based on the method, can after a process be migrated to object logical node from source logical node, when the data that described process is accessed meet the condition of Data Migration, the data of described process being accessed fast move to the internal memory of described destination node from the buffer memory of object logical node, thus promote the speed of Data Migration, and then improve entire system performance.

Further, when by after the buffer memory of the data of described process P0 access from the internal memory migration of described logical node i to described logical node j, for reducing the remote access of described process P0, the embodiment of the present invention additionally provides a kind of data migration method, composition graphs 6, the method is applied to NUMA manager, and the method comprises:

601, when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, data that described process P0 the accesses physical address at described logical node i is determined.

602, judge that whether described logical node i and described logical node j is at Same Physical node.

The detailed implementation process of step 601-step 602 can see the step 301 in above-described embodiment and step 302, and the embodiment of the present invention repeats no more this.

If 603 described logical node i and described logical node j are not at Same Physical node, send a notification message to node control chip, the physical address of data at described logical node i of described process P0 access is comprised in described notification message, the data in the processor high speed buffer storage of described logical node i of being accessed by described process P0 to make described node control chip, copy in the processor high speed buffer storage of described logical node j from the processor high speed buffer storage of described logical node i.

The data of being accessed by described process P0 when described operating system copy to after the buffer memory of described logical node j from the internal memory of described logical node i, before the data of accessing at described P0 meet transition condition, described P0 needs to continue the data of process P0 described in internal memory that cross-node accesses described logical node i, and access time delay is larger.For reducing the remote access number of times of described process P0 as far as possible, while the data of being accessed by described process P0 in described operating system copy to logical node j from described logical node i, simultaneously by the data in the processor high speed buffer storage of described logical node i of described process P0 access, the processor high speed buffer storage of described logical node j can be copied to from the processor high speed buffer storage of logical node i.

The data in the processor high speed buffer storage of described logical node i of described process P0 access are some data that described process P0 access frequency is higher, the data Replica in the processor high speed buffer storage of described logical node i of described process P0 being accessed when described operating system in the processor high speed buffer storage of described logical node j after, when described process P0 will access these data again, directly can access these data in the processor high speed buffer storage of described node j, now described process P0 accesses the data of oneself is local IP access, time delay is less.

If described logical node i and described logical node j is not at Same Physical node, described operating system needs the node control chip to linking the physical node at described logical node i place and the physical node at logical node j place to send a notification message, the physical address of data at described logical node i of described process P0 access is comprised in described notification message, described node control chip can to determine at the physical address of described logical node i to store in which page in the processor high speed buffer storage of described node i according to described process P0 described in the data of process P0 access, these data are copied to the processor high speed buffer storage of described logical node j by described node control chip from the processor high speed buffer storage of described logical node i.

If 604 described logical node i and described logical node j are at Same Physical node, the data in the processor high speed buffer storage of described logical node i of described process P0 access, copy in the processor high speed buffer storage of described logical node j from the processor high speed buffer storage of described logical node i.

Concrete, when described logical node i and described logical node j at Same Physical node time, described operating system can directly by the data in the processor high speed buffer storage of described logical node i of described process P0 access, from the processor high speed buffer storage of described logical node i, copy to the processor high speed buffer storage of described logical node j.

605, send the first notification message to all logical nodes, described first notification message is copied in the processor high speed buffer storage of described logical node j for the data in the processor high speed buffer storage of described logical node i notifying described process P0 and access.

Concrete, when the data in the processor high speed buffer storage of described logical node i of described process P0 access are copied to after in the processor high speed buffer storage of described logical node j, data in the processor high speed buffer storage of described logical node j are accessed for enabling other processes of described process P0 and other and described process P0 shared portion data, described operating system is operated by buffer consistency, the first notification message is sent to all logical nodes, described first notification message is copied in the processor high speed buffer storage of described logical node j for the data in the processor high speed buffer storage of described logical node i notifying described process P0 and access.

Concrete, when described logical node i and described logical node j is not at Same Physical node, described operating system by connecting the node control chip of the physical node at described logical node i place and the physical node at logical node j place, can issue described first notification message to all logical nodes in the server system of described NUMA framework;

When described logical node i and described logical node j is at Same Physical node, described operating system can issue described first notification message directly to all logical nodes.

Concrete, buffer consistency operation is the known technology of those skilled in the art, and the embodiment of the present invention repeats no more this.

Embodiments provide a kind of data migration method, based on the method, can after a process be migrated to object logical node from source logical node, when the data that described process is accessed meet transition condition, the data of described process being accessed fast move to the internal memory of described object logical node from the buffer memory of described object logical node, thus promote the speed of Data Migration, and then improve entire system performance.

Embodiments provide a kind of data migration device, composition graphs 7, this device comprises: determining unit 701, copied cells 702 and migration units 703;

Described determining unit 701, for when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determines data that described process P0 the accesses physical address at described logical node i;

The data of described process P0 access, for the data of accessing according to the described P0 physical address at described logical node i, are copied to the buffer memory of described logical node j by described copied cells 702 from the internal memory of described logical node i;

The data of described process P0 access, if for determining that the data that described process P0 accesses meet transition condition, are migrated to the internal memory of described logical node j from the buffer memory of described logical node j by described migration units 703.

Concrete, composition graphs 8, this device also comprises: judging unit 704;

Described judging unit 704, for judging that whether described logical node i and described logical node j is at Same Physical node;

Described copied cells 702 specifically for:

Optionally, described copied cells 702 also for:

If described logical node i and described logical node j is at Same Physical node, the data in the processor high speed buffer storage of described logical node i of described process P0 access, copy in the processor high speed buffer storage of described logical node j from the processor high speed buffer storage of described logical node i.

Optionally, composition graphs 9, this device also comprises: transmitting element 705, described transmitting element 705, for sending the first notification message to all logical nodes, described first notification message is copied in the processor high speed buffer storage of described logical node j for the data in the processor high speed buffer storage of described logical node i notifying described process P0 and access.

Concrete, in conjunction with Figure 10, this device also comprises: set up unit 706;

Describedly set up unit 706, for setting up data that described process P0 accesses in the described virtual address of logical node j and the mapping relations of physical address.

Embodiments provide a kind of data migration device, this device comprises: determining unit, copied cells and migration units; Described determining unit, when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determines data that described process P0 the accesses physical address at described logical node i; The data of described process P0 access, at the physical address of described logical node i, copy in the buffer memory of described logical node j by the data that described copied cells is accessed according to described P0 from the internal memory of described logical node i; The data of described process P0 access, when the data that described process P0 accesses meet transition condition, migrate to the internal memory of described logical node j from the buffer memory of described logical node j by described migration units.Based on the present invention, can after a process be migrated to object logical node from source logical node, when the data that described process is accessed meet transition condition, the data of described process being accessed fast move to the internal memory of described object logical node from the buffer memory of described object logical node, thus improve the speed of Data Migration, and then improve entire system performance.

Embodiments provide a kind of computer system, in conjunction with Figure 11, comprising:

Multiple physical node 1101, wherein, each physical node is divided into one or more logical node, and each logical node is assigned with first processor 1102, the first internal memory 1103, first processor cache memory 1104 and buffer memory 1105;

Node control chip 1106, for connecting two physical nodes, carries out copying of data between described two physical nodes;

NUMA manager 1107, by bus 1108, the second processor 1109 be connected with bus and the second internal memory 1110 be connected with bus form, wherein, described second processor 1109 is connected with all described physical nodes, for managing described physical node, the instruction that described second internal memory 1110 needs to call for storing described second processor 1109, described bus 1108 is for realizing the connection communication between described second processor 1109 and described second internal memory 1110.

Concrete, described bus 1108 can be industry standard architecture (Industry Standard Architecture, referred to as ISA) bus, peripheral component interconnect (Peripheral Component, referred to as PCI) bus or extended industry-standard architecture (Extended Industry Standard Architecture, referred to as EISA) bus etc.This bus 1108 can be divided into address bus, data/address bus, control bus etc.For ease of representing, only representing with a thick line in Figure 11, but not representing the bus only having a bus or a type.

Described second internal memory 1110 is for stores executable programs code, and this program code comprises computer-managed instruction.Described second internal memory 1110 may comprise high-speed RAM memory, still may comprise nonvolatile memory (non-volatile memory), such as at least one magnetic disc store.

Concrete, described first processor 1102 and the second processor 1109 may be a central processing unit (Central Processing Unit, referred to as CPU), or specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), or be configured to the one or more integrated circuits implementing the embodiment of the present invention.

Concrete, described second processor 1109 for:

When process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine data that described process P0 the accesses physical address at described logical node i;

The data of described process P0 access, at the physical address of described logical node i, are copied to the buffer memory 1105 of described logical node j by the data of accessing according to described P0 from first internal memory 1103 of described logical node i;

If determine, the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to first internal memory 1103 of described logical node j from the buffer memory 1105 of described logical node j.

Concrete, described second processor 1109 also for:

If described logical node i and described logical node j is not at Same Physical node, send a notification message to node control chip 1106, described notification message comprises the physical address of data at described logical node i of described process P0 access, described node control chip 1106 is connected with the physical node at described logical node j place with the physical node at described logical node i place respectively, and the data of being accessed by described process P0 to make described node control chip copy to the buffer memory 1105 of described logical node j from first internal memory 1103 of described logical node i;

If described logical node i and described logical node j is at Same Physical node, by the buffer memory 1105 of the data Replica of described process P0 access to described logical node j.

Optionally, described second processor 1109, also for judging that whether described logical node i and described logical node j is at Same Physical node;

If described logical node i and described logical node j is not at Same Physical node, send a notification message to node control chip 1106, the physical address of data at described logical node i of described process P0 access is comprised in described notification message, the data in the processor high speed buffer storage 1104 of described logical node i of being accessed by described process P0 to make described node control chip, copy in the processor high speed buffer storage 1104 of described logical node j from the processor high speed buffer storage 1104 of described logical node i;

If described logical node i and described logical node j is at Same Physical node, the data in the processor high speed buffer storage 1104 of described logical node i of described process P0 access, copy in the processor high speed buffer storage 1104 of described logical node j from the processor high speed buffer storage 1104 of described logical node i;

Send the first notification message to all logical nodes, described first notification message is copied in the processor high speed buffer storage 1104 of described logical node j for the data in the processor high speed buffer storage 1104 of described logical node i notifying described process P0 and access.

Concrete, described second processor 1109 also for: set up data that described process P0 accesses in the described virtual address of logical node j and the mapping relations of physical address.

Embodiments provide a kind of computer system, based on this computer system, can after a process be migrated to object logical node from source logical node, when the data that described process is accessed meet transition condition, the data of described process being accessed fast move to the internal memory of described destination node from the buffer memory of described destination node, promote the speed of Data Migration, and then improve entire system performance.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.

Claims

1. a data migration method, it is characterized in that, NUMA framework is by multiple physical node, node control chip and NUMA manager are formed, wherein, each physical node is divided into one or more logical node, and each logical node is assigned with first processor, first internal memory, first processor cache memory and buffer memory; Described node control chip, for connecting two physical nodes, carries out copying of data between described two physical nodes; Described NUMA manager, by bus, the second processor be connected with bus and the second internal memory be connected with bus form, wherein, described second processor is connected with all described physical nodes, for managing described physical node, and the instruction that described second internal memory needs to call for storing described second processor, the method is applied to described NUMA manager, and the method comprises:

If the data of described process P0 access meet transition condition, the data of described process P0 access are migrated to first internal memory of described logical node j from the buffer memory of described logical node j.

2. method according to claim 1, it is characterized in that, it is described when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, the method also comprises:

3. method according to claim 1 and 2, it is characterized in that, it is described when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, the method also comprises:

4. the method according to any one of claim 1-3, it is characterized in that, if determine that described the data that described process P0 accesses meet transition condition, the data of described process P0 access migrated to after first internal memory of described logical node j from the buffer memory of described logical node j, the method also comprises:

5. a data migration device, is characterized in that, this device comprises: determining unit, copied cells and migration units;

The data of described process P0 access, if meet transition condition for the data of described process P0 access, are migrated to the internal memory of described logical node j from the buffer memory of described logical node j by described migration units.

6. device according to claim 5, is characterized in that, this device also comprises: judging unit;

Described copied cells specifically for:

7. the device according to claim 5 or 6, is characterized in that, described copied cells also for:

This device also comprises: transmitting element;

8. the device according to any one of claim 5-7, is characterized in that, this device also comprises: set up unit;

9. a computer system, is characterized in that, comprising:

Described second processor calls the execution instruction in described second internal memory by described bus, for:

10. computer system according to claim 9, it is characterized in that, when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, described second processor calls the instruction in described second internal memory by described bus, specifically for:

11. computer systems according to claim 9 or 10, it is characterized in that, when process P0 moves to logical node j from logical node i, according to the data of the described process P0 access virtual address at logical node i, determine that data that described process P0 accesses are after the physical address of described logical node i, described second processor calls the execution instruction in described second internal memory by described bus, for:

12. computer systems according to any one of claim 9-11, it is characterized in that, determine that if described the data that described process P0 accesses meet transition condition, the data of described process P0 access are migrated to after first internal memory of described logical node j from the buffer memory of described logical node j, described second processor calls the execution instruction in described second internal memory, for: