CN104733283A - Semiconductor surface precleaning method - Google Patents
Semiconductor surface precleaning method Download PDFInfo
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- CN104733283A CN104733283A CN201310717828.4A CN201310717828A CN104733283A CN 104733283 A CN104733283 A CN 104733283A CN 201310717828 A CN201310717828 A CN 201310717828A CN 104733283 A CN104733283 A CN 104733283A
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- semiconductor substrate
- process cavity
- diaphragm
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
Abstract
The invention provides a semiconductor surface precleaning method which at least comprises the following steps that firstly, a base allowed to be pretreated is provided, and the base comprises a semiconductor substrate and an oxidation film formed on the surface of the semiconductor substrate in a natural oxidation mode; next, the base is placed in a first process cavity, etching gas is fed into the first process cavity, and the etching gas and the oxidization film generates chemical reaction to form a protection film on the semiconductor substrate; finally, the semiconductor substrate with the protection film is taken out of the first process cavity, stored in a storage device and placed in a second process cavity to be subjected to annealing treatment after a set period of preservation time, and the protection film is removed till the surface of the semiconductor substrate is exposed. By means of the precleaning method, the precleaning effect is good, efficiency is high, pollution caused by secondary natural oxidization is not likely to happen, and the cost is lowered.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly relate to a kind of semiconductor device surface precleaning method.
Background technology
Mos field effect transistor (MOSFET) is the most important basic active device of integrated circuit, and the CMOS formed with NMOS and PMOS complementation is the component units of deep-submicron super large integrated circuit.Wherein, Si CMOS integrated circuit because having the advantages such as low-power consumption, high integration, low noise and high reliability, in occupation of ascendancy in semiconductor IC industry.But along with the increase of the reduction of the further increase of footprint, device feature size, integrated level and complexity, especially after device feature size enters nanoscale, the material of Si cmos device, the limitation of physical features progressively manifest out, limit further developing of Si integrated circuit and manufacturing process thereof.
At present, the principal element affecting cmos device performance is the mobility of charge carrier, and the mobility of charge carrier can affect the size of electric current in raceway groove.In cmos device, the decline of carrier mobility not only can reduce the switch speed of transistor, but also resistance difference when holding and close can be made to reduce.Therefore, effectively improving carrier mobility is one of emphasis of cmos device structural design.
Because electronics has different responses with the strain of hole to identical type.Such as, apply compression in the current flow direction favourable to hole mobility, but electron mobility is harmful to; And it is favourable to electron mobility to apply tensile stress, but hole mobility is harmful to.Therefore, in order to improve the mobility of charge carrier in cmos device, be generally divide out process by PMOS and NMOS.Specifically, for nmos device, introducing along channel direction the mobility that tensile stress improves electronics in its raceway groove; For PMOS device, introducing along channel direction the mobility that compression improves hole in its raceway groove.
Embedded silicon germanium technologies proposes for the mobility improving hole in PMOS device, normally grows germanium silicon by selective epitaxial technology at source-drain area, realizes channel region and introduces strain.But, if epitaxial growth germanium-silicon layer has a lot of defect, the performance of device will be made to reduce, therefore, ensure that flawless epitaxial growth germanium-silicon layer is very important to the high performance device of acquisition.But will realize flawless epitaxial growth germanium-silicon layer difficulty very large, restrictive condition is a lot, wherein, before epitaxial growth SiGe, clean is carried out to silicon face and especially show important.
SiCoNi chemistry original position pre-clean process is company of Applied Materials for 45nm and the silicon face in-situ chemical dry method pre-cleaning technique researched and developed with lower node semiconductor technology, is usually used in cobalt or nickel metal carried out precleaning to silicon face before silicon face deposition.Because SiCoNi technique has the incomparable advantage of other pre-clean process, researcher is by SiCoNi pre-clean process clean to silicon face before epitaxial growth SiGe.But; when carrying out SiCoNi pre-clean process in prior art; its reactive ion etching all completes with annealing in SiCoNi process cavity; due to annealing after silicon face without any protection; once after silicon substrate takes out from SiCoNi process cavity, just at once silicon substrate must be inserted in epitaxial chamber and carry out follow-up epitaxial growth, otherwise; can there is autoxidation and form oxide-film on its surface in silicon substrate, cause secondary pollution again.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of semiconductor device surface precleaning method, for solving the silicon chip after carrying out precleaning in prior art, the problem that autoxidation causes secondary pollution easily occurs again.
For achieving the above object and other relevant objects, the invention provides a kind of semiconductor device surface precleaning method, described precleaning method at least comprises the following steps:
1) provide and can supply pretreated substrate, described substrate comprises the oxide-film that Semiconductor substrate and autoxidation are formed in described semiconductor substrate surface;
2) place described substrate in the first process cavity, and pass into etching gas in the first process cavity, described etching gas and oxide-film generation chemical reaction form diaphragm on a semiconductor substrate;
3) Semiconductor substrate being formed with diaphragm is taken out from the first process cavity; be stored in storage device; after the holding time of setting; the Semiconductor substrate being formed with diaphragm is placed in the second process cavity and carries out annealing in process; described diaphragm is removed, until expose semiconductor substrate surface.
Preferably, described Semiconductor substrate is silicon substrate or silicon-on-insulator.
Preferably, described oxide-film is silicon dioxide.
Preferably, in described first process cavity, the etching gas comprising Nitrogen trifluoride and ammonia is passed into; Described Nitrogen trifluoride, ammonia and described silicon dioxde reaction generate ammonium hexafluorosilicate diaphragm.
Preferably, described first process cavity is SiCoNi process cavity; Described second process cavity is epitaxy technique chamber or quick thermal treatment process chamber.
Preferably, described step 2) in the thickness of diaphragm that generates of reaction be 10 ~ 100 dusts.
Preferably, the holding time scope of described setting is 1 ~ 2880 minute.
Preferably, vacuum is set in described storage device.
Preferably, the temperature of carrying out annealing in described step 3) is 60 ~ 120 DEG C, and annealing time is 10 ~ 120 seconds.
As mentioned above, semiconductor device surface precleaning method of the present invention, has following beneficial effect:
Reactive ion etching and annealing process separate and carry out in different process cavity by the present invention, wherein, reactive ion etching occurs in the first process cavity, annealing occurs in the second process cavity, the Semiconductor substrate of taking out from the first process cavity can be preserved in the storage device the long period, needs Semiconductor substrate to take out from save set afterwards put into the second process cavity and carry out annealing and the technique such as follow-up extension or rapid thermal oxidation according to technique progress.The pre-clean process method time of the present invention is controlled, and not easily again occur autoxidation pollute.
Accompanying drawing explanation
Fig. 1 is semiconductor device surface precleaning method flow chart of the present invention.
Fig. 2 is the structural representation that the step 1) of semiconductor device surface precleaning method of the present invention presents.
Fig. 3 is the structural representation that the ammonium fluoride of semiconductor device surface precleaning method of the present invention is attached to oxide-film surface.
Fig. 4 is the step 2 of semiconductor device surface precleaning method of the present invention) structural representation that presents.
Fig. 5 is the structural representation that the step 3) of semiconductor device surface precleaning method of the present invention presents.
Element numbers explanation
S1 ~ S3 step
100 substrates
1 Semiconductor substrate
2 oxide-films
3 fluorides
4 diaphragms
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The invention provides a kind of semiconductor device surface precleaning method, as shown in Figure 1, described precleaning method at least comprises the following steps:
First carry out step S1, as shown in Figure 2, provide and can supply pretreated substrate 100, described substrate 100 comprises the oxide-film 2 that Semiconductor substrate 1 and autoxidation are formed in described Semiconductor substrate 1 surface.
Described Semiconductor substrate 1 can be any known Semiconductor substrate, includes but not limited to silicon substrate or silicon-on-insulator substrate (Silicon On Insulator, SOI) substrate.In the present embodiment, described Semiconductor substrate 1 is described for silicon substrate.
Bulk silicon substrate 1 is easily oxidized under field conditions (factors), and form layer oxide film 2 on the surface of silicon substrate, this oxide-film 2 is silicon dioxide.This layer of oxide-film 2 belongs to pollutant, is that technical staff is undesirable, if there is this layer of oxide-film 2, grown layer prepared by subsequent technique then there will be the defect such as dislocation, hole.In order to avoid the defects such as dislocation appear in follow-up grown layer, the oxide-film 2 that autoxidation is formed must be removed completely.
Then perform step S2, as shown in Figure 4, placing described substrate 100 in the first process cavity, and pass into etching gas in the first process cavity, there is chemical reaction and forms diaphragm 4 on semiconductor substrate 1 in described etching gas and oxide-film 2.
In an embodiment of the present invention, described first process cavity is preferably SiCoNi process cavity, and what described etching gas adopted is Nitrogen trifluoride and ammonia, Nitrogen trifluoride (NF
3) and ammonia (NH
3) the ratio of gas flow can in 0.01 ~ 0.5 scope.The pressure of etching cavity is 1.5 ~ 10Torr(holder), the power of etching cavity is 10 ~ 100 watts, 5 ~ 60 seconds processing times.The concrete steps of etching technics comprise: first, described substrate 100 are placed in SiCoNi process cavity and are controlled on the slide glass base of 50 ~ 90 DEG C; Then, lower powered electricity slurry is adopted to change Nitrogen trifluoride and ammonia into ammonium fluoride (NH4F) and fluoram (NH4FHF).The mixed fluoride thing 3 that above-mentioned ammonium fluoride and fluoram are formed as etching agent at substrate 100 surface condensation, as shown in Figure 3, this fluoride 3 and the silicon dioxide generation chemical reaction on Semiconductor substrate 1 surface, form hexafluoro silicon ammonium ((NH4) 2SiF6).It should be noted that, the silicon dioxide on Semiconductor substrate 1 surface and fluoride 3 react form hexafluoro silicon ammonium completely, and hexafluoro silicon ammonium is covered in Semiconductor substrate 1 as diaphragm 4.In addition, react rear hexafluoro silicon ammonium diaphragm 4 and there is hydrogen base with the interface of Semiconductor substrate 1, avoid Semiconductor substrate again autoxidation to occur at short notice after the first process cavity is taken out.
The thickness range of the hexafluoro silicon ammonium diaphragm 4 generated, in 10 ~ 100 dusts, both can ensure that this diaphragm 4 was removed completely in follow-up annealing, can play again the effect of protection Semiconductor substrate 1 better.
Finally carry out step S3; as shown in Figure 5; the Semiconductor substrate 1 being formed with diaphragm 4 is taken out from the first process cavity; be stored in storage device; after the holding time of setting; the Semiconductor substrate 1 being formed with diaphragm 4 is placed in the second process cavity and carries out annealing in process, described diaphragm 4 is removed, until expose Semiconductor substrate 1 surface.
Semiconductor substrate of the prior art is just carried out annealing and to be got rid of by diaphragm in the first process cavity; after taking out from the first process cavity; Semiconductor substrate without any protection; even if be kept at there is certain vacuum degree storage device in; Semiconductor substrate still can be formed oxide-film pollution layer by autoxidation; therefore, the Semiconductor substrate of taking out in prior art must be positioned at once in the process cavity of subsequent technique and process, and the time is comparatively hurry.In the present invention, Semiconductor substrate 1 is formed with diaphragm 4; autoxidation can not be there is at short notice in the Semiconductor substrate 1 of taking out from the first process cavity; Semiconductor substrate 1 after taking-up can be stored in the storage device of vacuum the long period; the holding time scope of described setting is 1 ~ 2880 minute, and described storage device can be the specific store box storing wafer.When reaching the holding time of setting, the Semiconductor substrate 1 being formed with diaphragm 4 being put into follow-up process cavity and carries out annealing.
The Semiconductor substrate 1 of taking out from save set is placed in the second process cavity and carries out annealing in process.Wherein, described second process cavity is selected according to the needs of actual process, and if desired serve as a contrast 1 surface at clean semiconductor and carry out epitaxy technique, then the second process cavity is chosen as epitaxy technique chamber; If desired carry out quick thermal treatment process (RapidThermal Oxidation, RTO) on clean Semiconductor substrate 1 surface, then the second process cavity is chosen as quick thermal treatment process chamber.Certainly, if desired carry out other techniques, then the second process cavity is chosen as other process cavity corresponding.In the present embodiment, described second process cavity is epitaxy technique chamber.The temperature of carrying out annealing in the second process cavity is 60 ~ 120 DEG C, and annealing time can within the scope of 10 ~ 120 seconds.Directly in the second process cavity, epitaxy technique is carried out or rapid thermal oxidation process makes the corresponding epitaxial loayer of Semiconductor substrate 1 Surface Creation or oxide layer after annealing.Can find out thus, the method time of the present invention is controlled, and the precleaning effect on Semiconductor substrate 1 surface is also better, and device performance also just significantly promotes.
Embodiment two
The present invention also provides a kind of semiconductor device surface precleaning device, by means of this precleaning device, the precleaning method that can more efficiently utilize embodiment one to provide carries out precleaning to Semiconductor substrate 1 surface, and can improve the process efficiency of the subsequent techniques such as extension, this precleaning device at least comprises:
First process cavity, placement can supply pretreated substrate 100, described substrate 100 comprises the oxide-film 2 that Semiconductor substrate 1 and autoxidation are formed in described Semiconductor substrate 1 surface, there is chemical reaction and form diaphragm 4 on semiconductor substrate 1 in the etching gas in the first process cavity and oxide-film 2, as shown in Figure 2 and Figure 4;
Storage device, preserves the Semiconductor substrate 1 being formed with diaphragm 4 of taking out from described first process cavity;
Second process cavity, places the Semiconductor substrate 1 being formed with diaphragm 4, in the second process cavity, carries out annealing in process, removes the diaphragm 4 in Semiconductor substrate 1, obtains the Semiconductor substrate 1 of surface cleaning, as shown in Figure 5.
Further; described second process cavity and storage device are arranged on same board; when needing to carry out the technique such as extension or rapid thermal oxidation; mechanical arm is utilized the Semiconductor substrate 1 with diaphragm 4 to be taken out from storage device; put into the second process cavity; so just can ensure to carry the distance of Semiconductor substrate 1 shorter, reduce Semiconductor substrate 1 further again by the risk of autoxidation.
Further, described first process cavity is separated with the second process cavity place board.In prior art, the first process cavity and the second process cavity are integrated on same board, mainly in order to make the Semiconductor substrate that cleans can fast to arrival second process cavity after the first process cavity annealing.And Semiconductor substrate 1 surface of the present invention has diaphragm 4, the longer time can be stopped natural environment after the first process cavity is taken out, therefore, the first process cavity and the second process cavity and storage device place board can be separated.Because the first process cavity does not take the position of board, just can integrated more second process cavity on board.For epitaxy technique, traditional board is two epitaxy technique chambeies, first process cavity (as SiCoNi pre-clean process chamber), in the present invention, the first process cavity is moved away from, vacate board position, then can simultaneously integrated three epitaxial chamber on a board, the wafer once carrying out epitaxy technique also just increases, improve process efficiency, shorten the process time, reduce costs.
In sum, the invention provides a kind of semiconductor device surface precleaning method, reactive ion etching and annealing process are separated and carries out in different process cavity, wherein, reactive ion etching occurs in the first process cavity, annealing occurs in the second process cavity, the Semiconductor substrate of taking out from the first process cavity can be preserved in the storage device the long period, needs Semiconductor substrate to take out from save set afterwards put into the second process cavity and carry out annealing and the technique such as follow-up extension or rapid thermal oxidation according to technique progress.The pre-clean process method time of the present invention is controlled, and not easily again occur autoxidation pollute.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a semiconductor device surface precleaning method, is characterized in that, described precleaning method at least comprises step:
1) provide and can supply pretreated substrate, described substrate comprises the oxide-film that Semiconductor substrate and autoxidation are formed in described semiconductor substrate surface;
2) place described substrate in the first process cavity, and pass into etching gas in the first process cavity, described etching gas and oxide-film generation chemical reaction form diaphragm on a semiconductor substrate;
3) Semiconductor substrate being formed with diaphragm is taken out from the first process cavity; be stored in storage device; after the holding time of setting; the Semiconductor substrate being formed with diaphragm is placed in the second process cavity and carries out annealing in process; described diaphragm is removed, until expose semiconductor substrate surface.
2. semiconductor device surface precleaning method according to claim 1, is characterized in that: described Semiconductor substrate is silicon substrate or silicon-on-insulator.
3. semiconductor device surface precleaning method according to claim 1, is characterized in that: described oxide-film is silicon dioxide.
4. semiconductor device surface precleaning method according to claim 3, is characterized in that: in described first process cavity, pass into the etching gas comprising Nitrogen trifluoride and ammonia; Described Nitrogen trifluoride, ammonia and described silicon dioxde reaction generate ammonium hexafluorosilicate diaphragm.
5. semiconductor device surface precleaning method according to claim 1, is characterized in that: described first process cavity is SiCoNi process cavity; Described second process cavity is epitaxy technique chamber or quick thermal treatment process chamber.
6. semiconductor device surface precleaning method according to claim 1, is characterized in that: described step 2) in the thickness of diaphragm that generates of reaction be 10 ~ 100 dusts.
7. semiconductor device surface precleaning method according to claim 1, is characterized in that: the holding time scope of described setting 1 ~ 2880 minute.
8. semiconductor device surface precleaning method according to claim 1, is characterized in that: be set to vacuum in described storage device.
9. semiconductor device surface precleaning method according to claim 1, is characterized in that: the temperature of carrying out in described step 3) annealing is 60 ~ 120 DEG C, and annealing time is 10 ~ 120 seconds.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022166087A1 (en) * | 2021-02-03 | 2022-08-11 | 长鑫存储技术有限公司 | Cleaning process and semiconductor process method |
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Application publication date: 20150624 |