CN104660242A - Pull-up resistor circuit - Google Patents
Pull-up resistor circuit Download PDFInfo
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- CN104660242A CN104660242A CN201310582339.2A CN201310582339A CN104660242A CN 104660242 A CN104660242 A CN 104660242A CN 201310582339 A CN201310582339 A CN 201310582339A CN 104660242 A CN104660242 A CN 104660242A
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Abstract
The invention relates to a pull-up resistor circuit. The pull-up resistor circuit comprises a power supply end, an output end, a first positive channel metal oxide semiconductor (PMOS) and a transmission unit. The source electrode of the first PMOS is connected with the power supply end. The drain electrode of the first PMOS is connected with the output end. The substrate of the first PMOS is suitable for inputting bias voltage. The voltage value of the bias voltage is equal to the voltage value of the larger voltage of the voltage of the power supply end and the voltage of the output end. The transmission unit is suitable for transmitting a pull-up control signal to the gate electrode of the first PMOS when the voltage of the power supply end is greater than or equal to the voltage of the output end, and transmitting the voltage of the output end to the gate electrode of the first PMOS when the voltage of the power supply end is less than the voltage of the output end. The pull-up resistor circuit does not generate reverse current when working in a high voltage tolerant mode, thereby improving the reliability of the overall integrated circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of pull-up resistor circuit.
Background technology
Pull-up resistor circuit is widely used in integrated circuit, especially applies more in I/O circuit.Many I/O ports need the high level arranging an acquiescence usually, when some does not have signal to input, by pull-up resistor circuit, I/O port are pulled to high potential.
Fig. 1 is existing a kind of pull-up resistor circuit.With reference to figure 1, described pull-up resistor circuit comprises power end VDD, output OUT and PMOS MP0.The source electrode of described PMOS MP0 is connected described power end VDD with substrate, the drain electrode of described PMOS MP0 connects described output OUT, and the grid of described PMOS MP0 is suitable for input control signal RE.Described power end VDD is suitable for receiving supply voltage, and described output OUT connects the I/O port of integrated circuit.
In the normal mode, namely be more than or equal to the voltage condition of described output OUT at the voltage of described power end VDD under, when described control signal RE is low level signal, described PMOS MP0 conducting, the current potential of described output OUT is pulled to equal with the current potential of described power end VDD; When described control signal RE is high level signal, described PMOS MP0 cut-off, pull-up function is invalid.
But, under high pressure margin mode, namely the voltage on described output OUT higher than during voltage on described power end VDD (such as, described supply voltage is generally 3.3V, and the voltage in bus is 5V, when described output OUT is connected with bus), even if described control signal RE is high level signal, because the voltage of described high level signal can not higher than described supply voltage, described PMOS MP0 still can conducting, causes producing the reverse irrigated current flowing to described power end VDD from described output OUT.
Summary of the invention
What the present invention solved is the problem that pull-up resistor circuit produces reverse irrigated current under high pressure margin mode.
For solving the problem, the invention provides a kind of pull-up resistor circuit, comprising: power end, output, the first PMOS and transmission unit;
The source electrode of described first PMOS connects described power end, the drain electrode of described first PMOS connects described output, the substrate of described first PMOS is suitable for input offset voltage, and in the voltage of the magnitude of voltage of described bias voltage and the voltage of described power end and described output, the magnitude of voltage of larger voltage is equal;
Described transmission unit is suitable for the grid when the voltage of described power end is more than or equal to the voltage of described output, pull-up control signal being transferred to described first PMOS, when the voltage of described power end is less than the voltage of described output by the voltage transmission of described output to the grid of described first PMOS.
Optionally, described power end is suitable for input supply voltage, and described output connects the I/O port of integrated circuit.
Optionally, described transmission unit comprises the second PMOS, the 3rd PMOS and control signal generation unit;
The grid of described second PMOS is suitable for inputting grid control signal, and the drain electrode of described second PMOS is suitable for inputting described pull-up control signal, and the source electrode of described second PMOS connects the substrate of described second PMOS and the grid of described first PMOS;
The grid of described 3rd PMOS connects described power end, and the drain electrode of described 3rd PMOS connects described output, and the source electrode of described 3rd PMOS connects the grid of described first PMOS, and the substrate of described 3rd PMOS is suitable for inputting described bias voltage;
Described control signal generation unit is suitable for producing described grid control signal, when the voltage of described power end is more than or equal to the voltage of described output, described grid control signal is low level signal, and when the voltage of described power end is less than the voltage of described output, the amplitude of described grid control signal is equal with the magnitude of voltage of described output.
Optionally, described control signal generation unit comprises the first switch element and second switch unit;
Between the grid that described first switch element is connected to described second PMOS and described output, between the grid that described second switch unit is connected to described second PMOS and ground, impedance during described second switch cell conduction is greater than impedance during described first switching means conductive;
Described first switch element is suitable for disconnection, the conducting when the voltage of described power end is less than the voltage of described output when the voltage of described power end is more than or equal to the voltage of described output;
Described second switch unit is suitable for the conducting when the voltage of described power end is more than or equal to the voltage of described output.
Optionally, described first switch element comprises the 4th PMOS;
The grid of described 4th PMOS connects described power end, and the source electrode of described 4th PMOS connects the grid of described second PMOS, and the drain electrode of described 4th PMOS connects described output, and the substrate of described 4th PMOS is suitable for inputting described bias voltage.
Optionally, described second switch unit comprises the 5th PMOS and the first NMOS tube;
The grid of described 5th PMOS connects the drain electrode of described 5th PMOS and the drain electrode of described first NMOS tube, and the source electrode of described 5th PMOS connects the grid of described second PMOS, and the substrate of described 5th PMOS is suitable for inputting described bias voltage;
The grid of described first NMOS tube connects described power end, the source electrode of described first NMOS tube and the Substrate ground of described first NMOS tube.
Optionally, described second switch unit comprises the second NMOS tube and the 3rd NMOS tube;
The grid of described second NMOS tube connects the grid of described power end and described 3rd NMOS tube, the drain electrode of described second NMOS tube connects the grid of described second PMOS, the source electrode of described second NMOS tube connects the drain electrode of described 3rd NMOS tube, and the substrate of described second NMOS tube connects the substrate of described 3rd NMOS tube and the source electrode of described 3rd NMOS tube and ground connection.
Optionally, described pull-up resistor circuit also comprises the bias-voltage generating circuit being suitable for producing described bias voltage, and described bias-voltage generating circuit comprises the 6th PMOS and the 7th PMOS;
The grid of described 6th PMOS connects the drain electrode of described 7th PMOS and described output, the source electrode of described 6th PMOS connects the grid of described power end and described 7th PMOS, and the drain electrode of described 6th PMOS connects the substrate of the source electrode of described 7th PMOS, the substrate of described 6th PMOS and described 7th PMOS and is suitable for exporting described bias voltage.
Compared with prior art, technical scheme of the present invention has the following advantages:
The pull-up resistor circuit that technical solution of the present invention provides comprises the first PMOS and transmission unit, the substrate of described first PMOS is suitable for input offset voltage, in the voltage of the magnitude of voltage of described bias voltage and the voltage of power end and output, the magnitude of voltage of larger voltage is equal, and described transmission unit is suitable for the grid voltage of pull-up control signal or output being exported to described first PMOS.
In the normal mode, pull-up control signal is transferred to the grid of described first PMOS by described transmission unit, and when described pull-up control signal is low level signal, described first PMOS conducting, realizes pull-up function; When described pull-up control signal is high level signal, described first PMOS cut-off, pull-up function is invalid.
Under high pressure margin mode, described transmission unit by the voltage transmission of output to the grid of described first PMOS, because bias voltage described under high pressure margin mode is equal with the voltage of described output, the current potential of the grid of described first PMOS, drain electrode and substrate is equal, in conducting channel, no current produces, i.e. described first PMOS cut-off.Therefore, described pull-up resistor circuit produces without reverse irrigated current, improves the reliability of whole integrated circuit.
Further, the pull-up resistor circuit that technical solution of the present invention provides is under high pressure margin mode, described transmission unit forbids the grid described pull-up control signal being transferred to described first PMOS, no matter whether described pull-up control signal is low level, all produce without reverse irrigated current, therefore, the state eliminating reverse irrigated current and described pull-up control signal has nothing to do.
Accompanying drawing explanation
Fig. 1 is existing a kind of pull-up resistor circuit;
Fig. 2 is the structural representation of the pull-up resistor circuit of embodiment of the present invention;
Fig. 3 is the circuit diagram of the pull-up resistor circuit of the embodiment of the present invention 1;
Fig. 4 is the circuit diagram of the pull-up resistor circuit of the embodiment of the present invention 2;
Fig. 5 is the circuit diagram of the bias-voltage generating circuit of the embodiment of the present invention 3.
Embodiment
Just as described in the background art, existing pull-up resistor circuit, under high pressure margin mode, can produce the reverse irrigated current being flowed to power end by output.Power end is suitable for receiving supply voltage, and the generation of reverse irrigated current can make described supply voltage raise, and affects the reliability of the whole integrated circuit of being powered by described supply voltage.
Fig. 2 is the structural representation of the pull-up resistor circuit that technical solution of the present invention provides.With reference to figure 2, described pull-up resistor circuit comprises power end VDD, output OUT, the first PMOS MP1 and transmission unit 20.
Described power end VDD is suitable for input supply voltage, and namely described power end VDD is suitable for connecting power supply.Described pull-up resistor circuit is applied in I/O circuit usually, and therefore, described output OUT connects the I/O port of integrated circuit usually.
The source electrode of described first PMOS MP1 connects described power end VDD, and the drain electrode of described first PMOS MP1 connects described output OUT, and the substrate of described first PMOS MP1 is suitable for input offset voltage Vbias.
In the voltage of the magnitude of voltage of described bias voltage Vbias and the voltage of described power end VDD and described output OUT, the magnitude of voltage of larger voltage is equal, namely, when the voltage of described power end VDD is greater than the voltage of described output OUT, described bias voltage Vbias is equal with the voltage of described power end VDD; When the voltage of described output OUT is greater than the voltage of described power end VDD, described bias voltage Vbias is equal with the voltage of described output OUT.
Described transmission unit 20 is suitable for the voltage transmission of pull-up control signal REN or described output OUT to the grid of described first PMOS.Described pull-up control signal REN is also referred to as pull-up enable signal usually, and whether the pull-up function being suitable for controlling described pull-up resistor circuit is effective.
The signal that described transmission unit 20 transmits is relevant to the mode of operation of described pull-up resistor circuit.Pull-up resistor circuit has two kinds of mode of operations usually: normal mode and high pressure margin mode, and when normal mode and pull-up resistor circuit working, the voltage of described power end VDD is more than or equal to the voltage of described output OUT; When high pressure margin mode and pull-up resistor circuit working, the voltage of described output OUT is greater than the voltage of described power end VDD.Usually, under high pressure margin mode, the missionary society of the voltage of described output OUT and the voltage of described power end VDD is greater than the threshold voltage of metal-oxide-semiconductor.
In the normal mode, namely when the voltage of described power end VDD is more than or equal to the voltage of described output OUT, described transmission unit 20 is suitable for the grid described pull-up control signal REN being transferred to described first PMOS MP1; Under high pressure margin mode, namely when the voltage of described output OUT is greater than the voltage of described power end VDD, described transmission unit 20 is suitable for the voltage transmission of described output OUT to the grid of described first PMOS MP1.
Below the operation principle of the pull-up resistor circuit of embodiment of the present invention is described.
In the normal mode, the voltage of described power end VDD is more than or equal to the voltage of described output OUT, described bias voltage Vbias is equal with the voltage of described power end VDD, and described pull-up control signal REN is transferred to the grid of described first PMOS MP1 by described transmission unit 20.When described pull-up control signal REN is low level signal, described first PMOS MP1 conducting, the current potential of described output OUT is pulled to equal with the current potential of described power end VDD; When described pull-up control signal REN is high level signal, described first PMOS MP1 cut-off, pull-up function is invalid.
Under high pressure margin mode, the voltage of described output OUT is greater than the voltage of described power end VDD, described bias voltage Vbias is equal with the voltage of described output OUT, described transmission unit 20 by the voltage transmission of described output OUT to the grid of described first PMOS MP1.Therefore, the voltage on the grid of described first PMOS MP1, drain electrode and substrate is all equal with the voltage on described output OUT.No matter which kind of state described pull-up control signal REN is, voltage difference between the grid of described first PMOS MP1 and drain electrode and the voltage difference between substrate and drain electrode are 0, in the conducting channel of described first PMOS MP1, no current produces, namely described first PMOS MP1 cut-off, can not produce the reverse irrigated current being flowed to described power end VDD by described output OUT.
Based on above-mentioned analysis, when the pull-up resistor circuit working that embodiment of the present invention provides is under high pressure margin mode, the reverse irrigated current being flowed to described power end VDD by described output OUT can not be produced, improve the reliability of whole integrated circuit.Further, the state eliminating reverse irrigated current and described pull-up control signal REN has nothing to do.
Continue reference with reference to figure 2, in the present embodiment, described transmission unit 20 comprises the second PMOS MP2, the 3rd PMOS MP3 and control signal generation unit 21.
The grid of described second PMOS MP2 is suitable for input grid control signal Vg, the drain electrode of described second PMOS MP2 is suitable for inputting described pull-up control signal REN, and the source electrode of described second PMOS MP2 connects the substrate of described second PMOS MP2 and the grid of described first PMOS MP1.
The grid of described 3rd PMOS MP3 connects described power end VDD, the drain electrode of described 3rd PMOS MP3 connects described output OUT, the source electrode of described 3rd PMOS MP3 connects the grid of described first PMOS MP1, and the substrate of described 3rd PMOS MP3 is suitable for inputting described bias voltage Vbias.
Described control signal generation unit 21 is suitable for producing described grid control signal Vg.In the normal mode, namely when the voltage of described power end VDD is more than or equal to the voltage of described output OUT, described grid control signal Vg is low level signal; Under high pressure margin mode, namely when the voltage of described output OUT is greater than the voltage of described power end VDD, the amplitude of described grid control signal Vg is equal with the magnitude of voltage of described output OUT.
Described control signal generation unit 21 comprises the first switch element 22 and second switch unit 23.Described first switch element 21 is connected between the grid of described second PMOS MP2 and described output OUT, between the grid that described second switch unit 23 is connected to described second PMOS MP2 and ground, impedance during 23 conducting of described second switch unit is greater than impedance during described first switch element 22 conducting.Therefore, when described first switch element 22 and the conducting simultaneously of described second switch unit 23, described grid control signal Vg is the signal that described first switch element 22 transmits.
Particularly, one end of described first switch element 22 connects one end of described second switch unit 23 and is suitable for producing described grid control signal Vg, the other end of described first switch element 22 connects described output OUT, the other end ground connection of described second switch unit 23.
Described first switch element 22 is suitable for disconnecting when the voltage of described power end VDD is more than or equal to the voltage of described output OUT, the conducting when the voltage of described power end VDD is less than the voltage of described output OUT; Described second switch unit 23 is suitable for the conducting when the voltage of described power end VDD is more than or equal to the voltage of described output OUT.
In the normal mode, namely when the voltage of described power end VDD is more than or equal to the voltage of described output OUT, described bias voltage Vbias is equal with the voltage of described power end VDD, therefore, and described 3rd PMOS MP3 cut-off.Simultaneously, due to described first switch element 22 disconnect, the conducting of described second switch unit 23, the grid control signal Vg that described control signal generation unit 22 provides is low level signal, therefore, described second PMOS MP2 conducting, transfers to the grid of described first PMOS MP1 by described pull-up control signal REN.
Under high pressure margin mode, namely when the voltage of described output OUT is greater than the voltage of described power end VDD, described bias voltage Vbias is equal with the voltage of described output OUT.Due to described first switch element 22 conducting, impedance during described first switch element 22 conducting is less than impedance during 23 conducting of described second switch unit, no matter described second switch unit 23 whether conducting, the voltage of described output OUT is exported to the grid of described second PMOS MP2 by described first switch element 22, and namely the amplitude of described grid control signal Vg is equal with the magnitude of voltage of described output OUT.Therefore, described second PMOS MP2 cut-off, described 3rd PMOS MP3 conducting, by the voltage transmission of described output OUT to the grid of described first PMOS MP1.
Described control signal generation unit 21 has multiple implementation, and for enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Embodiment 1
Fig. 3 is the circuit diagram of the pull-up resistor circuit of the present embodiment.With reference to figure 3, described pull-up resistor circuit comprises power end VDD, output OUT, the first PMOS MP1 and transmission unit.Described transmission unit comprises the second PMOS MP2, the 3rd PMOS MP3 and control signal generation unit, and described control signal generation unit comprises the first switch element 31 and second switch unit 32.Described power end VDD, output OUT, the first PMOS MP1, the second PMOS MP2 and the 3rd PMOS MP3 and Fig. 2 are similar, are not repeating at this.
In the present embodiment, described first switch element 31 comprises the 4th PMOS MP4, described second switch unit 32 comprises the 5th PMOS MP5 and the first NMOS tube MN1, and impedance during described first switch element 31 conducting is less than impedance during 32 conducting of described second switch unit.
Described first switch element 31 and described second switch unit 32 are all be made up of metal-oxide-semiconductor, therefore, impedance during described first switch element 31 conducting is relevant to the breadth length ratio of described 4th PMOS MP4, and impedance during 32 conducting of described second switch unit is relevant with the breadth length ratio of described first NMOS tube MN1 to the breadth length ratio of described 5th PMOS MP5.
Particularly, the grid of described 4th PMOS MP4 connects described power end VDD; The source electrode of described 4th PMOS MP4 connects the grid of described second PMOS MP2; The drain electrode of described 4th PMOS MP4 connects described output OUT; The substrate of described 4th PMOS MP4 is suitable for input offset voltage Vbias, and in the voltage of the magnitude of voltage of described bias voltage Vbias and the voltage of described power end VDD and described output OUT, the magnitude of voltage of larger voltage is equal.
The grid of described 5th PMOS MP5 connects the drain electrode of described 5th PMOS MP5 and the drain electrode of described first NMOS tube MN1; The source electrode of described 5th PMOS MP5 connects the grid of described second PMOS MP2; The substrate of described 5th PMOS MP5 is suitable for inputting described bias voltage Vbias.
The grid of described first NMOS tube MN1 connects described power end VDD; The source electrode of described first NMOS tube MN1 and the Substrate ground of described first NMOS tube MN1.
Below the operation principle of the pull-up resistor circuit of the present embodiment is described.
In the normal mode, the voltage of described power end VDD is more than or equal to the voltage of described output OUT, and described bias voltage Vbias is equal with the voltage of described power end VDD.Therefore, described 3rd PMOS MP3 and described 4th PMOS MP4 cut-off, described 5th PMOS MP5 and the first NMOS tube MN1 conducting, namely described first switch element 31 disconnect, the conducting of described second switch unit 32, the grid control signal Vg that described control signal generation unit provides is low level signal, pull-up control signal REN, because of grid conducting by dragging down, is transferred to the grid of described first PMOS MP1 by described second PMOS MP2.
When described pull-up control signal REN is low level signal, described first PMOS MP1 conducting, the current potential of described output OUT is pulled to equal with the current potential of described power end VDD; When described pull-up control signal REN is high level signal, described first PMOS MP1 cut-off, pull-up function is invalid.
Under high pressure margin mode, the voltage of described output OUT is greater than the voltage of described power end VDD, and described bias voltage Vbias is equal with the voltage of described output OUT, described 4th PMOS MP4 conducting, i.e. described first switch element 31 conducting.Due to impedance when impedance during described first switch element 31 conducting is less than 32 conducting of described second switch unit, therefore, when described first switch element 31 conducting, no matter described second switch unit 32 whether conducting, the grid potential of described second PMOS MP2 is pulled to equal with the current potential of described output OUT by described first switch element 31, namely the level of described grid control signal Vg is equal with the magnitude of voltage of described output OUT, described second PMOS MP2 cut-off.
Further, the voltage of described output OUT is greater than the voltage of described power end VDD, described 3rd PMOS MP3 conducting, by the voltage transmission on described output OUT to the grid of described first PMOS MP1.Because described bias voltage Vbias is also equal with the voltage of described output OUT, therefore, the voltage on the grid of described first PMOS MP1, drain electrode and substrate is all equal with the voltage on described output UT.No matter which kind of state described pull-up control signal REN is, voltage difference between the grid of described first PMOS MP1 and drain electrode and the voltage difference between substrate and drain electrode are 0, in the conducting channel of described first PMOS MP1, no current produces, namely described first PMOS MP1 cut-off, can not produce the reverse irrigated current being flowed to described power end VDD by described output OUT.
Under high pressure margin mode, described 5th PMOS MP5 and the equal conducting of described first NMOS tube MN1.By the dividing potential drop of described 5th PMOS MP5 and described first NMOS tube MN1, voltage difference between the drain electrode of described 5th PMOS MP5 and source electrode and the voltage difference between the drain electrode of described first NMOS tube MN1 and source electrode are all approximately the half of the voltage of described output OUT, namely described 5th PMOS MP5 and described first NMOS tube MN1 is all within reliable operating voltage range, ensure that the reliability of described 5th PMOS MP5 and described first NMOS tube MN1.
Embodiment 2
Fig. 4 is the circuit diagram of the pull-up resistor circuit of the present embodiment.With reference to figure 4, described pull-up resistor circuit comprises power end VDD, output OUT, the first PMOS MP1 and transmission unit, and described transmission unit comprises the second PMOS MP2, the 3rd PMOS MP3 and control signal generation unit.
Described power end VDD, output OUT, the first PMOS MP1, the second PMOS MP2 and the 3rd PMOS MP3 and Fig. 2 are similar, are not repeating at this.Described control signal generation unit comprises the first switch element 41 and second switch unit 42, and described first switch element 41 comprises the 4th PMOS MP4, and described 4th PMOS MP4 can description in reference example 1.
Described second switch unit 42 comprises the second NMOS tube MN2 and the 3rd NMOS tube MN3.
Particularly, the grid of described second NMOS tube MN2 connects the grid of described power end VDD and described 3rd NMOS tube MN3; The drain electrode of described second NMOS tube MN2 connects described second PMOS MP2 grid; The source electrode of described second NMOS tube MN2 connects the drain electrode of described 3rd NMOS tube MN3; The substrate of described second NMOS tube MN2 connects the substrate of described 3rd NMOS tube MN3 and the source electrode of described 3rd NMOS tube MN3 and ground connection.
The operation principle of the pull-up resistor circuit of the present embodiment is similar to Example 1.
In the normal mode, described 3rd PMOS MP3 and described 4th PMOS MP4 cut-off, described second NMOS tube MN2 and the 3rd NMOS tube MN3 conducting, the grid control signal Vg that described control signal generation unit provides is low level signal, pull-up control signal REN, because of grid conducting by dragging down, is transferred to the grid of described first PMOS by described second PMOS MP2.
When described pull-up control signal REN is low level signal, described first PMOS MP1 conducting, the current potential of described output OUT is pulled to equal with the current potential of described power end VDD; When described pull-up control signal REN is high level signal, described first PMOS MP1 cut-off, pull-up function is invalid.
Under high pressure margin mode, described 4th PMOS MP4 conducting, the amplitude of described grid control signal Vg is equal with the magnitude of voltage of described output OUT, therefore, described second PMOS MP2 cut-off.Described 3rd PMOS MP3 conducting, by the voltage transmission of described output OUT to the grid of described first PMOS, make the voltage on the grid of described first PMOS MP1, drain electrode and substrate all equal with the voltage on described output OUT, in the conducting channel of described first PMOS MP1, no current produces, namely described first PMOS MP1 cut-off, can not produce the reverse irrigated current being flowed to described power end VDD by described output OUT.
Under high pressure margin mode, described second NMOS tube MN2 and the equal conducting of described 3rd NMOS tube MN3.By the dividing potential drop of described second NMOS tube MN2 and described 3rd NMOS tube MN3, voltage difference between the drain electrode of the voltage difference between the drain electrode of described second NMOS tube MN2 and source electrode and described 3rd NMOS tube MN3 and source electrode is all approximately the half of the voltage of described output OUT, namely described second NMOS tube MN2 and described 3rd NMOS tube MN3 is all within reliable operating voltage range, ensure that the reliability of described second NMOS tube MN2 and described 3rd NMOS tube MN3.
Embodiment 3
The pull-up resistor circuit of the present embodiment comprises power end, output, the first PMOS and transmission unit, also comprises the bias-voltage generating circuit being suitable for producing bias voltage Vbias.Described power end, output, the first PMOS and transmission unit and embodiment 1 and embodiment 2 similar, do not repeating at this.
Fig. 5 is the circuit diagram of the bias-voltage generating circuit of the present embodiment.With reference to figure 5, described bias-voltage generating circuit comprises the 6th PMOS MP6 and the 7th PMOS MP7.
Particularly, the grid of described 6th PMOS MP6 connects drain electrode and the output OUT of described 7th PMOS MP7, the source electrode of described 6th PMOS MP6 connects the grid of power end VDD and described 7th PMOS MP7, and the drain electrode of described 6th PMOS MP6 connects the substrate of the source electrode of described 6th PMOS MP6, the substrate of described 6th PMOS MP6 and described 7th PMOS MP7 and is suitable for exporting described bias voltage Vbias.
When the voltage of described power end VDD is more than or equal to the voltage of described output OUT, described 6th PMOS MP6 conducting, the drain voltage of described 6th PMOS MP6 is equal with the voltage of described power end VDD, and namely the bias voltage Vbias of described bias-voltage generating circuit output is equal with the voltage of described power end VDD;
When the voltage of described output OUT is greater than the voltage of described power end VDD, described 7th PMOS MP7 conducting, the source voltage of described 7th PMOS MP7 is equal with the voltage of described output OUT, and namely the bias voltage Vbias of described bias-voltage generating circuit output is equal with the voltage of described output OUT.
In sum, the pull-up resistor circuit that technical solution of the present invention provides, when high pressure margin mode, produces without reverse irrigated current, improves the reliability of whole integrated circuit.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a pull-up resistor circuit, is characterized in that, comprises power end, output, the first PMOS and transmission unit;
The source electrode of described first PMOS connects described power end, the drain electrode of described first PMOS connects described output, the substrate of described first PMOS is suitable for input offset voltage, and in the voltage of the magnitude of voltage of described bias voltage and the voltage of described power end and described output, the magnitude of voltage of larger voltage is equal;
Described transmission unit is suitable for the grid when the voltage of described power end is more than or equal to the voltage of described output, pull-up control signal being transferred to described first PMOS, when the voltage of described power end is less than the voltage of described output by the voltage transmission of described output to the grid of described first PMOS.
2. pull-up resistor circuit as claimed in claim 1, it is characterized in that, described power end is suitable for input supply voltage, and described output connects the I/O port of integrated circuit.
3. pull-up resistor circuit as claimed in claim 1, it is characterized in that, described transmission unit comprises the second PMOS, the 3rd PMOS and control signal generation unit;
The grid of described second PMOS is suitable for inputting grid control signal, and the drain electrode of described second PMOS is suitable for inputting described pull-up control signal, and the source electrode of described second PMOS connects the substrate of described second PMOS and the grid of described first PMOS;
The grid of described 3rd PMOS connects described power end, and the drain electrode of described 3rd PMOS connects described output, and the source electrode of described 3rd PMOS connects the grid of described first PMOS, and the substrate of described 3rd PMOS is suitable for inputting described bias voltage;
Described control signal generation unit is suitable for producing described grid control signal, when the voltage of described power end is more than or equal to the voltage of described output, described grid control signal is low level signal, and when the voltage of described power end is less than the voltage of described output, the amplitude of described grid control signal is equal with the magnitude of voltage of described output.
4. pull-up resistor circuit as claimed in claim 3, it is characterized in that, described control signal generation unit comprises the first switch element and second switch unit;
Between the grid that described first switch element is connected to described second PMOS and described output, between the grid that described second switch unit is connected to described second PMOS and ground, impedance during described second switch cell conduction is greater than impedance during described first switching means conductive;
Described first switch element is suitable for disconnection, the conducting when the voltage of described power end is less than the voltage of described output when the voltage of described power end is more than or equal to the voltage of described output;
Described second switch unit is suitable for the conducting when the voltage of described power end is more than or equal to the voltage of described output.
5. pull-up resistor circuit as claimed in claim 4, it is characterized in that, described first switch element comprises the 4th PMOS;
The grid of described 4th PMOS connects described power end, and the source electrode of described 4th PMOS connects the grid of described second PMOS, and the drain electrode of described 4th PMOS connects described output, and the substrate of described 4th PMOS is suitable for inputting described bias voltage.
6. pull-up resistor circuit as claimed in claim 4, it is characterized in that, described second switch unit comprises the 5th PMOS and the first NMOS tube;
The grid of described 5th PMOS connects the drain electrode of described 5th PMOS and the drain electrode of described first NMOS tube, and the source electrode of described 5th PMOS connects the grid of described second PMOS, and the substrate of described 5th PMOS is suitable for inputting described bias voltage;
The grid of described first NMOS tube connects described power end, the source electrode of described first NMOS tube and the Substrate ground of described first NMOS tube.
7. pull-up resistor circuit as claimed in claim 4, it is characterized in that, described second switch unit comprises the second NMOS tube and the 3rd NMOS tube;
The grid of described second NMOS tube connects the grid of described power end and described 3rd NMOS tube, the drain electrode of described second NMOS tube connects the grid of described second PMOS, the source electrode of described second NMOS tube connects the drain electrode of described 3rd NMOS tube, and the substrate of described second NMOS tube connects the substrate of described 3rd NMOS tube and the source electrode of described 3rd NMOS tube and ground connection.
8. pull-up resistor circuit as claimed in claim 3, it is characterized in that, described control signal generation unit comprises the 4th PMOS, the 5th PMOS and the first NMOS tube;
The grid of described 4th PMOS connects described power end, the source electrode of described 4th PMOS connects the grid of described second PMOS, the drain electrode of described 4th PMOS connects described output, and the substrate of described 4th PMOS connects the substrate of described 5th PMOS and is suitable for inputting described bias voltage;
The grid of described 5th PMOS connects the drain electrode of described 5th PMOS and the drain electrode of described first NMOS tube, and the source electrode of described 5th PMOS connects the grid of described second PMOS;
The grid of described first NMOS tube connects described power end, the source electrode of described first NMOS tube and the Substrate ground of described first NMOS tube.
9. pull-up resistor circuit as claimed in claim 3, it is characterized in that, described control signal generation unit comprises the 4th PMOS, the second NMOS tube and the 3rd NMOS tube;
The grid of described 4th PMOS connects described power end, and the source electrode of described 4th PMOS connects the grid of described second PMOS, and the drain electrode of described 4th PMOS connects described output, and the substrate of described 4th PMOS is suitable for inputting described bias voltage;
The grid of described second NMOS tube connects the grid of described power end and described 3rd NMOS tube, the drain electrode of described second NMOS tube connects the grid of described second PMOS, the source electrode of described second NMOS tube connects the drain electrode of described 3rd NMOS tube, and the substrate of described second NMOS tube connects the substrate of described 3rd NMOS tube and the source electrode of described 3rd NMOS tube and ground connection.
10. pull-up resistor circuit as claimed in claim 1, it is characterized in that, also comprise the bias-voltage generating circuit being suitable for producing described bias voltage, described bias-voltage generating circuit comprises the 6th PMOS and the 7th PMOS;
The grid of described 6th PMOS connects the drain electrode of described 7th PMOS and described output, the source electrode of described 6th PMOS connects the grid of described power end and described 7th PMOS, and the drain electrode of described 6th PMOS connects the substrate of the source electrode of described 7th PMOS, the substrate of described 6th PMOS and described 7th PMOS and is suitable for exporting described bias voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310582339.2A CN104660242B (en) | 2013-11-19 | 2013-11-19 | Pull-up resistor circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310582339.2A CN104660242B (en) | 2013-11-19 | 2013-11-19 | Pull-up resistor circuit |
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| Publication Number | Publication Date |
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| CN104660242A true CN104660242A (en) | 2015-05-27 |
| CN104660242B CN104660242B (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310582339.2A Active CN104660242B (en) | 2013-11-19 | 2013-11-19 | Pull-up resistor circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108123708A (en) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of pull-up circuit for I/O circuit |
| CN110798202A (en) * | 2019-12-13 | 2020-02-14 | 武汉新芯集成电路制造有限公司 | Pull-up circuit |
| CN114625685A (en) * | 2022-03-01 | 2022-06-14 | 厦门智多晶科技有限公司 | IO circuit with hot plug function, chip and power supply control method of IO circuit |
| WO2022193181A1 (en) * | 2021-03-17 | 2022-09-22 | 华为技术有限公司 | Interface circuit and control method thereof, chip, terminal device |
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| US5933027A (en) * | 1997-03-14 | 1999-08-03 | Lucent Technologies Inc. | High-voltage-tolerant output buffers in low-voltage technology |
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| US4963766A (en) * | 1989-06-28 | 1990-10-16 | Digital Equipment Corporation | Low-voltage CMOS output buffer |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108123708A (en) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of pull-up circuit for I/O circuit |
| CN108123708B (en) * | 2016-11-29 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | Pull-up circuit for IO circuit |
| CN110798202A (en) * | 2019-12-13 | 2020-02-14 | 武汉新芯集成电路制造有限公司 | Pull-up circuit |
| WO2022193181A1 (en) * | 2021-03-17 | 2022-09-22 | 华为技术有限公司 | Interface circuit and control method thereof, chip, terminal device |
| CN114625685A (en) * | 2022-03-01 | 2022-06-14 | 厦门智多晶科技有限公司 | IO circuit with hot plug function, chip and power supply control method of IO circuit |
| CN114625685B (en) * | 2022-03-01 | 2023-04-18 | 厦门智多晶科技有限公司 | IO circuit with hot plug function, chip and power supply control method of IO circuit |
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| Publication number | Publication date |
|---|---|
| CN104660242B (en) | 2018-04-27 |
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