CN104425344B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104425344B CN104425344B CN201310382881.3A CN201310382881A CN104425344B CN 104425344 B CN104425344 B CN 104425344B CN 201310382881 A CN201310382881 A CN 201310382881A CN 104425344 B CN104425344 B CN 104425344B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 172
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000926 separation method Methods 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 16
- -1 SiCN Inorganic materials 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 description 28
- 238000005530 etching Methods 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
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- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 3
- 229910001449 indium ion Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
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- 229910004541 SiN Inorganic materials 0.000 description 2
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- 238000001020 plasma etching Methods 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
A kind of semiconductor structure and forming method thereof, semiconductor structure, including：P type substrate, has N-type buried isolation regions in the P type substrate；P-type epitaxial layer in P type substrate, the p-type epitaxial layer includes first area and second area, and first area is located at N-type buried isolation regions top, and second area is around the first area；Ldmos transistor in the first area of p-type epitaxial layer；Cover the dielectric layer of the p-type epi-layer surface and ldmos transistor；Ring shaped conductive connector in the second area of dielectric layer and p-type epitaxial layer, the bottom of ring shaped conductive connector is in contact with N-type buried isolation regions；Positioned at the separation layer on ring shaped conductive plug sidewall surface；The first connector and the second connector in the dielectric layer on the first area of p-type epitaxial layer, the first connector are in contact with grid structure, and the second connector is in contact with source region or drain region.Semiconductor structure isolation effect of the invention is good, and device size is smaller.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
Power field effect pipe mainly includes vertical bilateral diffusion field-effect pipe VDMOS（Vertical Double-Diffused
MOSFET）With horizontal dual pervasion field effect pipe LDMOS（Lateral Double-Diffused MOSFET）Two types.Its
In, compared to vertical bilateral diffusion field-effect pipe VDMOS, horizontal dual pervasion field effect pipe LDMOS has many advantages, such as, for example, after
Person has more preferable heat endurance and frequency stability, gain higher and durability, lower feedback capacity and thermal resistance, and
Constant input impedance and simpler biasing circuit.
In the prior art, a kind of conventional N-type LDMOS transistor structure as shown in figure 1, including：Semiconductor substrate（In figure
It is not shown）, the p-well 100 in Semiconductor substrate；N-type drift region 101 in p-well 100；Positioned at N-type drift region 101
In fleet plough groove isolation structure 104, the fleet plough groove isolation structure 104 be used for increase ldmos transistor conducting path, with increase
The breakdown voltage of big ldmos transistor；Grid 105 in Semiconductor substrate, the grid floats across the p-well and N-type
Area 101 is moved, and part is located on fleet plough groove isolation structure 104；Source region 102 in the p-well of the side of grid 105, and be located at
The doping type in the drain region 103 in the N-type drift region of the opposite side of grid 105, source region 102 and drain region 103 is N-type.
But the isolation performance of existing ldmos transistor and other devices is poor and ldmos transistor and semiconductor
Isolation performance between substrate is also poor.
The content of the invention
The problem that the present invention is solved is to improve ldmos transistor with substrate and the isolation performance of other devices.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：P type substrate, institute are provided
State and be formed with N-type buried isolation regions in P type substrate；P-type epitaxial layer is formed in the P type substrate, the p-type epitaxial layer includes
First area and second area, first area are located at N-type buried isolation regions top, and second area is around the first area；
The first area of the p-type epitaxial layer forms ldmos transistor, and the ldmos transistor includes：Positioned at the of p-type epitaxial layer
N-type drift region in one region；The first fleet plough groove isolation structure in N-type drift region；Positioned at the firstth area of p-type epitaxial layer
Grid structure on domain, grid structure covering p-type epitaxial layer, the first fleet plough groove isolation structure, p-type epitaxial layer and the first shallow trench
N-type drift region between isolation structure；Source region in the p-type epitaxial layer of the side of grid structure；Positioned at grid structure
Drain region in the N-type drift region of opposite side；Form the dielectric layer of the covering p-type epi-layer surface and ldmos transistor, medium
Grid structure top surface of the surface of layer higher than ldmos transistor；Etch p-type epitaxial layer second area on dielectric layer and
The second area of p-type epitaxial layer, forms ring-shaped groove, and ring-shaped groove is around the first area of p-type epitaxial layer, and the annular ditch
Trench bottom exposes N-type buried isolation regions surface；Separation layer is formed in the both sides sidewall surfaces of the ring-shaped groove；Etching p-type
Dielectric layer on the first area of epitaxial layer, in the dielectric layer formed exposure grid structure top surface first through hole and
Exposure source region or second through hole on drain region surface；Full metal is filled in the ring-shaped groove, ring shaped conductive connector, annular is formed
The bottom of conductive plunger is in contact with N-type buried isolation regions, and full metal is filled in first through hole and the second through hole, forms first
Connector and the second connector.
Optionally, the separation layer thickness is 500~3000 angstroms.
Optionally, the material of the separation layer is SiO2, one or more in SiN, SiON, SiCN, SiC.
Optionally, the material of the metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Optionally, in first through hole, the second through hole and the ring-shaped groove before the full metal of filling, the first through hole and the
Insulation surface forms diffusion impervious layer in the side wall and ring-shaped groove of two through holes.
Optionally, the material of the diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
Optionally, the depth of the ring-shaped groove is 3~6 microns, and the width of ring-shaped groove is 0.6~1.2 micron.
Optionally, the ring-shaped groove part is located in N-type buried isolation regions.
Optionally, the depth of the part-toroidal groove in N-type buried isolation regions is 0.5~1 micron.
Optionally, the formation process of the N-type buried isolation regions be ion implanting, in N-type buried isolation regions N-type impurity from
The concentration of son is 1E18atom/cm3~2E21atom/cm3。
Optionally, the second area of the p-type epitaxial layer is also formed with the second fleet plough groove isolation structure, the ring-shaped groove
Through the second fleet plough groove isolation structure..
Present invention also offers a kind of semiconductor structure, including：P type substrate, in the P type substrate have N-type bury every
From area；P-type epitaxial layer in P type substrate, the p-type epitaxial layer includes first area and second area, first area position
In N-type buried isolation regions top, second area is around the first area；LDMOS in the first area of p-type epitaxial layer
Transistor, the ldmos transistor includes：N-type drift region in the first area of p-type epitaxial layer；Positioned at N-type drift region
In the first fleet plough groove isolation structure；Grid structure on the first area of p-type epitaxial layer, outside grid structure covering p-type
Prolong the N-type drift region between layer, the first fleet plough groove isolation structure, p-type epitaxial layer and the first fleet plough groove isolation structure；Positioned at grid
Source region in the p-type epitaxial layer of the side of structure；Drain region in the N-type drift region of the opposite side of grid structure；Covering institute
State the dielectric layer of p-type epi-layer surface and ldmos transistor, the grid structure top of the surface higher than ldmos transistor of dielectric layer
Portion surface；Dielectric layer on the second area of p-type epitaxial layer and the ring shaped conductive in the second area of p-type epitaxial layer are inserted
Plug, the bottom of ring shaped conductive connector is in contact with N-type buried isolation regions；Positioned at the separation layer on ring shaped conductive plug sidewall surface；
The first connector and the second connector in the dielectric layer on the first area of p-type epitaxial layer, the first connector and grid structure phase
Contact, the second connector is in contact with source region or drain region.
Optionally, the separation layer thickness is 500~3000 angstroms, and the material of the separation layer is SiO2、SiN、SiON、
One or more in SiCN, SiC.
Optionally, the material of the ring shaped conductive connector, the first connector and the second connector be metal, the metal be W,
One or more in Al, Cu, Ti, Ag, Au, Pt, Ni.
Optionally, between first connector and the second connector and dielectric layer and ring shaped conductive connector and separation layer it
Between also have diffusion impervious layer.
Optionally, the material of the diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
Optionally, the ring shaped conductive plug section is located in N-type buried isolation regions.
Optionally, the depth of the part-toroidal conductive plunger in N-type buried isolation regions is 0.5~1 micron
Optionally, the concentration of N-type impurity ion is 1E18atom/cm in N-type buried isolation regions3~1E22atom/cm3。
Optionally, the second area of the p-type epitaxial layer also has the second fleet plough groove isolation structure, and the ring shaped conductive is inserted
Plug runs through second fleet plough groove isolation structure.
Compared with prior art, technical scheme has advantages below：
Semiconductor structure of the invention, with the isolation junction that separation layer and ring shaped conductive connector, N-type buried isolation regions are constituted
Structure, separation layer realizes the lateral isolation of the semiconductor devices outside the ldmos transistor formed in first area and first area, ring
Shape conductive plunger is in contact with N-type buried isolation regions, and positive voltage is applied to N-type buried isolation regions by ring shaped conductive connector, is made
PN junction between N-type buried isolation regions and P type substrate is reverse-biased, realize longitudinal direction between ldmos transistor and P type substrate every
From, isolation effect is improve by lateral isolation and longitudinal direction isolation, and the material of ring shaped conductive connector is metal, and its resistance is non-
Often small, the efficiency that ring shaped conductive connector absorbs carrier is improved, and effectively prevents crosstalk noise, and lateral isolation uses separation layer in addition
Isolation, compared to the isolation of existing PN junction, the volume very little that separation layer isolation is occupied improves the integrated level of device.
Further, the separation layer thickness is 500~3000 angstroms, and the material of the separation layer is SiO2、SiN、SiON、
One or more in SiCN, SiC so that the separation layer in the small volume for occupying simultaneously, be operated in ldmos transistor
Isolation effect under high voltage is preferable.
The forming method of semiconductor structure of the invention, ring shaped conductive plug material is metal, the system of ring shaped conductive connector
Work can be mutually compatible with the connector manufacture craft of back segment, saves processing step, and manufacture craft is simple.
Brief description of the drawings
Fig. 1 is the cross-sectional view of prior art ldmos transistor；
Fig. 2~Fig. 8 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
Specific embodiment
Ldmos transistor is power device, therefore can apply high voltage during ldmos transistor work, therefore in order to
Ensure the normal work of other low-voltage devices of formation in Semiconductor substrate, it usually needs ldmos transistor is served as a contrast with semiconductor
Other devices on bottom are isolated.Fig. 1 is refer to, existing isolation method is typically to form N-type shading ring in p-well 100
106, N-type shading ring 106 is formed by ion implanting, and positive voltage is applied on N-type shading ring 106 so that N-type shading ring 106 and P
Occur reverse-biased between trap 100, so that ldmos transistor separates with the device of surrounding, prevent the big electricity produced under high voltage
Generation influence of the stream horizontal proliferation on peripheral devices.
In order to ensure the isolation effect of N-type shading ring 106, N-type shading ring 106 needs deeper depth and doping higher
Concentration, but above-mentioned N-type shading ring 106 is formed by ion implanting, when the depth of N-type shading ring 106 is deeper, ion implanting
Method be difficult to ensure that concentration higher in deeper N-type shading ring 106, this is accomplished by increasing the laterally wide of N-type shading ring 106
Degree can like this cause that the volume that N-type shading ring 106 is occupied increases to keep its isolation, be unfavorable for device integration
Improve.
In addition, 106 pairs of isolation effects of transverse direction of N-type shading ring are substantially, but the effect of its isolation to longitudinal direction has very much
Limit.
Therefore, the invention provides a kind of semiconductor structure and forming method thereof, the semiconductor structure uses ring shaped conductive
The isolation structure that connector and separation layer, N-type buried isolation regions are constituted, realizes other devices on ldmos transistor and substrate
Lateral isolation and longitudinal direction isolate, and isolation effect is good, and lateral isolation mode using ring shaped conductive connector and separation layer is occupied
Volume it is smaller.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general ratio
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.Additionally, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 2~Fig. 8 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
First, refer to Fig. 2, there is provided P type substrate 200, N-type buried isolation regions 203 are formed with the P type substrate 200；
P-type epitaxial layer 201 is formed in the P type substrate 200, the p-type epitaxial layer 201 includes first area 21 and second area
22, first area 21 is located at the top of N-type buried isolation regions 203, and second area 22 is around the first area 21.
The material of the P type substrate 200 is silicon（Si）, germanium（Ge）Or SiGe（GeSi）, carborundum（SiC）Or it is other
Semi-conducting material, in the present embodiment, the material of the N-type substrate 201 is silicon.
Doped with the foreign ion of p-type in P type substrate 200, the p type impurity ion is boron ion, gallium ion, indium ion
In one or more.
N-type buried isolation regions 203 are formed with the P type substrate 200, the N-type buried isolation regions 203 are used for follow-up shape
Into ldmos transistor and P type substrate 200 between longitudinal direction isolate, ldmos transistor work when, in N-type buried isolation regions
During 203 applying positive voltage, PN junction is reverse-biased between N-type buried isolation regions 203 and the substrate of P type substrate 200, realizes that N-type buries isolation
Isolating between area 203 and P type substrate.
The N-type buried isolation regions 203 by carrying out N-type ion implanting to P type substrate 200, the N-type ion be phosphorus from
One or more in son, arsenic ion, antimony ion.The concentration of N-type impurity ion is larger in N-type buried isolation regions so that N-type is covered
Bury and be easy to that PN junction is reverse-biased between isolated area 203 and P type substrate 200, and junction depth when reverse-biased is larger, to improve longitudinal isolation
Performance, the N-type ion concentration in the N-type buried isolation regions 203 is 1E18atom/cm3~2E21atom/cm3, such as：
1E19atom/cm3、2E19atom/cm3、1E20atom/cm3、9E20atom/cm3Deng.
P-type epitaxial layer 201 is formed with the P type substrate 200, p-type epitaxial layer 201 includes the area of first area 21 and second
Domain 22, second area 22 is located at centre around the first area 21, i.e. first area 21, and second area 22 is located at edge, institute
First area 21 is stated positioned at the surface of N-type mask separation layer 203, the area of first area 21 is less than or is slightly less than N-type mask
The area of separation layer 203, is subsequently formed ldmos transistor in the first area 21 of p-type epitaxial layer 201, in second area 22 after
The continuous isolation structure for forming annular（Separation layer and ring shaped conductive connector）.
The p-type epitaxial layer 201 is formed by epitaxy technique, the doped p-type impurity in situ when p-type epitaxial layer is epitaxially formed
Ion, the p type impurity ion is one or more in boron ion, gallium ion, indium ion.
The material of p-type epitaxial layer 201 is identical with the material of P type substrate or differs, in the present embodiment, the p-type extension
The material of layer 201 is silicon.
Then, Fig. 3 is refer to, ldmos transistor is formed in the first area 21 of the p-type epitaxial layer 201, it is described
Ldmos transistor includes：N-type drift region 209 in the first area 21 of p-type epitaxial layer 201；Positioned at N-type drift region 209
In the first fleet plough groove isolation structure 206；Grid structure 212 on the first area 21 of p-type epitaxial layer 201, grid knot
The covering p-type of structure 212 epitaxial layer 201, the first fleet plough groove isolation structure 206, the fleet plough groove isolation structure of p-type epitaxial layer 201 and first
N-type drift region 209 between 206；Source region 213 in the p-type epitaxial layer 201 of the side of grid structure 212；Positioned at grid
Drain region 214 in the N-type drift region 209 of the opposite side of structure 212.
The detailed process that the ldmos transistor is formed is：The shape first in the first area 21 of the p-type epitaxial layer 201
Into the first fleet plough groove isolation structure 206；Then the first N-type ion implanting is carried out to the Semiconductor substrate, N-type drift region is formed
209, the N-type drift region 209 surrounds first fleet plough groove isolation structure 206, and the foreign ion of the first N-type ion implanting is
One or more in phosphonium ion, arsenic ion, antimony ion；Then grid knot is formed on the first area 21 of p-type epitaxial layer 201
Structure 212, the covering p-type of grid structure 212 epitaxial layer 201, the first fleet plough groove isolation structure 206, p-type epitaxial layer 201 and first are shallow
N-type drift region 209 between groove isolation construction 206, the grid structure 212 is including gate dielectric layer 211, positioned at gate dielectric layer
Gate electrode 210 and positioned at gate dielectric layer 211 and the side wall of the side wall of gate electrode 210 on 211；The second N-type ion implanting is carried out,
Source region 216 in the p-type epitaxial layer 201 of grid structure 212 and the side of side wall, in the another of grid structure 212 and side wall
Drain region 214 in the N-type drift region 209 of side, the foreign ion of the second N-type ion implanting is in phosphonium ion, arsenic ion, antimony ion
One or more；After carrying out N shapes ion implanting and p-type ion implanting, in addition it is also necessary to annealed, to activate Doped ions, institute
The time for stating annealing is 20~30 seconds, and the temperature of annealing is more than 1000 degrees Celsius.
The material of the gate dielectric layer 211 is silica, and the material of gate electrode 210 is polysilicon.The gate dielectric layer 211
Material can also be high-k dielectric material, the material of the corresponding gate electrode 210 is metal.
The side wall can be the stacked structure of single or multiple lift.
First fleet plough groove isolation structure 206 as ldmos transistor a part, for increase source region 213 and leakage
The path length of the source and drain circuit produced between area 214.The grid structure 212 can cover the first fleet plough groove isolation structure
206 part or all of surface, in the present embodiment, the grid structure 212 covers first fleet plough groove isolation structure 206
At least half of surface.
Be also formed with p-type isolated area 217 between the N-type drift region 209 and N shapes buried isolation regions 203, the p-type every
The electric isolation that absciss layer is used between N-type drift region 209 and N shapes buried isolation regions 203, p-type isolated area 217 is forming N-type drift
Before or after moving area 209, formed by deep doped p-type ion implanting.
PXing Ti areas 216 are also formed with the p-type epitaxial layer of the side of the grid structure 212, source region 213 is located at PXing Ti areas
In 216, the PXing Ti areas 216 are used to adjust the threshold voltage of ldmos transistor, and can reduce parasitic triode effect, improve
The source and drain breakdown voltage of ldmos transistor.The PXing Ti areas 216 are formed after grid structure is formed by p-type ion implanting.
Be formed with the second fleet plough groove isolation structure 204 in the second area 22 of the p-type epitaxial layer 201, the second shallow trench every
From structure 204 around the first area 22 of the p-type epitaxial layer 201, the ring shaped conductive connector being subsequently formed runs through the second shallow ridges
Recess isolating structure 204, the second fleet plough groove isolation structure 204 improves the doped region in ring shaped conductive connector and p-type epitaxial layer
Electric isolation performance.Second fleet plough groove isolation structure 204 can be with the same step shape of the first fleet plough groove isolation structure 206
Into.
The p-type epitaxial layer 201 is also formed with the 3rd fleet plough groove isolation structure 207, the 3rd shallow trench in first area 21
Around the ldmos transistor, the 3rd fleet plough groove isolation structure 207 is used for what first area 21 was formed to isolation structure 207
Body adulterates ring 208 and isolating between the source region 213 of ldmos transistor and drain region 214.The body doping ring 208 is around described
Ldmos transistor（Or the 3rd fleet plough groove isolation structure 207）, the body doping ring 208 is used to connect earth terminal or negative voltage, anti-
The only generation of latch-up, and current potential to the channel region of the bottom of grid structure 212 is adjusted.Adulterated in body doping ring 208
Foreign ion type be p-type, body doping ring 208 formed by p-type ion implanting, the foreign ion of p-type ion implanting is
One or more in boron ion, gallium ion or indium ion.3rd fleet plough groove isolation structure 207 can be with the first shallow trench
The same step of isolation structure 206 is formed.
P-type shading ring 215 is also formed with the second area 22 of the p-type epitaxial layer 201, p-type shading ring 215 is around described
Second fleet plough groove isolation structure 204, the p-type shading ring 215 is grounded, in the first area 21 of p-type epitaxial layer 201
The electric isolation of the semiconductor devices in ldmos transistor and p-type epitaxial layer 201 in other regions.The p-type shading ring 215,
Body doping ring 208 and PXing Ti areas 216 can be formed by the p-type ion implantation technology of same step.It should be noted that institute
State p-type shading ring 215, body doping ring 208 and PXing Ti areas 216 can also be by the p-type ion implantation technology shape of different step
Into.
The 4th fleet plough groove isolation structure 205 is also formed with the second area 22 of the p-type epitaxial layer 201, the described 4th is shallow
Groove isolation construction 205 is used for p-type shading ring 215 in P around the p-type shading ring 215, the 4th fleet plough groove isolation structure 205
Isolation between other active areas of the second area 22 of type epitaxial layer 201.4th fleet plough groove isolation structure 205 can be with
The same step of one fleet plough groove isolation structure 206 is formed.
First fleet plough groove isolation structure 206, the second fleet plough groove isolation structure 204, the 3rd fleet plough groove isolation structure 207
Or the 4th fleet plough groove isolation structure 205 material be SiO2, SiN, SiON, SiCN or SiC.In the present embodiment, described first is shallow
Groove isolation construction 206, the second fleet plough groove isolation structure 204, the 3rd fleet plough groove isolation structure 207 or the 4th shallow trench isolation junction
The material of structure 205 is SiO2。
With reference to Fig. 4, the dielectric layer 218 of the covering surface of p-type epitaxial layer 201 and ldmos transistor, dielectric layer are formed
Grid structure 210 top surface of 218 surface higher than ldmos transistor.
The material of the dielectric layer 218 is SiO2, SiN, SiON, SiCN, SiC or low-K dielectric constant material etc..Dielectric layer
218 can be formed by chemical vapor deposition method.
The dielectric layer 218 can be single or multiple lift stacked structure.
With reference to Fig. 5, second of dielectric layer 218 and p-type epitaxial layer 201 on the second area 22 of etching p-type epitaxial layer 201
Region 22, forms ring-shaped groove 219, and ring-shaped groove 219 is around the first area 21 of p-type epitaxial layer 301, and the ring-shaped groove
219 bottom-exposeds go out the surface of N-type buried isolation regions 203.
Needed to form mask layer on the dielectric layer 218 before the dielectric layer 218 is etched（Not shown in figure）, institute
Stating mask layer has the opening on exposure dielectric layer 218 surface, the width of the width of the opening and position with ring-shaped groove and position
Put corresponding.
The ring-shaped groove 219 is formed by two step etching technics, including the first plasma etching industrial and the second grade from
Sub- etching technics, first using the first plasma etch process etch media layer 218 and the second fleet plough groove isolation structure 204,
The first sub-trenches are formed, it is fluoro-gas that the first plasma etch process uses gas, such as CF4Or C3F8Deng；Then, edge
The first sub-trenches, using the first plasma etch process etching p-type epitaxial layer 201, the is formed in p-type epitaxial layer 201
Two sub-trenches, the first sub-trenches and the second sub-trenches constitute ring-shaped groove 219, the first plasma etch process use gas for
Chloride or bromine-containing gas, such as Cl2Or HBr etc..
In other embodiments of the invention, it would however also be possible to employ a step etching technics forms the ring-shaped groove.
Ring-shaped groove 219 is formed in the second area 22 of the p-type epitaxial layer 201, ring-shaped groove 219 is outside p-type
Prolong the first area 21 of layer 201, and the bottom-exposed of the ring-shaped groove 219 goes out the surface of N-type buried isolation regions 203, ring-shaped groove
Separation layer is subsequently formed on 219 side wall, subsequently filling metal forms ring shaped conductive connector, ring shaped conductive to ring-shaped groove 219
The bottom of connector is connected with N-type buried isolation regions 203, and positive electricity is applied to N-type buried isolation regions 203 by ring shaped conductive connector
Pressure so that the PN junction between N-type buried isolation regions 203 and P type substrate 200 is reverse-biased, realizes ldmos transistor and P type substrate 200
Between longitudinal direction isolation.
In other embodiments of the invention, the ring-shaped groove part is located in N-type buried isolation regions, i.e., in etching P
During type epitaxial layer, N-type buried isolation regions described in over etching so that the depth of the ring-shaped groove of formation increases, therefore it is follow-up in ring
When forming ring shaped conductive connector in shape groove so that ring shaped conductive connector can be fully contacted with N-type buried isolation regions, prevent two
The phenomenons such as loose contact are produced on the contact surface of person.
The depth that the ring-shaped groove is located at the part in N-type buried isolation regions is 0.5~1 micron, makes to form annular ditch
The ring shaped conductive connector formed in groove can contact best results with N-type buried isolation regions.
The depth of the ring-shaped groove 219 is 3~6 microns, and the width of ring-shaped groove 219 is 0.6~1.2 micron, is compared
In existing PN junction as lateral isolation, the horizontal stroke that separation layer and ring shaped conductive connector are constituted is formed subsequently in ring-shaped groove 219
To isolation structure, it has smaller device size, is conducive to improving the integrated level of device.
Then, Fig. 6 is refer to, separation layer 220 is formed in the both sides sidewall surfaces of the ring-shaped groove 219.
Separation layer 220 is formed in the side both sides side wall of ring-shaped groove 219 so that separation layer 220 is also around p-type epitaxial layer 201
First area 21, the separation layer 220 is used for the electric isolation of the conductive plunger that is subsequently formed and p-type epitaxial layer 201, described
Separation layer 220 is additionally operable to the transverse direction of the semiconductor devices outside the ldmos transistor formed in first area 21 and first area 21
Isolation.
The thickness of the separation layer 220 is 500~3000 angstroms, and the material of the separation layer 220 is insulating materials, specific institute
The material for stating separation layer 220 is SiO2, one or more in SiN, SiON, SiCN, SiC so that the separation layer is being occupied
Small volume simultaneously, it is preferable in ldmos transistor work isolation effect under high voltages.
The separation layer 220 can be single or multiple lift stacked structure.
The forming process of the separation layer 220 is：Using depositing operation the ring-shaped groove 219 side wall and bottom table
The surface of face and p-type epitaxial layer 201 forms spacer material layer；The spacer material layer is etched using without mask etching technique,
The surface of removal p-type epitaxial layer 201 and the spacer material layer of the lower surface of ring-shaped groove 219, in the ring-shaped groove 219
Both sides side wall forms separation layer 220.
Then, Fig. 7, the dielectric layer 218 on the first area 21 of etching p-type epitaxial layer 201, in dielectric layer 218 be refer to
It is middle to form exposure grid structure（Gate electrode 210）The first through hole 221 and exposure source region 213 or the table of drain region 214 of top surface
Second through hole 222 in face.
Before the dielectric layer 218 is etched, mask layer, mask material filling are formed on the surface of the dielectric layer 218
Ring-shaped groove 219, the mask layer has some openings on exposure dielectric layer 218 surface.The mask material can be light
Photoresist.
Etch the dielectric layer 218 and use fluorine-containing plasma etching.
In the present embodiment, during etch media layer 218, third through-hole 223 and four-way can also be formed in dielectric layer 218
Hole 224, the third through-hole 223 exposes the surface of body doping ring 208, and the fourth hole 224 exposes p-type shading ring
215 surface.
Finally, Fig. 8 is refer to, in the ring-shaped groove 219（With reference to Fig. 7）The middle full metal of filling, forms ring shaped conductive and inserts
Plug 225, the bottom of ring shaped conductive connector 225 is in contact with N-type buried isolation regions 203, in the through hole of first through hole 221 and second
222（With reference to Fig. 7）The middle full metal of filling, forms the first connector 226 and the second connector 227, the first connector 226 and grid structure
（Gate electrode 210）It is in contact, the second connector 227 is in contact with source region 213 or drain region 214.
The forming process of the ring shaped conductive connector 225, the first connector 226 and the second connector 227 is：In the dielectric layer
Metal level is formed on 218（Not shown in figure）, layer filling full ring-shaped groove 219, the through hole 222 of first through hole 221 and second；
The metal level is planarized until exposing the surface of dielectric layer 218, ring shaped conductive connector 204 is formed in ring-shaped groove 219,
The first connector 226 and the second connector 227 are formed in the through hole 222 of first through hole 221 and second.
Forming ring shaped conductive connector 225, the first connector 226 and the second connector 227 simultaneously, in third through-hole 223 and the
Four through holes 224（With reference to Fig. 7）It is middle to form the 3rd connector 228 and the 4th connector 229, the 3rd connector 228 and body doping ring 208
It is in contact, the 4th connector 229 is in contact with p-type shading ring 215.
The material of the metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.Used in the present embodiment
Metal is W.
Also include：Before full metal is filled in ring-shaped groove 219, the through hole 222 of first through hole 221 and second, described first
Insulation surface forms diffusion impervious layer in the side wall and ring-shaped groove 219 of the through hole 222 of through hole 221 and second（Do not show in figure
Go out）, the diffusion impervious layer is used to prevent metallic atom in connector from being spread in dielectric layer 218 and in separation layer 220.
The material of the diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.The diffusion impervious layer can be with
It is Ti and TiN double-deckers or the double-decker of Ta and TaN.
The ring shaped conductive connector 204 is electrically connected with N-type buried isolation regions 203, can be to by ring shaped conductive connector 204
N-type buried isolation regions 203 apply positive voltage so that the PN junction constituted between N-type buried isolation regions 203 and P type substrate 200 is anti-
Partially, so as to realize isolating the longitudinal direction formed in follow-up first area 21 between ldmos transistor and P type substrate 200, prevent
High voltage and high current when ldmos transistor works are produced by P type substrate 200 to the semiconductor devices outside first area 21
Influence.
The material of ring shaped conductive connector 204 is metal, and making for ring shaped conductive connector 204 can make work with the connector of back segment
Skill is mutually compatible, saves processing step, and manufacture craft is simple, also, because the resistance of metal material is very low, annular is led
The efficiency that electric plug 204 absorbs carrier is improved, and effectively prevents crosstalk noise, in addition, by ring shaped conductive connector 204 and isolation
Layer 220 constitutes isolation structure and causes that existing lateral isolation becomes insulating materials and isolates from PN junction isolation, the size reduction of device,
Improve integrated level.
Above-mentioned ldmos transistor operationally, applies operating voltage, source region 213 and body doping ring 208 on gate electrode 210
Ground connection or negative voltage, positive voltage is applied on drain region 214 and ring shaped conductive connector 204.
The semiconductor structure that above-mentioned direction is formed, refer to Fig. 8, including：
P type substrate 200, has N-type buried isolation regions 203 in the P type substrate 200；
P-type epitaxial layer 201 in P type substrate 200, the p-type epitaxial layer 201 includes the area of first area 21 and second
Domain 22, first area 21 is located at the top of N-type buried isolation regions 203, and second area 22 is around the first area 21；
Ldmos transistor in the first area 21 of p-type epitaxial layer 201, the ldmos transistor includes：Positioned at P
N-type drift region 209 in the first area 21 of type epitaxial layer 201；The first shallow trench isolation junction in N-type drift region 209
Structure 206；Grid structure on the first area 21 of p-type epitaxial layer 201, grid structure covering p-type epitaxial layer 201, first
N-type drift region 209 between fleet plough groove isolation structure 206, the fleet plough groove isolation structure 203 of p-type epitaxial layer 201 and first；It is located at
Source region 213 in the p-type epitaxial layer 201 of the side of grid structure；In the N-type drift region 209 of the opposite side of grid structure
Drain region 214；
The dielectric layer 218 of the surface of p-type epitaxial layer 301 and ldmos transistor is covered, the surface of dielectric layer 218 is higher than
The grid structure top surface of ldmos transistor；
Dielectric layer 218 on the second area 22 of p-type epitaxial layer 201 and in the second area 22 of p-type epitaxial layer 201
Ring shaped conductive connector 225, the bottom of ring shaped conductive connector 225 is in contact with N-type buried isolation regions 203；
Positioned at the separation layer 220 of the sidewall surfaces of ring shaped conductive connector 225；
The first connector 226 and the second connector in the dielectric layer 218 on the first area 21 of p-type epitaxial layer 201
227, the first connector 226 is in contact with grid structure, and the second connector 227 is in contact with source region 213 or drain region 215.
Specifically, the thickness of the separation layer 220 is 500~3000 angstroms, the material of the separation layer is SiO2、SiN、
One or more in SiON, SiCN, SiC.
The material of the ring shaped conductive connector 225, the first connector 226 and the second connector 227 be metal, the metal be W,
One or more in Al, Cu, Ti, Ag, Au, Pt, Ni.
Between the connector 227 of first connector 226 and second and dielectric layer 218 and ring shaped conductive connector 225 and isolate
Also there is diffusion impervious layer between layer 220.
The material of the diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
In other embodiments of the invention, the ring shaped conductive plug section is located in N-type buried isolation regions, positioned at N
The depth of the part-toroidal conductive plunger in type buried isolation regions is 0.5~1 micron.
The concentration of N-type impurity ion is 1E18atom/cm in N-type buried isolation regions 2033~1E22atom/cm3。
The second area 22 of the p-type epitaxial layer 20 also has the second fleet plough groove isolation structure 204, and the ring shaped conductive is inserted
225 plugs run through second fleet plough groove isolation structure 204.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
P type substrate is provided, N-type buried isolation regions are formed with the P type substrate；
P-type epitaxial layer is formed in the P type substrate, the p-type epitaxial layer includes first area and second area, first area
Positioned at N-type buried isolation regions top, second area is around the first area；
Ldmos transistor is formed in the first area of the p-type epitaxial layer, the ldmos transistor includes：Positioned at p-type extension
N-type drift region in the first area of layer；The first fleet plough groove isolation structure in N-type drift region；Positioned at p-type epitaxial layer
Grid structure on first area, grid structure covering p-type epitaxial layer, the first fleet plough groove isolation structure, p-type epitaxial layer and first
N-type drift region between fleet plough groove isolation structure；Source region in the p-type epitaxial layer of the side of grid structure；Positioned at grid
Drain region in the N-type drift region of the opposite side of structure；
The dielectric layer of the covering p-type epi-layer surface and ldmos transistor is formed, the surface of dielectric layer is higher than LDMOS crystal
The grid structure top surface of pipe；
The second area of the dielectric layer and p-type epitaxial layer on the second area of p-type epitaxial layer is etched, ring-shaped groove, annular is formed
Groove is around the first area of p-type epitaxial layer, and the ring-shaped groove bottom-exposed goes out N-type buried isolation regions surface, by ring
Shape conductive plunger applies positive voltage to N-type buried isolation regions so that the PN junction between N-type buried isolation regions and P type substrate is reverse-biased,
Realize that the longitudinal direction between ldmos transistor and P type substrate isolates；
Separation layer is formed in the both sides sidewall surfaces of the ring-shaped groove；
The dielectric layer on the first area of p-type epitaxial layer is etched, the of exposure grid structure top surface is formed in the dielectric layer
One through hole and second through hole on exposure source region or drain region surface；
Full metal is filled in the ring-shaped groove, ring shaped conductive connector is formed, bottom and the N-type of ring shaped conductive connector bury every
It is in contact from area, full metal is filled in first through hole and the second through hole, forms the first connector and the second connector.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the separation layer thickness is 500~
3000 angstroms.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the separation layer is SiO2、
One or more in SiN, SiON, SiCN, SiC.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the metal be W, Al,
One or more in Cu, Ti, Ag, Au, Pt, Ni.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first through hole, the second through hole and
Before full metal is filled in ring-shaped groove, the separation layer table in the side wall and ring-shaped groove of the first through hole and the second through hole
Face forms diffusion impervious layer.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the material of the diffusion impervious layer is
One or more in Ti, Ta, TiN, TaN.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the depth of the ring-shaped groove is 3
~6 microns, the width of ring-shaped groove is 0.6~1.2 micron.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the ring-shaped groove part is located at N
In type buried isolation regions.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that in N-type buried isolation regions
The depth of part-toroidal groove is 0.5~1 micron.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the shape of the N-type buried isolation regions
It is ion implanting into technique, the concentration of N-type impurity ion is 1E18atom/cm in N-type buried isolation regions3~2E21atom/cm3。
The forming method of 11. semiconductor structures as claimed in claim 1, it is characterised in that the secondth area of the p-type epitaxial layer
Domain is also formed with the second fleet plough groove isolation structure, and the ring-shaped groove runs through the second fleet plough groove isolation structure.
A kind of 12. semiconductor structures, it is characterised in that including：
P type substrate, has N-type buried isolation regions in the P type substrate；
P-type epitaxial layer in P type substrate, the p-type epitaxial layer includes first area and second area, and first area is located at
N-type buried isolation regions top, second area is around the first area；
Ldmos transistor in the first area of p-type epitaxial layer, the ldmos transistor includes：Positioned at p-type epitaxial layer
First area in N-type drift region；The first fleet plough groove isolation structure in N-type drift region；Positioned at the of p-type epitaxial layer
Grid structure on one region, grid structure covering p-type epitaxial layer, the first fleet plough groove isolation structure, p-type epitaxial layer and first are shallow
N-type drift region between groove isolation construction；Source region in the p-type epitaxial layer of the side of grid structure；Positioned at grid knot
Drain region in the N-type drift region of the opposite side of structure；
The dielectric layer of the p-type epi-layer surface and ldmos transistor is covered, the surface of dielectric layer is higher than ldmos transistor
Grid structure top surface；
Dielectric layer on the second area of p-type epitaxial layer and the ring shaped conductive connector in the second area of p-type epitaxial layer, ring
The bottom of shape conductive plunger is in contact with N-type buried isolation regions, and positive electricity is applied to N-type buried isolation regions by ring shaped conductive connector
Pressure so that the PN junction between N-type buried isolation regions and P type substrate is reverse-biased, realizes vertical between ldmos transistor and P type substrate
To isolation；
Positioned at the separation layer on ring shaped conductive plug sidewall surface；
The first connector and the second connector in the dielectric layer on the first area of p-type epitaxial layer, the first connector and grid knot
Structure is in contact, and the second connector is in contact with source region or drain region.
13. semiconductor structures as claimed in claim 12, it is characterised in that the separation layer thickness is 500~3000 angstroms, institute
The material for stating separation layer is SiO2, one or more in SiN, SiON, SiCN, SiC.
14. semiconductor structures as claimed in claim 12, it is characterised in that the ring shaped conductive connector, the first connector and
The material of two connectors is metal, and the metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
15. semiconductor structures as claimed in claim 12, it is characterised in that first connector and the second connector and dielectric layer
Between and ring shaped conductive connector and separation layer between also have diffusion impervious layer.
16. semiconductor structures as claimed in claim 15, it is characterised in that the material of the diffusion impervious layer be Ti, Ta,
One or more in TiN, TaN.
17. semiconductor structures as claimed in claim 12, it is characterised in that the ring shaped conductive plug section is covered positioned at N-type
In burying isolated area.
18. semiconductor structures as claimed in claim 17, it is characterised in that the part-toroidal in N-type buried isolation regions
The depth of conductive plunger is 0.5~1 micron.
19. semiconductor structures as claimed in claim 12, it is characterised in that N-type impurity ion is dense in N-type buried isolation regions
It is 1E18atom/cm to spend3~1E22atom/cm3。
20. semiconductor structures as claimed in claim 12, it is characterised in that the second area of the p-type epitaxial layer also has
Second fleet plough groove isolation structure, the ring shaped conductive connector runs through second fleet plough groove isolation structure.
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| US6118152A (en) * | 1997-11-05 | 2000-09-12 | Denso Corporation | Semiconductor device and method of manufacturing the same |
| CN101728392A (en) * | 2008-10-22 | 2010-06-09 | 台湾积体电路制造股份有限公司 | High voltage device having reduced on-state resistance |
| CN102037562A (en) * | 2008-02-27 | 2011-04-27 | 先进模拟科技公司 | Isolated transistors and diodes and isolation and termination structures for semiconductor die |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6118152A (en) * | 1997-11-05 | 2000-09-12 | Denso Corporation | Semiconductor device and method of manufacturing the same |
| CN102037562A (en) * | 2008-02-27 | 2011-04-27 | 先进模拟科技公司 | Isolated transistors and diodes and isolation and termination structures for semiconductor die |
| CN101728392A (en) * | 2008-10-22 | 2010-06-09 | 台湾积体电路制造股份有限公司 | High voltage device having reduced on-state resistance |
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